Clock generation circuit, interface conversion circuit and server

Abstract

The utility model relates to the technical field of servers, in particular to a clock generation circuit, an interface conversion circuit and a server. According to the clock generation circuit, a signal delay control unit and a clock generation unit are arranged, when a first processing unit generates a PCIE3.0 clock signal, a PCIE4.0 clock trigger signal CPUC10GATE-is generated, after the PCIE4.0 clock trigger signal CPUC10GATE-passes through the signal delay control unit, the time of the PCIE4.0 clock trigger signal CPUC10GATE-is delayed, and then the clock generation unit is triggered to generate the PCIE4.0 clock signal. The power-on time sequence output by the PCIE4.0 clock signal is controlled, so that the interference between the PCIE3.0 clock signal and the PCIE4.0 clock signal is avoided, and the clock generation circuit can generate the stable and reliable PCIE4.0 clock signal.

Description

Technical Field

[0001] The embodiment of the utility model relates to the technical field of servers, and in particular to a clock generating circuit, an interface conversion circuit and a server. Background Art

[0002] At present, embedded GPU computing platform products are widely used in application fields such as machine vision, deep learning, AI and edge computing, vehicle-road collaboration and assisted driving. In embedded GPU computing platform products, the CPU and GPU as well as peripheral chips need to work together and need to be connected to peripheral circuits through PCIE interface circuits.

[0003] The inventors of this application have discovered during their research that, in actual applications, the performance of embedded GPU computing platform products is closely related to the performance of the CPU and GPU themselves, on the one hand, and to the compatibility between the CPU, GPU and interface circuits, on the other hand. The performance limitations of any one part will affect the overall performance of the product.

[0004] Therefore, how to achieve adaptation between CPU, GPU and interface circuit becomes very important. Utility Model Content

[0005] In view of the above problems, the embodiments of the present utility model provide a clock generation circuit, an interface conversion circuit and a server, which are used to solve the above technical problems existing in the prior art.

[0006] According to one aspect of an embodiment of the present application, a clock generating circuit is provided, comprising: a first processing unit, a signal delay control unit and a clock generating unit; the first processing unit comprises a control signal output port, and the control signal output port is electrically connected to the signal delay control unit; the signal delay control unit comprises a MOS tube and a Schmitt trigger, the Schmitt trigger comprises an input end and an output end, the control signal output port is electrically connected to the input end of the Schmitt trigger through the MOS tube, the output end of the Schmitt trigger is electrically connected to the clock generating unit, and the Schmitt trigger is used to delay the control signal output by the control signal output port; the clock generating unit comprises an enable control end and a clock signal output end, the enable control end is electrically connected to the output end of the Schmitt trigger, and outputs the clock signal through the clock signal output end.

[0007] In some embodiments, the MOS transistor is an N-channel MOS transistor Q1; a gate of the N-channel MOS transistor Q1 is electrically connected to the control signal output port, a source of the N-channel MOS transistor Q1 is grounded, and a drain of the N-channel MOS transistor Q1 is electrically connected to the input end of the Schmitt trigger.

[0008] In some embodiments, the input terminal of the Schmitt trigger is grounded via a filter capacitor C14.

[0009] In some embodiments, the clock generating unit further includes a pull-up resistor R13; one end of the pull-up resistor is electrically connected to the enable control end, and the other end of the pull-up resistor is grounded.

[0010] In some embodiments, the clock generating unit further includes a crystal oscillator Y1; the crystal oscillator Y1 is connected to a clock input port of the clock generating unit.

[0011] In some embodiments, the clock generating unit also includes a magnetic bead FB1 and multiple filter capacitors; one end of the magnetic bead FB1 is connected to a power supply, and the other end is respectively connected to one end of the multiple filter capacitors for outputting power to the clock generating unit; the other ends of the multiple filter capacitors are respectively grounded.

[0012] On the other hand, an embodiment of the present application provides an interface conversion circuit, comprising the clock generating circuit, the second processing unit and the interface unit described in the above embodiment; the clock signal output end of the clock generating unit is electrically connected to the first processing unit, the second processing unit and the interface unit, respectively, and outputs clock signals to the first processing unit, the second processing unit and the interface unit, respectively; the second processing unit is electrically connected to the first processing unit and the interface unit, respectively, and is used to be electrically connected to an external device through the interface unit according to the clock signal.

[0013] In some embodiments, the Schmitt trigger includes a first Schmitt trigger U2, a second Schmitt trigger U5 and a third Schmitt trigger U6; the input ends of the first Schmitt trigger U2, the second Schmitt trigger U5 and the third Schmitt trigger U6 are respectively electrically connected to the drain of the N-channel MOS transistor Q1.

[0014] In some embodiments, the first processing unit is a GPU processor; the second processing unit is a CPU processor; the interface unit is a PCIE4.0 interface; the clock generation unit includes a first enable control terminal OE0#, a second enable control terminal OE1#, and a third enable control terminal OE2#, a first clock signal output port pair DIF0 / DIF0#, a second clock signal output port pair DIF1 / DIF1#, and a third clock signal output port pair DIF2 / DIF2#; the output end of the first Schmitt trigger U2 is electrically connected to the first enable control terminal OE0#, and the clock generation unit includes a first enable control terminal OE0#, a second enable control terminal OE1#, and a third enable control terminal OE2#, a first clock signal output port pair DIF0 / DIF0#, a second clock signal output port pair DIF1 / DIF1#, and a third clock signal output port pair DIF2 / DIF2#. The unit is electrically connected to the clock port of the GPU processor through the first clock signal output port pair DIF0 / DIF0#; the output end of the second Schmitt trigger U5 is electrically connected to the second enable control end OE1#, and the clock generating unit is electrically connected to the clock port of the PCIE4.0 interface through the second clock signal output port pair DIF1 / DIF1#; the output end of the third Schmitt trigger U6 is electrically connected to the third enable control end OE2#, and the clock generating unit is electrically connected to the clock port of the CPU processor through the third clock signal output port pair DIF2 / DIF2#.

[0015] Another aspect of the embodiments of the present application provides a server, comprising the interface conversion circuit proposed in the above embodiments.

[0016] As can be seen from the above, the clock generating circuit 100 proposed in the embodiment of the present application is provided with a signal delay control unit 120 and a clock generating unit 130. When the first processing unit outputs a control signal through the control signal output port, the signal delay control unit delays the control signal through a Schmitt trigger. After the control signal is delayed, the clock generating unit 130 is triggered to output a new clock signal. In this way, the power-on timing of the newly generated clock signal output is controlled, thereby avoiding interference between the original clock signal and the new clock signal, and enabling the clock generating circuit to generate a stable and reliable clock signal.

[0017] The above description is only an overview of the technical solution of the utility model. In order to more clearly understand the technical means of the utility model, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the utility model more obvious and easy to understand, the specific implementation methods of the utility model are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] By reading the detailed description of the preferred embodiment below, various other advantages and benefits will become clear to those of ordinary skill in the art. The accompanying drawings are only used for the purpose of illustrating the preferred embodiment and are not considered to be limiting of the present invention. Moreover, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0019] Figure 1 A schematic diagram of a clock generation circuit provided by an embodiment of the utility model is shown;

[0020] Figure 2 A circuit diagram of a clock generating unit provided by an embodiment of the utility model is shown;

[0021] Figure 3 A circuit diagram of a Schmitt trigger provided by an embodiment of the utility model is shown;

[0022] Figure 4 A power supply circuit diagram of a clock generating unit provided in an embodiment of the utility model is shown;

[0023] Figure 5 A circuit diagram of a clock generation unit provided in an embodiment of the utility model is shown.

[0024] Figure 6 A schematic diagram of an interface conversion circuit provided by an embodiment of the utility model is shown;

[0025] Figure 7 A circuit diagram of an interface conversion circuit provided by an embodiment of the utility model is shown. DETAILED DESCRIPTION

[0026] The following embodiments of the technical solution of the present application are described in detail in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present application, and are therefore only used as examples, and cannot be used to limit the scope of protection of the present application.

[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by technicians in the technical field to which this application belongs; the terms used herein are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" in the specification and claims of this application and the above-mentioned figure descriptions and any variations thereof are intended to cover non-exclusive inclusions.

[0028] In the description of the embodiments of the present application, the technical terms "first", "second", etc. are only used to distinguish different objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the number, specific order or primary and secondary relationship of the indicated technical features. In the description of the embodiments of the present application, the meaning of "multiple" is more than two, unless otherwise clearly and specifically defined.

[0029] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0030] In the description of the embodiments of the present application, the term "and / or" is only a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists, A and B exist at the same time, and B exists. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0031] In the description of the embodiments of the present application, the term "multiple" refers to more than two (including two). Similarly, "multiple groups" refers to more than two groups (including two groups), and "multiple pieces" refers to more than two pieces (including two pieces).

[0032] In the description of the embodiments of the present application, the technical terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, which are only for the convenience of describing the embodiments of the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the embodiments of the present application.

[0033] In the description of the embodiments of the present application, unless otherwise clearly specified and limited, technical terms such as "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, and it can be the internal connection of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present application can be understood according to the specific circumstances.

[0034] High-speed embedded CPU systems are becoming more and more widely used and are often used in conjunction with GPUs. For example, Intel's 11th-generation CPU can be paired with a PCIEx16 graphics card, which can support a maximum interface rate of PCIE4.0, and the GPU can use the W480E chipset.

[0035] In actual applications, since the CPU and GPU need to be used together, the performance of any one component will affect the overall performance. For example, since the W480E chipset supports a maximum clock of PCIE3.0, many machines and devices cannot maximize CPU performance due to the chipset, resulting in Intel's 11th generation CPU only supporting a maximum rate of PCIE 3.0, which cannot meet the needs of high-speed GPU computing venues and affect the normal use of the client.

[0036] In view of this, the embodiments of the present application provide a clock generation circuit, an interface conversion circuit and a server. The clock generation circuit, interface conversion circuit and server proposed in the embodiments of the present application can be applied to a variety of scenarios and on a variety of devices. The embodiments of the present application only use the W480E chipset, Intel 11th generation CPU, PCIE3.0 and PCIE4.0 as examples for illustration, and cannot be understood as limiting the scope of protection of the present application.

[0037] The clock generation circuit provided in the embodiment of the present application enables the processing unit to control the clock generation unit to generate a new PCIE4.0 clock signal, and by outputting the new PCIE4.0 clock signal to the CPU, GPU and interface circuit, it can all work under the PCIE4.0 clock, solving the problem in the prior art that all components cannot perform at their maximum performance due to the limitation of the clock signal. In the embodiment of the present application, the signal delay control unit controls the clock generation unit to generate a new first clock signal, avoiding interference between the new PCIE4.0 clock signal and the original PCIE3.0 clock signal, greatly improving the stability of the first clock signal, and also improving the working performance of the interface conversion circuit and the server.

[0038] Please refer to Figure 1 , Figure 2 and Figure 3 , shows a schematic structural diagram of a clock generating circuit 100 proposed in an embodiment of the present application, including a first processing unit 110, a signal delay control unit 120 and a clock generating unit 130.

[0039] The first processing unit 110 includes a control signal output port, and the control signal output port is electrically connected to the signal delay control unit 120; the signal delay control unit 120 includes a MOS tube 121 and a Schmitt trigger 122, and the Schmitt trigger 122 includes an input end and an output end. The control signal output port is electrically connected to the input end of the Schmitt trigger 122 through the MOS tube 121, and the output end of the Schmitt trigger 122 is electrically connected to the clock generating unit 130, and the Schmitt trigger 122 is used to delay the control signal output by the control signal output port; the clock generating unit 130 includes an enable control end and a clock signal output end, and the enable control end is electrically connected to the output end of the Schmitt trigger 122, and the clock generating unit 130 outputs the clock signal through the clock signal output end.

[0040] In the embodiment of the present application, the first processing unit 110 is a W480E chipset, the clock generating unit 130 is a clock generator of model PCIE5 9FGL0451CKILFT, and the Schmitt trigger is SN74LVC1G17 of Texas Instruments. It should be pointed out that the above-mentioned first processing unit, clock generating unit and Schmitt trigger can also use other types of devices, which are not limited in the embodiment of the present application.

[0041] like Figure 1 , Figure 2 and Figure 3 As shown, the first processing unit 110 includes a control signal output port and a clock signal input port. The first processing unit 110 outputs the clock control signal CPU_C10_GATE- through the control signal output port. In practical applications, the control signal output port is usually in a low level state. In the embodiment of the present application, when the first processing unit 110 outputs the PCIE3.0 clock signal, in order to enable it to output the PCIE4.0 clock signal, when the first processing unit 110 outputs the PCIE3.0 clock signal, the control signal output port of the first processing unit 110 is changed from a low level to a high level.

[0042] like Figure 1 As shown, the signal delay control unit 120 includes a MOS transistor 121 and a Schmitt trigger 122. The MOS transistor 121 can be a P-channel MOS transistor or an N-channel MOS transistor, which is not limited here, as long as it can output a low-level signal to the input end of the Schmitt trigger after the control signal output port is converted from a low level to a high level.

[0043] The Schmitt trigger 122 is a binary trigger with a hysteresis characteristic, that is, the level of the input signal required for the output state to change depends on the current output state. Only when the input signal exceeds or falls below a preset threshold value, the change of the output end will be triggered. Therefore, the Schmitt trigger can delay the input signal. In the embodiment of the present application, when the control signal output port is converted from a low level to a high level, the signal is inverted through the MOS tube 121, and a low-level signal is input to the input end of the Schmitt trigger 122. The Schmitt trigger 122 delays the low-level signal, and a delayed, stable and reliable low-level signal can be output to the clock generation unit 130 through the output end of the Schmitt trigger 122.

[0044] The clock generating unit 130 is a clock generator of model PCIE5 9FGL0451CKILFT, which can generate a clock signal that meets the requirements of PCIE4.0. Figure 2 and Figure 3 As shown, the clock generating unit 130 includes an enable control terminal OE0# and clock signal output terminals DIF0 and DIF0#. When the enable control terminal OE0# of the clock generating unit 130 receives the delayed low-level signal OE0_U1 sent by the Schmitt trigger 122, the clock generating unit 130 outputs PCIE4.0 clock signals CLKIN_OBS_P and CLKIN_OBS_N through the clock signal output terminals DIF0 and DIF0#.

[0045] When the first processing unit 110 outputs the PCIE3.0 clock signal, its control signal output port changes from a low level to a high level, that is, the CPU_C10_GATE-signal is output to trigger the PCIE4.0 clock signal. When the CPU_C10_GATE-signal passes through the signal delay control unit 120, the signal will be delayed for a period of time before triggering the clock generation unit 130 to generate the PCIE4.0 clock signal. In other words, the time when the first processing unit 110 outputs the PCIE3.0 clock signal is earlier than the PCIE4.0 clock signal generated by the clock generation unit 130. In this way, the power-on timing of the PCIE4.0 clock signal output is controlled, thereby avoiding interference between the PCIE3.0 clock signal and the PCIE4.0 clock signal, and enabling the clock generation circuit to generate a stable and reliable PCIE4.0 clock signal.

[0046] It should be pointed out that in actual applications, in addition to the need to output PCIE4.0 clock signals in hardware, W480E also needs to make corresponding changes in configuration to enable it to support PCIE4.0. For example, the BIOS of W480E needs to be changed. The BIOS changes the External PEG / DMI Clock Configuration option from Disable to Enable, so that the PCIE clock output is based on the actual hardware circuit, rather than being limited to the configuration with the highest clock of PCIE3.0.

[0047] In some embodiments, in order to make the circuit structure of the signal delay control unit 120 simpler, as shown in FIG. Figure 3 As shown, in the embodiment of the present application, the MOS transistor is an N-channel MOS transistor Q1; the gate of the N-channel MOS transistor Q1 is electrically connected to the control signal output port, the source of the N-channel MOS transistor Q1 is grounded, and the drain of the N-channel MOS transistor Q1 is electrically connected to the input end of the Schmitt trigger.

[0048] The gate of the N-channel MOS transistor Q1 is connected to the control signal output port of the first processing unit 110 through the resistor R27, and is grounded through the resistor R28. This connection method can prevent the current passing through the N-channel MOS transistor Q1 from being too large, causing damage to the MOS transistor. The drain of the N-channel MOS transistor Q1 is connected to the power supply VCC3_3 through the resistor R10, and the drain of the N-channel MOS transistor Q1 is also connected to the input terminal A of the Schmitt trigger U2.

[0049] It should be noted that when multiple Schmitt triggers are configured, the input end of each Schmitt trigger can be connected to the drain of the N-channel MOS transistor Q1. The embodiment of the present application provides the N-channel MOS transistor Q1, so that the circuit structure is simple and the energy consumption is low.

[0050] Furthermore, in some embodiments, in order to improve the stability of the Schmitt trigger and reduce signal interference, Figure 3 As shown, a filter capacitor C14 is provided at the input terminal A of the Schmitt trigger U2, one end of the filter capacitor C14 is grounded, and the other end is connected to the input terminal A. By providing the filter capacitor C14, the signal output by the N-channel MOS tube Q1 can be filtered, thereby reducing interference with the input signal of the Schmitt trigger U2.

[0051] Furthermore, in some embodiments, Figure 2As shown, the clock generation unit 120 also includes a pull-up resistor R13; one end of the pull-up resistor R13 is electrically connected to the enable control terminal OE0#, and the other end is grounded. The output end of the Schmitt trigger U2 is electrically connected to the enable control terminal OE0#, and the OE0_U1 signal output by the Schmitt trigger U2 is connected to the enable control terminal OE0# through the pull-up resistor R13, so that the input signal is more stable and reliable. Preferably, the pull-up resistor R13 can use a 10K resistor.

[0052] In order to make the clock generation unit 130 work better, in some embodiments, Figure 2 and Figure 4 As shown, the clock generating unit 130 further includes a crystal oscillator Y1; the crystal oscillator Y1 outputs a clock signal for the clock generating unit 130 to work normally to the clock input ports X2 and XIN / CLKIN_5 of the clock generating unit.

[0053] The crystal oscillator Y1 is a commonly used crystal oscillator unit, whose Pin1 is connected to XIN / CLKIN_5 after being grounded through capacitor C12, whose Pin3 is connected to X2 port of clock generation unit 130 through resistor R22 after being grounded through C11; and whose Pin2 and Pin4 pins are grounded.

[0054] In some embodiments, such as Figure 5 As shown, the clock generating unit 130 also includes a magnetic bead FB1 and multiple filter capacitors; one end of the magnetic bead FB1 is connected to the power supply, and the other end is respectively connected to one end of the multiple filter capacitors to output power to the clock generating unit; the other ends of the multiple filter capacitors are respectively grounded.

[0055] like Figure 5 As shown, the input voltage of the clock generating unit 130 includes two voltage inputs, VDD3_3 and VDD3_3A. In the embodiment of the present application, one end of the magnetic bead FB1 is connected to the external power supply VCC3_3 and the other end is respectively connected to multiple filter capacitors C2, C3, C4, etc., and a voltage divider resistor R1 is set at the same time, so that the voltages VDD3_3 and VDD3_3A can be input respectively.

[0056] It can be seen from the above embodiments that the clock generating circuit 100 proposed in the present application generates a PCIE4.0 clock trigger signal CPU_C10_GATE- when the first processing unit 110 generates a PCIE3.0 clock signal by setting a signal delay control unit 120 and a clock generating unit 130. After the PCIE4.0 clock trigger signal CPU_C10_GATE- passes through the signal delay control unit 120, its time is delayed, and then the clock generating unit 130 is triggered to generate a PCIE4.0 clock signal. In this way, the power-on timing of the PCIE4.0 clock signal output is controlled, thereby avoiding interference between the PCIE3.0 clock signal and the PCIE4.0 clock signal, and enabling the clock generating circuit to generate a stable and reliable PCIE4.0 clock signal.

[0057] On the other hand, in order to better adapt the CPU, GPU and interface circuits and give full play to the optimal performance of each chip, in some embodiments of the present application, such as Figure 6 As shown, an interface conversion circuit 200 is also proposed, comprising the clock generation circuit 100, the second processing unit 140 and the interface unit 150 proposed in any of the above embodiments. The clock signal output end of the clock generation unit 100 is electrically connected to the first processing unit 110, the second processing unit 140 and the interface unit 150 respectively, and outputs the clock signal to the first processing unit 110, the second processing unit 140 and the interface unit 150 respectively; the second processing unit 140 is electrically connected to the first processing unit 110 and the interface unit 150 respectively, and is used to be electrically connected to an external device through the interface unit 150 according to the clock signal.

[0058] In this embodiment, the first processing unit 110 is a GPU processor, the second processing unit 140 is a CPU processor, and the interface unit 150 is a PCIE4.0 interface. Figure 6 As shown, the second processing unit 140 is electrically connected to the first processing unit 110 and the interface unit 150 respectively.

[0059] When the interface conversion circuit needs to support the PCIE4.0 interface, the clock generation unit 130 generates a clock signal, which is a PCIE4.0 clock signal, and sends the PCIE4.0 clock signal to the first processing unit 110, the second processing unit 140 and the interface unit 150 respectively.

[0060] After the first processing unit 110, the second processing unit 140 and the interface unit 150 all receive the PCIE4.0 clock signal, the second processing unit 140 can be electrically connected to the external device through the interface unit 150 and transmit data through the PCIE4.0 interface.

[0061] The interface conversion circuit 200 can enable the CPU and GPU to support the PCIE4.0 interface, thereby improving the adaptability of each part and improving the overall performance.

[0062] In some embodiments, in order to output multiple PCIE4.0 clock signals, such as Figure 3 As shown, the Schmitt trigger includes a first Schmitt trigger U2, a second Schmitt trigger U5 and a third Schmitt trigger U6; the input ends of the first Schmitt trigger U2, the second Schmitt trigger U5 and the third Schmitt trigger U6 are electrically connected to the drain of the N-channel MOS transistor Q1 respectively.

[0063] In an embodiment of the present application, the signal delay control unit 120 needs to provide a PCIE4.0 clock signal to the first processing unit 110, the second processing unit 140 and the interface unit 150 at the same time. Therefore, in an embodiment of the present application, a plurality of Schmitt triggers are set in the signal delay control unit 120.

[0064] like Figure 3 As shown, the first Schmitt trigger U2, the second Schmitt trigger U5 and the third Schmitt trigger U6 are arranged in parallel, the input terminals A thereof are respectively electrically connected to the drain of the N-channel MOS transistor Q1, and the output terminals thereof respectively output delayed signals OE0_U1, OE1_U1 and OE2_U1, the output terminal of the first Schmitt trigger U2 is connected to the OE0# port of the clock signal generating unit, the output terminal of the second Schmitt trigger U5 is connected to the OE1# port of the clock signal generating unit, and the output terminal of the third Schmitt trigger U6 is connected to the OE2# port of the clock signal generating unit.

[0065] After the N-channel MOS transistor Q1 receives the CPU_C10_GATE- signal sent by the first processing unit 110, the first Schmitt trigger U2, the second Schmitt trigger U5 and the third Schmitt trigger U6 respectively generate delayed OE0_U1, OE1_U1 and OE2_U1 signals, and send them to the signal generating unit 130, so that it generates corresponding PCIE4.0 clock signals respectively.

[0066] Continue to refer Figure 3 and Figure 7 The first processing unit 110 is a GPU processor; the second processing unit 140 is a CPU processor; the interface unit 150 is a PCIE4.0 interface; the clock generation unit 130 includes a first enable control terminal OE0#, a second enable control terminal OE1# and a third enable control terminal OE2#, a first clock signal output port pair DIF0 / DIF0#, a second clock signal output port pair DIF1 / DIF1#, and a third clock signal output port pair DIF2 / DIF2#.

[0067] The output end of the first Schmitt trigger U2 is electrically connected to the first enable control end OE0#, and the clock generation unit 130 is electrically connected to the clock ports RSVD[2] and RSVD[3] of the GPU processor through the first clock signal output port pair DIF0 / DIF0#, and outputs the first clock signals CLKIN_OBS_P and CLKIN_OBS_N; the output end of the second Schmitt trigger U5 is electrically connected to the second enable control end OE1#, and the clock generation unit 130 is electrically connected to the clock port of the PCIE4.0 interface through the second clock signal output port pair DIF1 / DIF1#. The REFCLK# and REFCLK- ports are electrically connected to output the second clock signals CLK_H_PCIBCLKP and CLK_H_PCIBCLKN; the output end of the third Schmitt trigger U6 is electrically connected to the third enable control terminal OE2#, and the clock generating unit 130 is electrically connected to the clock ports PCI_BCLKP and PCI_BCLKN of the CPU processor through the third clock signal output port pair DIF2 / DIF2# to output the second clock signals CLK_H_PCIBCLKP and CLK_PEG_SLOT1+ and CLK_PEG_SLOT1-.

[0068] Through the above method, the clock generation unit 130 can generate three PCIE4.0 clock signals to the first unit 110, the second processing unit 140 and the interface unit 150 at the same time according to the signal sent by the signal delay control unit 120, so that the first unit 110, the second processing unit 140 and the interface unit 150 can support the PCIE4.0 signal at the same time, coordinate the operations between the first unit 110, the second processing unit 140 and the interface unit 150, and greatly improve the system performance.

[0069] The embodiment of the present application also proposes a server, including the interface conversion circuit proposed in any of the above embodiments. Its circuit structure is the same as that described in the above embodiments, and will not be repeated here.

[0070] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application, and they should all be included in the scope of the claims and specification of the present application. In particular, as long as there is no structural conflict, the various technical features mentioned in the various embodiments can be combined in any way. The present application is not limited to the specific embodiments disclosed herein, but includes all technical solutions that fall within the scope of the claims.

Claims

1. A clock generating circuit, characterized in that: include: a first processing unit, a signal delay control unit, and a clock generation unit; The first processing unit comprises a control signal output port, and the control signal output port is electrically connected to the signal delay control unit; The signal delay control unit includes a MOS tube and a Schmitt trigger, the Schmitt trigger includes an input end and an output end, the control signal output port is electrically connected to the input end of the Schmitt trigger through the MOS tube, the output end of the Schmitt trigger is electrically connected to the clock generation unit, and the Schmitt trigger is used to delay the control signal output by the control signal output port; The clock generating unit comprises an enable control terminal and a clock signal output terminal. The enable control terminal is electrically connected to the output terminal of the Schmitt trigger and outputs the clock signal through the clock signal output terminal.

2. The clock generating circuit according to claim 1, wherein: The MOS tube is an N-channel MOS tube Q1; The gate of the N-channel MOS transistor Q1 is electrically connected to the control signal output port, the source of the N-channel MOS transistor Q1 is grounded, and the drain of the N-channel MOS transistor Q1 is electrically connected to the input end of the Schmitt trigger.

3. The clock generating circuit according to claim 2, characterized in that: The input end of the Schmitt trigger is grounded via a filter capacitor C14.

4. The clock generating circuit according to claim 2, wherein: The clock generation unit also includes a pull-up resistor R13; One end of the pull-up resistor is electrically connected to the enable control end, and the other end is grounded.

5. The clock generating circuit according to claim 1, wherein: The clock generating unit also includes a crystal oscillator Y1; The crystal oscillator Y1 is connected to the clock input port of the clock generating unit.

6. The clock generating circuit according to claim 1, wherein: The clock generation unit also includes a magnetic bead FB1 and a plurality of filter capacitors; One end of the magnetic bead FB1 is connected to the power supply, and the other end is respectively connected to one end of the plurality of filter capacitors, so as to output power to the clock generating unit; The other ends of the plurality of filter capacitors are grounded respectively.

7. An interface conversion circuit, characterized in that: comprising a clock generating circuit, a second processing unit and an interface unit as claimed in any one of claims 1 to 6; The clock signal output end of the clock generating unit is electrically connected to the first processing unit, the second processing unit and the interface unit respectively, and outputs the clock signal to the first processing unit, the second processing unit and the interface unit respectively; The second processing unit is electrically connected to the first processing unit and the interface unit respectively, and is used to be electrically connected to an external device through the interface unit according to the clock signal.

8. The interface conversion circuit according to claim 7, characterized in that: The Schmitt trigger includes a first Schmitt trigger U2, a second Schmitt trigger U5 and a third Schmitt trigger U6; The input terminals of the first Schmitt trigger U2 , the second Schmitt trigger U5 and the third Schmitt trigger U6 are electrically connected to the drain of the N-channel MOS transistor Q1 , respectively.

9. The interface conversion circuit according to claim 8, characterized in that: The first processing unit is a GPU processor; the second processing unit is a CPU processor; the interface unit is a PCIE4.0 interface; The clock generation unit includes a first enable control terminal OE0#, a second enable control terminal OE1#, a third enable control terminal OE2#, a first clock signal output port pair DIF0 / DIF0#, a second clock signal output port pair DIF1 / DIF1#, and a third clock signal output port pair DIF2 / DIF2#; The output end of the first Schmitt trigger U2 is electrically connected to the first enable control end OE0#, and the clock generation unit is electrically connected to the clock port of the GPU processor through the first clock signal output port pair DIF0 / DIF0#; The output end of the second Schmitt trigger U5 is electrically connected to the second enable control end OE1#, and the clock generating unit is electrically connected to the clock port of the PCIE4.0 interface through the second clock signal output port pair DIF1 / DIF1#; The output end of the third Schmitt trigger U6 is electrically connected to the third enable control end OE2#, and the clock generating unit is electrically connected to the clock port of the CPU processor through the third clock signal output port pair DIF2 / DIF2#.

10. A server, characterized in that: Comprising the interface conversion circuit as described in any one of claims 7-9.

Images