Packaging structure of semiconductor device
By forming grooves on the substrate and filling the packaging glue, the high cost and material forming cooling and shrinkage problems caused by the mold dependence of the packaging structure in the prior art are solved, and a low-cost and high-reliability semiconductor device packaging structure is realized.
Patent Information
- Application Number
- CN202421136253.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-22
- Publication Date
- 2025-02-28
- Estimated Expiration
- 2034-05-22
AI Technical Summary
The packaging structure of existing optoelectronic semiconductor devices relies on molds, which leads to high costs and has product failure problems caused by shrinkage during cooling of material forming.
A mold-dependent semiconductor device packaging structure is designed, and the chip and bonding wire are packaged by forming grooves on the substrate and filling packaging glue to achieve a flat packaging design and reduce costs.
This packaging structure reduces dependence on molds, reduces packaging costs, improves the reliability and mechanical stability of the packaging structure, and avoids chip damage caused by material forming cooling and shrinkage.
Smart Images
Figure CN222546360U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of semiconductors, and more specifically, to a packaging structure of a semiconductor device. Background Art
[0002] The packaging structure of existing optoelectronic semiconductor devices is usually composed of parts and components made of a variety of different materials, and relies on molds for final packaging molding. The corresponding cost of the molds is relatively high. The product may involve multiple sets of modules from the beginning of design to the finalization, which leads to high manufacturing costs of the product.
[0003] Furthermore, since different materials have different expansion coefficients, when rigid materials are used to wrap bonding wires and chips, there is a risk of chips falling off and bonding wires tearing. Using softer materials can avoid such risks, but softer materials cannot provide mechanical protection for the package, and the product will deform and components will be damaged.
[0004] At present, the packaging structure of optoelectronic semiconductor devices needs to be manufactured using molds, which is not only too expensive, but also faces problems such as product failure caused by shrinkage during material molding and cooling.
[0005] Therefore, there is an urgent need for a semiconductor device packaging structure that is independent of molds and has higher reliability to meet market demand. Utility Model Content
[0006] In view of this, the utility model provides a packaging structure of a semiconductor device, which avoids dependence on a mold, reduces packaging costs, and achieves the requirements of low cost and high reliability.
[0007] To achieve this object, the utility model provides a packaging structure of a semiconductor device, comprising: a substrate, a first surface of the substrate is provided with a groove, the thickness of the edge of the substrate is greater than the thickness of the center of the substrate; a control chip, located on the bottom surface of the groove of the substrate, the control chip is located in a cavity formed by the groove; an optoelectronic chip, located on the control chip and covering a portion of the surface of the control chip; a bonding wire, the bonding wire electrically connects the control chip to the substrate; a protective layer or a wavelength converter, covering the optoelectronic chip; a packaging glue, located in the groove, the packaging glue fills the gap between the side wall of the groove and the control chip, and extends to cover one of the following partial top surfaces: (1) the packaging glue extends to cover a portion of the top surface of the control chip; (2) the packaging glue extends to cover a portion of the top surface of the protective layer; (3) the packaging glue extends to cover a portion of the top surface of the wavelength converter.
[0008] Optionally, the substrate is a ceramic substrate.
[0009] Optionally, the substrate is an aluminum nitride ceramic substrate.
[0010] Optionally, the protective layer is a transparent layer.
[0011] Optionally, the wavelength converter is a phosphor layer.
[0012] Optionally, the thickness of the packaging glue is smaller than the depth of the groove, and the packaging glue completely covers the bonding wire.
[0013] Optionally, the protective layer or the wavelength converter further extends to cover a portion or the entire surface of the control chip.
[0014] Optionally, it also includes an enclosure, which is arranged around the light-emitting area of the optoelectronic chip.
[0015] Optionally, when the packaging glue extends to cover a portion of the top surface of the control chip, the enclosure is located on the surface of the control chip.
[0016] Optionally, when the packaging glue extends to cover a portion of the top surface of the protective layer, the barrier is located on the surface of the protective layer.
[0017] Optionally, when the packaging glue extends to cover a portion of the top surface of the wavelength converter, the enclosure is located on the surface of the wavelength converter.
[0018] Optionally, an upper surface of the packaging glue is lower than an upper surface of the enclosure, and the packaging glue is located between the side wall of the groove and the enclosure.
[0019] Optionally, a heat conducting block is further provided on the substrate in a region corresponding to the control chip.
[0020] Optionally, the heat conductive block is a plurality of separate heat conductive blocks.
[0021] Optionally, a projection of the packaging adhesive toward the substrate does not overlap with a projection of the optoelectronic chip toward the substrate.
[0022] The beneficial technical effect of the utility model is that: the packaging structure of the semiconductor device of the utility model, the protective layer or the wavelength converter covers the optoelectronic chip, which can protect the optoelectronic chip. The protective layer attached to the optoelectronic chip can make the packaging structure more reliable; the wavelength converter attached to the optoelectronic chip is easier to dissipate heat of the wavelength converter, and the better the heat dissipation, the higher the conversion efficiency of the wavelength converter.
[0023] Furthermore, by forming a groove on the substrate and filling the groove with encapsulation glue to encapsulate the chip and bonding wire in the groove, the processing of the packaging structure is freed from the need for a mold, and the cost can be effectively reduced while realizing a flat packaging design; the encapsulation glue will hinder the light emission of the optoelectronic chip, and the encapsulation glue does not cover the light-emitting area of the optoelectronic chip to ensure the brightness of the optoelectronic chip.
[0024] Furthermore, the packaging structure adopts a substrate with a certain thickness, which not only provides a good external protection frame for the chip, but the softer internal packaging glue also reduces the risk of chip falling off and bonding wire tearing. The substrate is an integrated structure. The packaging structure of the semiconductor device can not only effectively reduce the types of materials, but also avoid damage to the chip caused by cooling and shrinkage during material molding. The structure has high mechanical stability, which improves the stability and reliability of the packaging structure of the semiconductor device.
[0025] Furthermore, providing a barrier can prevent the encapsulation glue from overflowing into the light-emitting area of the optoelectronic chip, thereby ensuring the brightness of the optoelectronic chip.
[0026] Furthermore, conductive blocks may be used in the substrate to replace through holes, thereby improving the heat dissipation performance of the packaging structure of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] The above and other purposes, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
[0028] Figure 1 is a cross-sectional schematic diagram of a packaging structure of a semiconductor device according to a first embodiment of the utility model;
[0029] Figure 2 It is a schematic top view layout diagram of the packaging structure of the semiconductor device of the first embodiment of the utility model;
[0030] Figure 3 It is a schematic diagram of the arrangement of through holes below the chip component in the packaging structure of the semiconductor device of the first embodiment of the utility model;
[0031] Figure 4 is a cross-sectional schematic diagram of a packaging structure of a semiconductor device according to a second embodiment of the utility model;
[0032] Figure 5 is a schematic top view layout diagram of a semiconductor device packaging structure according to a second embodiment of the utility model;
[0033] Figure 6 A schematic diagram showing the manufacturing process of a packaging structure of a semiconductor device according to a second embodiment of the present invention;
[0034] Figures 7a to 7eSchematic cross-sectional views showing the various manufacturing steps of the packaging structure of the semiconductor device of the second embodiment of the utility model;
[0035] Figure 8 is a schematic cross-sectional view of a packaging structure of a semiconductor device according to a third embodiment of the present utility model;
[0036] Fig. 9 is a schematic cross-sectional view of a packaging structure of a semiconductor device according to a fourth embodiment of the present utility model;
[0037] Fig.10 It is a schematic diagram of the arrangement of heat-conducting blocks in the packaging structure of a semiconductor device according to the fourth embodiment of the utility model. DETAILED DESCRIPTION
[0038] The present invention is described below based on embodiments, but the present invention is not limited to these embodiments. In the detailed description of the present invention below, some specific details are described in detail. For those skilled in the art, the present invention can be fully understood without the description of these details. In order to avoid confusing the essence of the present invention, well-known methods, processes, procedures, and components are not described in detail.
[0039] In the description of the present invention, it is necessary to understand that the orientation or position relationship indicated by the terms such as "upper", "lower", "left", "right", "inside", "outside", "horizontal" and "longitudinal" is based on the orientation or position relationship shown in the corresponding drawings. It is for the convenience of describing the shape, position and connection relationship of each component in the present invention, rather than indicating or implying that the components must be located in a specific orientation and morphological structure in the whole, and should not be understood as a limitation on the present invention.
[0040] Figure 1 It is a cross-sectional schematic diagram of the packaging structure of the semiconductor device of the first embodiment of the utility model, the packaging structure 100 of the semiconductor device of the first embodiment includes a substrate 1 and a chip 2 located in a groove 10 of the substrate 1; wherein the groove 10 is, for example, located in the middle area of the substrate 1, the thickness of the edge of the substrate 1 is greater than the thickness of the center of the substrate 1, the chip 2 is, for example, located on the bottom surface 11 of the groove 10, the side wall of the groove 10 surrounds the chip 2 to form a cavity, the chip 2 includes, for example, a control chip 21 and an optoelectronic chip 22, and the optoelectronic chip 22 is electrically connected to the control chip 21. The control chip 21 is located on the first surface of the substrate 1, and specifically located on the bottom surface of the groove 10 of the substrate 1, and the optoelectronic chip 22 is located on the control chip 21 and covers part of the surface of the control chip 21.
[0041] The optoelectronic chip 22 is, for example, a light emitting diode chip or a laser diode chip, etc. The optoelectronic chip 22 has, for example, a plurality of light emitting areas that can be independently controlled and these light emitting areas can be arranged in a matrix form. For example, the optoelectronic chip 22 includes a matrix composed of 80*320 light emitting areas, but is not limited thereto, and can be applied to adaptive lighting in the automotive field. The control chip 21 is, for example, a chip for controlling the optoelectronic chip 22.
[0042] The second surface of the substrate 1 is arranged opposite to the first surface, and both the first surface and the second surface of the substrate 1 are planes, and a groove 10 is arranged on the first surface (upper surface). Further, the substrate 1 may be a ceramic substrate, and preferably, the substrate 1 may be an aluminum nitride ceramic substrate. A plurality of conductive layers 12 are also arranged on the bottom surface 11 of the groove 10 of the substrate 1, and the upper surface of the control chip 21 is electrically connected to the corresponding conductive layer 12 on the substrate 1 through the bonding wire 3. The second surface of the substrate 1, i.e., the side surface opposite to the bottom surface 11 of the groove 10 (the back side of the substrate), is also provided with a pad 13, and the pad 13 is, for example, electrically connected to the mounting and external of the packaging structure 100. The substrate 1 is also provided with a through hole 14 connecting the bottom surface 11 of the groove 10 and the second surface, and the through hole 14 includes, for example, a plurality of through holes, and by filling the side wall of the through hole 14 or in the through hole 14 with conductive material, the conductive layer 12 or other conductive wiring structure can be connected to the pad 13 on the second surface to achieve electrical connection; further, see Figure 3 As shown, the heat in the chip 2 can be promptly discharged through a plurality of through holes 14 arranged in an array, thereby achieving good heat dissipation capability.
[0043] The substrate 1 has a window structure in the middle to form a groove 10. The shape, size and depth of the groove 10 match the chip 2. Of course, the substrate 1 is made of a hard material, for example, and not only can various metal wiring layers be arranged inside, but the structure outside the groove 10 can also provide protection for the chip 2. Figure 2As shown, the size of the control chip 21 is, for example, larger than the size of the optoelectronic chip 22, and a pad may be provided in the edge area of the control chip 21 for bonding or increasing the area to enhance heat dissipation. A protective layer or wavelength converter 4 is provided on the optoelectronic chip 22, and the protective layer or wavelength converter 4 at least covers the surface of the optoelectronic chip 22. In this embodiment, the protective layer or wavelength converter 4 covers the surface of the optoelectronic chip 22 and the exposed surface of the control chip 21. The protective layer or wavelength converter 4 may be made of, for example, silicone, ceramic, glass, and the like. Optionally, the protective layer 4 is a transparent layer that only protects the optoelectronic chip 22 without changing the light color of the optoelectronic chip 22, and the optoelectronic chip 22 emits, for example, red, green, blue, and other colors of light. Optionally, the wavelength converter 4 is a phosphor layer that has a wavelength conversion function and can convert the light emitted by the optoelectronic chip 22 into white light. The encapsulation glue 5 is filled between the side wall of the groove 10 and the control chip 21, covering the bonding wire 3 to protect the bonding wire 3. Furthermore, the encapsulation glue 5 also extends to cover the edge of the protective layer or wavelength converter 4 to prevent water vapor in the external environment from entering from the interface between the protective layer or wavelength converter 4 and the control chip 21 to affect the reliability of the chip 2. The projection of the encapsulation glue 5 in the direction of the substrate 1 does not overlap with the projection of the optoelectronic chip 22 in the direction of the substrate 1, which can ensure the brightness of the optoelectronic chip 22. The protective layer or wavelength converter 4 is generally arranged on the control chip 21 and the optoelectronic chip 22 before the encapsulation glue 5. After the bonding wire 3 and the protective layer or wavelength converter 4 are arranged, the encapsulation glue 5 is filled into the groove 10 to cover the exposed surface of the groove 10, the bonding wire 3, the chip 2 and the edge of the protective layer or wavelength converter 4. The chip 2 and the bonding wire 3 are sealed and protected by the encapsulation glue 5 and the protective layer or wavelength converter 4. In order to reduce the impact on the bonding wire 3, the encapsulation glue 5 can be applied by dispensing or injection molding, for example. The encapsulation glue 5 is made of elastic materials, such as silicone resin, silica gel, epoxy resin, etc., and its hardness is less than that of the substrate 1. The encapsulation glue 5 can achieve sealing and waterproofing while reducing the mechanical load and stress of the bonding wire 3 and the chip 2, avoiding the risk of the bonding wire 3 tearing and the chip 2 falling off. Of course, in order to ensure that the function of the optoelectronic chip 22 is not affected, the encapsulation glue 5 only covers the edge area of the protective layer or the wavelength converter 4, and the encapsulation glue 5 is not set in the light-emitting area of the optoelectronic chip 22 to ensure the light-emitting brightness of the optoelectronic chip 22. In order to avoid overflow of the encapsulation glue 5, the depth of the groove 10 is, for example, not less than the height of the chip 2 combined with the protective layer or the wavelength converter 4, that is, the thickness of the encapsulation glue 5 is less than the depth of the groove 10.
[0044] Figure 3 Schematic diagram of through hole arrangement below chip assembly in the semiconductor device packaging structure of the first embodiment of the utility model, from Figure 3It can be seen that in the packaging structure of the semiconductor device, the substrate 1 is provided with a through hole 14 in the area corresponding to the control chip 21 in the chip 2. The through holes 14 are, for example, multiple, and the multiple through holes 14 are arranged in an array below the control chip 21. The interior or side walls of the through holes 14 are filled with metal. The edges of the arrayed control chips 21 are, for example, larger than the edges of the control chip 21. The through holes 14 enhance the thermal conductivity and heat dissipation capabilities of the chip 2, thereby improving its stability and reliability.
[0045] Figure 4 is a cross-sectional schematic diagram of a packaging structure of a semiconductor device according to a second embodiment of the present utility model, Figure 5 1 is a schematic diagram of a top view layout of a semiconductor device packaging structure of a second embodiment of the present invention; the semiconductor device of the second embodiment is similar to the first embodiment as a whole, except that a barrier 6 is further provided in the edge region on the protective layer or the wavelength converter 4, and the barrier 6 surrounds the edge region of the protective layer or the wavelength converter 4 and is not provided above the optoelectronic chip 22, such as Figure 4 and Figure 5 As shown, when the encapsulation glue 5 is filled, the encapsulation glue 5 can be prevented from spreading to the light-emitting area of the optoelectronic chip 22, thereby affecting the brightness of the optoelectronic chip 22. That is, the projection of the encapsulation glue 5 in the direction of the substrate 1 does not overlap with the projection of the optoelectronic chip 22 in the direction of the substrate 1, thereby ensuring the brightness of the optoelectronic chip 22. The enclosure 6 is, for example, set before the encapsulation glue 5, and the enclosure 6 also has a certain height. The enclosure 6 is, for example, made of the same material as the encapsulation glue 5, and the enclosure 6 is, for example, formed by a dispensing process; of course, the enclosure 6 can also be formed of other materials. The enclosure 6 is, for example, an opaque material, which can not only block the flow of the encapsulation glue 5, but also reduce unnecessary light scattering and reduce the interference of stray light.
[0046] The manufacturing process of the packaging structure of the semiconductor device of the second embodiment is as follows: Figure 6 As shown, including:
[0047] Step S10, setting a groove on the substrate; specifically, Figure 7a As shown, a groove 10 with a certain depth is provided on the upper surface of the central area of the substrate 1 .
[0048] Step S20, placing a chip in the groove of the substrate, and electrically connecting the chip to the substrate through bonding wires; specifically, Figure 7b As shown, a chip 2 is arranged on the bottom surface of the groove 10 of the substrate 1. The chip 2 includes a control chip 21 and an optoelectronic chip 22. The optoelectronic chip 22 is located above the control chip 21. The pads on the upper surface of the control chip 21 are electrically connected to the substrate 1 through bonding wires 3.
[0049] Step S30: setting a protective layer or a wavelength converter; specifically, Figure 7cAs shown, a protection layer or a wavelength converter 4 is disposed on the control chip 21 to cover the exposed area of the control chip 21 and the optoelectronic chip 22 .
[0050] Step S40 forms a fence; specifically, Figure 7d As shown, on the protective layer or the wavelength converter 4, a barrier 6 is arranged around the light emitting area of the optoelectronic chip 22, and the barrier 6 can be arranged, for example, by a glue dispensing process.
[0051] Step S50 forms a packaging glue; specifically, Figure 7e As shown, encapsulation glue 5 is filled between the side wall of the groove 10 and the enclosure 6 to cover the exposed surface of the substrate 1, the bonding wire 3, the chip 2 and the edge of the protective layer or the wavelength converter 4, and the chip 2 and the bonding wire 3 are sealed and protected by the encapsulation glue 5 and the protective layer or the wavelength converter 4.
[0052] Figure 8 : is a cross-sectional schematic diagram of the packaging structure of the semiconductor device of the third embodiment of the utility model; the packaging structure of the semiconductor device of the third embodiment is similar to that of the second embodiment as a whole, except that the protective layer or wavelength converter 4 covers the surface of the optoelectronic chip 22 and extends to cover part of the surface of the control chip 21, the enclosure 6 is located on the control chip 21, the packaging glue 5 covers the edge of the control chip 21, and there is a gap between the protective layer or wavelength converter 4 and the enclosure 6. In other embodiments, the protective layer or wavelength converter 4 may also only cover the surface of the optoelectronic chip 22 without extending to cover the surface of the control chip 21, or the protective layer or wavelength converter 4 covers the surface of the optoelectronic chip 22 and extends to cover part of the surface of the control chip 21, and the protective layer or wavelength converter 4 extends to contact with the enclosure 6. The projection of the packaging glue 5 in the direction of the substrate 1 does not overlap with the projection of the optoelectronic chip 22 in the direction of the substrate 1, which can ensure the brightness of the optoelectronic chip 22.
[0053] Fig. 9 is a schematic cross-sectional view of a packaging structure of a semiconductor device according to a fourth embodiment of the present utility model; Fig.10 1 is a schematic diagram of the arrangement of heat conduction blocks in the packaging structure of the semiconductor device of the fourth embodiment of the utility model; the fourth embodiment is also similar to the first embodiment, except that the heat conduction of the chip 2 in the packaging structure of the semiconductor device of the fourth embodiment is not achieved by the through hole 14. In the fourth embodiment, the substrate 1 is provided with a heat conduction block 15 in the area corresponding to the chip 2. For example, the heat conduction block 15 may be one or more. See Fig. 9 and Fig.10 A plurality of heat-conducting blocks 15 are arranged in an array below the chip 2. The edge of the heat-conducting block 15 is, for example, larger than the edge of the chip 2. The heat-conducting blocks 15 enhance the heat-conducting and heat-dissipating capacity of the semiconductor device packaging structure, further improving its stability and reliability.
[0054] The beneficial technical effect of the utility model is that: the packaging structure of the semiconductor device of the utility model, the protective layer or the wavelength converter covers the optoelectronic chip, which can protect the optoelectronic chip. The protective layer attached to the optoelectronic chip can make the packaging structure more reliable; the wavelength converter attached to the optoelectronic chip is easier to dissipate heat of the wavelength converter, and the better the heat dissipation, the higher the conversion efficiency of the wavelength converter.
[0055] Furthermore, by forming a groove on the substrate and filling the groove with encapsulation glue to encapsulate the chip and bonding wire in the groove, the processing of the packaging structure is freed from the need for a mold, and the cost can be effectively reduced while realizing a flat packaging design; the encapsulation glue will hinder the light emission of the optoelectronic chip, and the encapsulation glue does not cover the light-emitting area of the optoelectronic chip to ensure the brightness of the optoelectronic chip.
[0056] Furthermore, the packaging structure adopts a substrate with a certain thickness, which not only provides a good external protection frame for the chip, but the softer internal packaging glue also reduces the risk of chip falling off and bonding wire tearing. The substrate is an integrated structure. The packaging structure of the semiconductor device can not only effectively reduce the types of materials, but also avoid damage to the chip caused by cooling and shrinkage during material molding. The structure has high mechanical stability, which improves the stability and reliability of the packaging structure of the semiconductor device.
[0057] Furthermore, providing a barrier can prevent the encapsulation glue from overflowing into the light-emitting area of the optoelectronic chip, thereby ensuring the brightness of the optoelectronic chip.
[0058] Furthermore, conductive blocks may be used in the substrate to replace through holes, thereby improving the heat dissipation performance of the packaging structure of the semiconductor device.
[0059] In addition, persons of ordinary skill in the art will appreciate that the drawings provided herein are for illustration purposes and are not necessarily drawn to scale.
[0060] At the same time, it should be understood that example embodiments are provided so that the present disclosure is comprehensive and its scope is fully conveyed to those skilled in the art. Many specific details (such as examples of specific components, devices and methods) are given to provide a comprehensive understanding of the present disclosure. It will be understood by those skilled in the art that specific details need not be adopted, that example embodiments can be implemented in many different forms, and that example embodiments should not be construed as limiting the scope of the present disclosure. In some example embodiments, well-known device structures and well-known technologies are not described in detail.
[0061] When an element or layer is referred to as being "on," "engaged to," "connected to," or "coupled to" another element or layer, it may be directly on, directly engaged to, connected to, or coupled to another element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly" "on," "directly engaged to," "directly connected to," or "directly coupled to" another element or layer, there may be no intervening elements or layers. Other words used to describe the relationship between elements should be interpreted in a similar manner (e.g., "between" versus "directly between," "adjacent" versus "directly adjacent," etc.). As used herein, the term "and / or" includes any or all combinations of one or more of the associated listed items.
[0062] Although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms can only be used to distinguish an element, component, region, layer or section from another element, region, layer or section. Terms such as "first", "second" and other numerical terms do not mean order or sequence when used here, unless the context clearly indicates. Thus, the first element, component, region, layer or section discussed below can be referred to as the second element, component, region, layer or section, without departing from the teaching of the exemplary embodiment. In addition, in the description of the utility model, unless otherwise stated, the meaning of "multiple" is two or more.
[0063] The above description is only a preferred embodiment of the utility model and is not intended to limit the utility model. For those skilled in the art, the utility model may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the utility model shall be included in the protection scope of the utility model.
Claims
1. A semiconductor device packaging structure, characterized in that: include: A substrate, wherein a first surface of the substrate is provided with a groove, and a thickness at an edge of the substrate is greater than a thickness at a center of the substrate; A control chip is located on the bottom surface of the groove of the substrate, and the control chip is located in the cavity formed by the groove; an optoelectronic chip, located on the control chip and covering a portion of the surface of the control chip; A bonding wire electrically connecting the control chip to the substrate; A protective layer or a wavelength converter, covering the optoelectronic chip; The packaging glue is located in the groove, the packaging glue fills the gap between the side wall of the groove and the control chip, and extends to cover one of the following partial top surfaces: (1) The packaging glue extends to cover a portion of the top surface of the control chip; (2) the encapsulation adhesive extends to cover a portion of the top surface of the protective layer; (3) The packaging glue extends to cover a portion of the top surface of the wavelength converter.
2. The packaging structure according to claim 1, characterized in that: The substrate is a ceramic substrate.
3. The packaging structure according to claim 2, characterized in that: The substrate is an aluminum nitride ceramic substrate.
4. The packaging structure according to claim 1, characterized in that: The protective layer is a transparent layer.
5. The packaging structure according to claim 1, characterized in that: The wavelength converter is a phosphor layer.
6. The packaging structure according to claim 1, characterized in that: The thickness of the packaging glue is smaller than the depth of the groove, and the packaging glue completely covers the bonding wire.
7. The packaging structure according to claim 1, characterized in that: The protection layer or the wavelength converter also extends to cover a portion or the entire surface of the control chip.
8. The packaging structure according to claim 1 or 7, characterized in that: It also includes an enclosure, which is arranged around the light-emitting area of the optoelectronic chip.
9. The packaging structure according to claim 8, characterized in that: When the packaging glue extends to cover a portion of the top surface of the control chip, the enclosure is located on the surface of the control chip.
10. The packaging structure according to claim 8, characterized in that: When the packaging glue extends to cover a portion of the top surface of the protection layer, the barrier is located on the surface of the protection layer.
11. The packaging structure according to claim 8, characterized in that: When the packaging glue extends to cover a portion of the top surface of the wavelength converter, the enclosure is located on the surface of the wavelength converter.
12. The packaging structure according to claim 8, characterized in that: The upper surface of the packaging glue is lower than the upper surface of the enclosure, and the packaging glue is located between the side wall of the groove and the enclosure.
13. The packaging structure according to claim 1, characterized in that: The substrate is further provided with a heat conducting block in a region corresponding to the control chip.
14. The packaging structure according to claim 13, characterized in that: The heat conducting block is a plurality of separate heat conducting blocks.
15. The packaging structure according to claim 1, characterized in that: The projection of the packaging glue toward the substrate does not overlap with the projection of the optoelectronic chip toward the substrate.