Phase shifter

Abstract

The embodiment of the utility model provides a phase shifter, and the phase shifter comprises an orthogonal signal generator which is used for generating an I-path signal and a Q-path signal which are orthogonal based on a differential input signal; the gain amplification module comprises an I branch and a Q branch; the I branch comprises a first variable gain unit and a second variable gain unit; the first variable gain unit changes the phase weighting of the I-path signal based on the received first gain control signal; the second variable gain unit changes the amplitude weighting of the I-path signal based on the received second gain control signal; the Q branch comprises a third variable gain unit and a fourth variable gain unit; the third variable gain unit changes the phase weighting of the Q-path signal based on the received third gain control signal; the fourth variable gain unit changes the amplitude weighting of the Q-path signal based on the received fourth gain control signal; and the vector synthesizer is used for carrying out vector summation on the signal output by the gain amplification module to obtain a differential output signal.

Description

Technical Field

[0001] The present disclosure relates to the field of communications, and in particular to a phase shifter. Background Art

[0002] Phased array technology has a wide range of applications in millimeter wave communications, radar and other fields. The phased array system contains a large number of transceiver components, and the performance of the transceiver components will directly affect the performance of the phased array system. The transceiver components of the phased array system are mainly used to amplify signals, control the phase and amplitude changes of signals, etc. Therefore, traditional transceiver components usually include power amplifiers, low noise amplifiers, phase shifters and variable gain amplifiers. In traditional transceiver components, phase shifters and variable gain amplifiers are discrete, that is, phase control and amplitude control need to be implemented with at least two devices, resulting in large equipment size and area, and high power consumption. Utility Model Content

[0003] The embodiment of the present disclosure provides a phase shifter.

[0004] The embodiment of the present disclosure provides a phase shifter, including: an orthogonal signal generator, used to generate orthogonal I-path signal and Q-path signal based on a differential input signal; a gain amplifier module, including an I branch and a Q branch; the I branch includes a first variable gain unit and a second variable gain unit; the first variable gain unit changes the phase weighting of the I-path signal based on a received first gain control signal; the second variable gain unit changes the amplitude weighting of the I-path signal based on a received second gain control signal; the Q branch includes a third variable gain unit and a fourth variable gain unit; the third variable gain unit changes the phase weighting of the Q-path signal based on a received third gain control signal; the fourth variable gain unit changes the amplitude weighting of the Q-path signal based on a received fourth gain control signal; a vector synthesizer, used to perform vector summation on the signal output by the gain amplifier module to obtain a differential output signal.

[0005] In the phase shifter of the embodiment of the present disclosure, the phase shifter includes an orthogonal signal generator, a gain amplifier module and a vector synthesizer, wherein the gain amplifier module includes an I branch and a Q branch, which are respectively used to control the phase weighting and amplitude weighting of the I signal and the phase weighting and amplitude weighting of the Q signal; wherein the I branch includes a first variable gain unit and a second variable gain unit; the first variable gain unit changes the phase weighting of the I signal based on the received first gain control signal; the second variable gain unit changes the amplitude weighting of the I signal based on the received second gain control signal; the Q branch includes a third variable gain unit and a fourth variable gain unit; the third variable gain unit changes the phase weighting of the Q signal based on the received third gain control signal; the fourth variable gain unit changes the amplitude weighting of the Q signal based on the received fourth gain control signal; the signal output by the gain amplifier module is input to the vector synthesizer, and after vector summation by the vector synthesizer, a differential output signal is synthesized. Relative to the input signal of the orthogonal signal generator, the phase and amplitude of the differential output signal are modulated, wherein the phase can be modulated by 360 degrees, and the amplitude can be modulated by more than two gears.

[0006] In the scheme disclosed in the present invention, the gain amplification module in the phase shifter can realize phase and amplitude modulation, and there is no need to set up an additional gain amplifier outside the phase shifter for amplitude modulation; the phase shifter is used as a separate module to simultaneously perform phase and amplitude modulation, and there is no need to set up matching circuits between the various units in the phase shifter. For example, there is no need to set up a matching circuit between the first variable gain unit and the second variable gain unit, and there is no need to set up a matching circuit between the third variable gain unit and the fourth variable gain unit, so that the matching circuit between the phase modulation part and the amplitude modulation part can be omitted, which can save chip area and help save power consumption.

[0007] Furthermore, the second variable gain unit also includes multiple pairs of fixed gain transistors, which are used to provide fixed gain. The multiple pairs of fixed gain transistors can compensate for gain instability caused by different transistor sizes, ensuring that the second variable gain unit can achieve the required gain. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A schematic diagram of the structure of a transceiver component in the related art is shown;

[0009] Figure 2 A schematic structural diagram of a phase shifter provided by an embodiment of the present disclosure is shown;

[0010] Figure 3 A schematic diagram of a signal synthesis process of a phase shifter provided by an embodiment of the present disclosure is shown;

[0011] Figure 4AA schematic diagram of the structure of the I branch provided in an embodiment of the present disclosure is shown;

[0012] Figure 4B A schematic diagram of the structure of the Q branch provided by an embodiment of the present disclosure is shown;

[0013] Figure 5 A schematic diagram of the structure of a first variable gain unit provided in an embodiment of the present disclosure is shown;

[0014] Figure 6 The structure of the second variable gain unit provided by the embodiment of the present disclosure is shown. Figure 1 ;

[0015] Figure 7 A schematic diagram of the structure of a gain amplification module provided in an embodiment of the present disclosure is shown;

[0016] Figure 8 The structure of the second variable gain unit provided by the embodiment of the present disclosure is shown. Figure 2 ;

[0017] Fig. 9 A control module block diagram provided by an embodiment of the present disclosure is shown;

[0018] Fig.10 A control step flow chart provided by an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0019] The following will be combined with the embodiments of the present disclosure and the accompanying drawings to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0020] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0021] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0022] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.

[0023] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0024] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0025] In order to thoroughly understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below, but in addition to these detailed descriptions, the present disclosure may also have other implementations.

[0026] The rapid development of phased array technology has put forward higher and higher requirements for the miniaturization of transceiver components. Among the transceiver components, the integration of RF front-end transceiver circuits is one of the most challenging designs. Generally, RF front-end transceiver circuits not only require performance indicators such as wide bandwidth, low insertion loss, and high isolation, but also require a small size to achieve high integration.

[0027] In the related art, each antenna unit in the phased array circuit is equipped with a transceiver component, and multiple transceiver components are synthesized to obtain a phased array. Figure 1 FIG. 1 shows a schematic diagram of the structure of a transceiver component in the related art. Figure 1 As shown, the transceiver assembly includes a transmitting link and a receiving link; the transmitting link and the receiving link are switched by the transmitting and receiving channel switches 101 and 108. The transmitting link includes a power amplifier 102, a phase shifter 103 and a variable gain amplifier 104; the receiving link includes a low noise amplifier 105, a phase shifter 106 and a variable gain amplifier 107. Among them, the phase shifters 103 and 106 are respectively used to realize the phase control of the transmitting link and the receiving link, the variable gain amplifiers 104 and 107 are respectively used to realize the amplitude control of the transmitting link and the receiving link, the power amplifier 102 is used to realize the signal amplification of the transmitting link, and the low noise amplifier 105 is used to realize the signal amplification of the receiving link. It should be noted that in actual application, the positions of the phase shifter and the variable gain amplifier can be interchanged. In addition, a matching circuit is usually provided between the phase shifter and the variable gain amplifier, and the matching circuit is used to match the transmission signal between the phase shifter and the variable gain amplifier.

[0028] Figure 2 FIG. 2 shows a schematic diagram of the structure of a phase shifter provided by an embodiment of the present disclosure. Figure 2 As shown, the embodiment of the present disclosure provides a phase shifter, including:

[0029] The orthogonal signal generator 210 is used to generate an orthogonal I-path signal and a Q-path signal based on a differential input signal;

[0030] The gain amplification module 220 includes an I branch and a Q branch;

[0031] The I branch includes a first variable gain unit 221 and a second variable gain unit 222; the first variable gain unit 221 changes the phase weighting of the I signal based on the received first gain control signal; the second variable gain unit changes the amplitude weighting of the I signal based on the received second gain control signal;

[0032] The Q branch includes a third variable gain unit 223 and a fourth variable gain unit 224; the third variable gain unit changes the phase weighting of the Q path signal based on the received third gain control signal; the fourth variable gain unit changes the amplitude weighting of the Q path signal based on the received fourth gain control signal;

[0033] The vector synthesizer 230 is used to perform vector summation on the signal output by the gain amplification module 220 to obtain a differential output signal.

[0034] It should be noted that Figure 2 The first variable gain unit 221 to the fourth variable gain unit 224 in the illustrated gain amplification module 220 are only used to illustrate the inclusion relationship, and are not used to limit the connection relationship between the first variable gain unit 221 to the fourth variable gain unit 224. The specific connection relationship will be described in detail later.

[0035] It should also be noted that in the embodiments of the present disclosure, "amplitude weighting" can be an adjustment based on "phase weighting", that is, "amplitude weighting" is performed first and then "phase weighting"; or "phase weighting" can be an adjustment based on "amplitude weighting", that is, "amplitude weighting" is performed first and then "phase weighting"; or "amplitude weighting" and "phase weighting" are performed in parallel.

[0036] Here, "phase weighting" means adjusting the amplitude of the orthogonal signal in the I direction and the Q direction so that when the I-path signal and the Q-path signal are synthesized into a synthesized signal, the phase of the synthesized signal is adjusted and the amplitude of the synthesized signal remains unchanged. In other words, the phase of the synthesized signal is adjusted; "amplitude weighting" means adjusting the amplitude of the orthogonal signal in the I direction and the Q direction so that when the I-path signal and the Q-path signal are synthesized into a synthesized signal, the amplitude of the synthesized signal is adjusted and the phase of the synthesized signal remains unchanged. In other words, the amplitude of the synthesized signal is adjusted. In the embodiment of the present disclosure, the phase weighting of the I-path signal is changed by the first variable gain unit and the phase weighting of the Q-path signal is changed by the third variable gain unit to achieve phase adjustment of the synthesized signal of the I-path signal and the Q-path signal; the amplitude weighting of the I-path signal is changed by the second variable gain unit and the amplitude weighting of the Q-path signal is changed by the fourth variable gain unit to achieve amplitude adjustment of the synthesized signal of the I-path signal and the Q-path signal.

[0037] The phase shifter in the disclosed embodiment includes an orthogonal signal generator, a gain amplifier module and a vector synthesizer, wherein the gain amplifier module includes an I branch and a Q branch, which are respectively used to control the phase weighting and amplitude weighting of the I signal and the phase weighting and amplitude weighting of the Q signal; the signal output by the gain amplifier module is input to the vector synthesizer, and after vector summation by the vector synthesizer, a differential output signal is synthesized. Relative to the input signal of the orthogonal signal generator, the phase and amplitude of the differential output signal are modulated.

[0038] Here, “vector summation” is to synthesize the I-path signal and the Q-path signal to obtain a synthesized signal.

[0039] Furthermore, in the scheme disclosed herein, the gain amplification module in the phase shifter can realize phase and amplitude modulation, without the need to set up an additional gain amplifier outside the phase shifter for amplitude modulation; when the phase shifter is used as a separate module to simultaneously perform phase and amplitude modulation, there is no need to set up matching circuits between the various units in the phase shifter, for example, there is no need to set up a matching circuit between the first variable gain unit and the second variable gain unit, and there is no need to set up a matching circuit between the third variable gain unit and the fourth variable gain unit, thereby omitting the matching circuit between the phase modulation part and the amplitude modulation part, which can save chip area and help save power consumption.

[0040] In the disclosed embodiment, the phase shifter further includes: an input balun 240 and an output balun 250; wherein the input balun 240 is used to convert the single-ended input signal into the differential input signal; and the output balun 250 is used to convert the differential output signal into a single-ended output signal.

[0041] In some embodiments, the input balun 240 and the output balun 250 are three-port devices for switching between single-ended signals (including single-ended input signals and single-ended output signals) and differential signals (including differential input signals and differential output signals). The single-ended input signal entering the phase shifter 200 is divided into two differential input signals, In+ and In-, by the input balun 240, and then passes through the orthogonal signal generator 210 to generate four orthogonal signals (I-signal and Q-signal) of differential output, i.e., I+, I-, Q+, Q-. The output end of the orthogonal signal generator 210 includes an I+ signal end, an I- signal end, a Q+ signal end, and a Q- signal end.

[0042] In the embodiment of the present disclosure, the first variable gain unit and the second variable gain unit are connected in series, and the third variable gain unit and the fourth variable gain unit are connected in series.

[0043] It should be noted that, when the first variable gain unit and the second variable gain unit are connected in series, and the third variable gain unit and the fourth variable gain unit are connected in series, the series connection positions of the first variable gain unit 221 and the second variable gain unit 222 can be interchanged with each other, and the series connection positions of the third variable gain unit 223 and the fourth variable gain unit 224 can be interchanged with each other. Figure 2 Only one positional relationship of series connection is shown schematically.

[0044] In some embodiments, the two input ends of the first variable gain unit 221 are respectively connected to the I+ signal terminal and the I- signal terminal of the orthogonal signal generator, the two input ends of the second variable gain unit 222 are respectively connected to the two output ends of the first variable gain unit 221, and the two output ends of the second variable gain unit 222 output the first orthogonal signal and the second orthogonal signal; the two input ends of the third variable gain unit 223 are respectively connected to the Q+ signal terminal and the Q- signal terminal of the orthogonal signal generator 210, and the two input ends of the fourth variable gain unit 224 are respectively connected to the two output ends of the third variable gain unit 223, and the two output ends of the fourth variable gain unit 224 output the third orthogonal signal and the fourth orthogonal signal.

[0045] In an embodiment of the present disclosure, the second variable gain unit is configured to perform amplitude weighted adjustment on the signal output by the first variable gain unit based on the second gain control signal; the fourth variable gain unit is configured to perform amplitude weighted adjustment on the signal output by the third variable gain unit based on the fourth gain control signal.

[0046] In some embodiments, the first variable gain unit 221 performs phase weighted adjustment on the I-path signal to generate a first phase-shifted signal and a second phase-shifted signal; the second variable gain unit 222 performs amplitude weighted adjustment on the first phase-shifted signal and the second phase-shifted signal to generate a first orthogonal signal and a second orthogonal signal; the third variable gain unit 223 performs phase weighted adjustment on the Q-path signal to generate a third phase-shifted signal and a fourth phase-shifted signal; the fourth variable gain unit 224 performs amplitude weighted adjustment on the Q-path phase-shifted signal to generate a third orthogonal signal and a fourth orthogonal signal; the I branch outputs a first orthogonal signal and a second orthogonal signal, and the Q branch outputs a third orthogonal signal and a fourth orthogonal signal.

[0047] In some embodiments, Figure 3 FIG. 1 is a schematic diagram showing a signal synthesis process of a phase shifter provided by an embodiment of the present disclosure. It should be noted that: Figure 3 Take the example of performing "phase weighting" first and then "amplitude weighting" for explanation. Figure 3As shown, the gains of the first variable gain unit 221, the second variable gain unit 222, the third variable gain unit 223 and the fourth variable gain unit 224 are G1, G2, G3 and G4 respectively. The two input ends of the first variable gain unit 221 are respectively connected to the I+ signal end and the I- signal end, and the first phase-shifted signal and the second phase-shifted signal output by the first variable gain unit 221 are G1×I+ and G1×I- respectively; the two input ends of the second variable gain unit 222 are respectively connected to the two output ends of the first variable gain unit 221, and the second variable gain unit 222 outputs a first orthogonal signal G2×G1×I+ and a second orthogonal signal G2×G1×I-; the two input ends of the third variable gain unit 223 are respectively connected to the Q+ signal end and the Q- signal end, and the third phase-shifted signal and the fourth phase-shifted signal output by the third variable gain unit 223 are G3×Q+ and G3×Q- respectively; the two input ends of the fourth variable gain unit 224 are respectively connected to the two output ends of the third variable gain unit 223, and the fourth variable gain unit 224 outputs a third orthogonal signal G4×G3×Q+ and a fourth orthogonal signal G4×G3×Q-.

[0048] The vector synthesizer 230 performs I / Q vector synthesis on the first orthogonal signal G2×G1×I+ and the third orthogonal signal G4×G3×Q+, and outputs a differential output signal Out+ after vector synthesis, and performs I / Q vector synthesis on the second orthogonal signal G2×G1×I- and the fourth orthogonal signal G4×G3×Q-, and outputs a differential output signal Out- after vector synthesis. The phase weighting of the I-signal is changed by the first variable gain unit, and the phase weighting of the Q-signal is changed by the third variable gain unit. On the basis of the phase weighting, the amplitude weighting of the I-signal is changed by the second variable gain unit, and the amplitude weighting of the Q-signal is changed by the fourth variable gain unit, so as to achieve the common adjustment of the phase and amplitude of the synthesized signal of the I-signal and the Q-signal obtained after vector summation.

[0049] In the embodiment of the present disclosure, the first variable gain unit and the second variable gain unit may also be connected in parallel, and the third variable gain unit and the fourth variable gain unit may also be connected in parallel.

[0050] In some embodiments, the first variable gain unit performs phase weighted adjustment on the I-path signal to generate a first phase-shifted signal and a second phase-shifted signal; the second variable gain unit performs amplitude weighted adjustment on the I-path signal to generate a first amplified signal and a second amplified signal; wherein the first amplified signal, the second amplified signal and the first phase-shifted signal and the second phase-shifted signal have the same phase; the third variable gain unit performs phase weighted adjustment on the Q-path signal to generate a third phase-shifted signal and a fourth phase-shifted signal; the fourth variable gain unit performs amplitude weighted adjustment on the Q-path signal to generate a third amplified signal and a fourth amplified signal; wherein the third amplified signal, the fourth amplified signal and the third phase-shifted signal and the fourth phase-shifted signal have the same phase; the I branch outputs the first orthogonal signal and the second orthogonal signal obtained by superimposing the gains of the first phase-shifted signal, the second phase-shifted signal and the first amplified signal and the second amplified signal, and the Q branch outputs the third orthogonal signal and the fourth orthogonal signal obtained by superimposing the gains of the third phase-shifted signal, the fourth phase-shifted signal and the third amplified signal and the fourth amplified signal.

[0051] Figure 4A FIG. 1 shows a schematic diagram of the structure of the I branch provided in an embodiment of the present disclosure. Figure 4B FIG. 2 shows a schematic diagram of the structure of the Q branch provided by an embodiment of the present disclosure. Figure 4A and Figure 4B As shown, the two input ends of the first variable gain unit 421 are respectively connected to the I+ signal end and the I- signal end, the two input ends of the second variable gain unit 422 are respectively connected to the I+ signal end and the I- signal end, and the two output ends of the first variable gain unit 421 are respectively connected to the two output ends of the second variable gain unit 422, and the first orthogonal signal and the second orthogonal signal are output; the two input ends of the third variable gain unit 423 are respectively connected to the Q+ signal end and the Q- signal end, and the two input ends of the fourth variable gain unit 424 are respectively connected to the Q+ signal end and the Q- signal end, and the two output ends of the third variable gain unit 423 are respectively connected to the two output ends of the fourth variable gain unit 424, and the third orthogonal signal and the fourth orthogonal signal are output.

[0052] In some embodiments, the gains of the first variable gain unit 421, the second variable gain unit 422, the third variable gain unit 423 and the fourth variable gain unit 424 are G1, G2, G3 and G4 respectively. The two input ends of the first variable gain unit 421 are connected to the I+ signal end and the I- signal end respectively, the two input ends of the second variable gain unit 422 are connected to the I+ signal end and the I- signal end respectively, the first phase-shifted signal and the second phase-shifted signal outputted from the two output ends of the first variable gain unit 421 are G1×I+, G1×I- respectively; the first amplified signal and the second amplified signal outputted from the two output ends of the second variable gain unit 422 are G2×I+, G2×I- respectively, and the I branch outputs a first orthogonal signal (G2+G1)×I+, a second orthogonal signal (G2+G1)×I-; The two input ends of the third variable gain unit 423 are connected to the Q+ signal end and the Q- signal end respectively, the two input ends of the fourth variable gain unit 424 are connected to the Q+ signal end and the Q- signal end respectively, the third phase-shifted signal and the fourth phase-shifted signal outputted by the two output ends of the third variable gain unit 423 are G3×Q+ and G3×Q- respectively; the third amplified signal and the fourth amplified signal outputted by the two output ends of the fourth variable gain unit 424 are G4×Q+ and G4×Q- respectively, and the third orthogonal signal outputted by the Q branch is (G4+G3)×Q+ and the fourth orthogonal signal (G4+G3)×Q-.

[0053] The vector synthesizer performs I / Q vector synthesis on the first orthogonal signal (G2+G1)×I+ and the third orthogonal signal (G4+G3)×Q+, and outputs the differential output signal Vout+ after vector synthesis, and performs I / Q vector synthesis on the second orthogonal signal (G2+G1)×I- and the fourth orthogonal signal (G4+G3)×Q-, and outputs the differential output signal Vout- after vector synthesis.

[0054] In some embodiments, the first variable gain unit, the second variable gain unit, the third variable gain unit and the fourth variable gain unit may be variable gain amplifiers (VGA, Variable Gain Amplifier).

[0055] Figure 5 FIG. 4 shows a schematic diagram of the structure of a first variable gain unit provided in an embodiment of the present disclosure, such as Figure 5 As shown, the first variable gain unit includes N first transistor units 310, and the N first transistor units 310 work in parallel; the first variable gain unit implements phase weighted control via one or more first transistor units 310 among the multiple first transistor units 310; N is an integer greater than or equal to 2.

[0056] The first gain control signal includes N first control signals Va0-VaN-1 (for clarity, Figure 5 Only Va0 is shown in the figure, and each first control signal controls a first transistor unit. For example, the first control signal Va0 controls the first first transistor unit, and the first control signal VaN-1 controls the Nth first transistor unit. Here, the first control signal can be a voltage signal.

[0057] The first gain control signal includes N first control signals. The first variable gain unit implements phase weighted control via one or more first transistor units among the plurality of first transistor units, so that the first variable gain unit can implement 2 N Different gain states.

[0058] It should be noted that Figure 5 Taking the first first transistor unit among the N first transistor units as an example, the first first transistor unit 310 includes a pair of first main transistors M1 and M4 and a pair of first cross-coupled transistors M2 and M3; the first main transistors M1 and M4 are connected to the first control signal Va0, and the first cross-coupled transistors M2 and M3 are connected to the inverted signal of the first control signal Va0. The signals connected to the first main transistors M1 and M4 and the first cross-coupled transistors M2 and M3 are inverted by inverters INV1 and INV2, respectively. Among them, the structure of each first transistor unit among the N first transistor units is the same.

[0059] In the disclosed embodiment, the transistors in the first transistor unit 310 can be connected in a common source manner, which can improve gain and reduce parasitic phase shift. Further, the first transistor unit 310 also includes a pair of first cross-coupled transistors M2 and M3, which can significantly reduce parasitic phase shift.

[0060] The gates of the first main transistor M1 and the first cross-coupling transistor M2 are connected to the I+ signal terminal, the gates of the first main transistor M4 and the first cross-coupling transistor M3 are connected to the I- signal terminal, the sources of the first main transistors M1, M4 and the first cross-coupling transistors M2, M3 are grounded, the drains of the first main transistor M1 and the first cross-coupling transistor M3 serve as the I+ output terminal of the first variable gain unit, and the drains of the first main transistor M4 and the first cross-coupling transistor M2 serve as the I- output terminal of the first variable gain unit.

[0061] The first transistor unit 310 further includes capacitors C1-C4 and resistors R1-R4, wherein the capacitors C1-C4 are filter capacitors and the resistors R1-R4 are filter resistors. The capacitors C1-C4 and the resistors R1-R4 form a filter network of the first transistor unit 310.

[0062] Figure 6 The structure of the second variable gain unit provided by the embodiment of the present disclosure is shown. Figure 1 ,like Figure 6 As shown, the second variable gain unit includes M second transistor units 410 .

[0063] The second gain control signal includes 2M second control signals Vb0-Vb2M-1 (for clarity, Figure 6 Only Vb0 and Vb1 are shown in the figure, and each two second control signals of the 2M second control signals Vb0-Vb2M-1 control one second transistor unit 410. For example, the second control signals Vb0 and Vb1 control the first second transistor unit, and the second control signals Vb2M-2 and Vb2M-1 control the Mth second transistor unit. Here, the second control signal can be specifically a voltage signal.

[0064] The second gain control signal includes 2M second control signals, and the second variable gain unit implements amplitude weighting adjustment in response to the difference between the two second control signals, so that the second variable gain unit can implement 2 M Different gain states.

[0065] It should be noted that Figure 6 Taking the first second transistor unit among the M second transistor units as an example, the first second transistor unit 410 includes a pair of second main transistors M5 and M8 and a pair of second cross-coupled transistors M6 and M7, and the first second variable gain unit 410 responds to the difference between the second control signals Vb0 and Vb1 to implement amplitude weighted adjustment. Specifically, the second main transistors M5 and M8 are connected to the second control signal Vb0, the second cross-coupled transistors M6 and M7 are connected to the second control signal Vb1, and the first second variable gain unit 410 responds to (Vb0-Vb1) to implement amplitude weighted adjustment.

[0066] In the disclosed embodiment, the transistors in the second transistor unit 410 are connected in a common source manner, which can improve gain and reduce parasitic phase shift. Further, the second transistor unit 410 also includes a pair of second cross-coupled transistors M6 and M7, which can significantly reduce parasitic phase shift.

[0067] The second transistor unit 410 may further include capacitors C5-C8 and resistors R5-R8, wherein the capacitors C5-C8 are filter capacitors and the resistors R5-R8 are filter resistors. The capacitors C5-C8 and the resistors R5-R8 form a filter network of the second transistor unit 410.

[0068] In the case where the first variable gain unit and the second variable gain unit are connected in parallel, the gates of the second main transistor M5 and the second cross-coupling transistor M6 are connected to the I+ signal terminal, the gates of the second main transistor M8 and the second cross-coupling transistor M7 are connected to the I- signal terminal, the sources of the second main transistors M5, M8 and the second cross-coupling transistors M6 and M7 are grounded, the drains of the second main transistor M5 and the second cross-coupling transistor M7 serve as the I+ output terminal of the second variable gain unit, and the drains of the second main transistor M8 and the second cross-coupling transistor M6 serve as the I- output terminal of the second variable gain unit. After the I+ output terminal of the first variable gain unit is connected to the I+ output terminal of the second variable gain unit, the first orthogonal signal is output; after the I- output terminal of the first variable gain unit is connected to the I- output terminal of the second variable gain unit, the second orthogonal signal is output.

[0069] In the case where the first variable gain unit and the second variable gain unit are connected in series, a first current multiplexing circuit is provided between the first variable gain unit and the second variable gain unit, for multiplexing the current of the first variable gain unit to the second variable gain unit, two input ends of the first current multiplexing circuit are connected to two output ends of the first variable gain unit, and two input ends of the second variable gain unit are connected to the output end of the first current multiplexing circuit. In the case where the third variable gain unit and the fourth variable gain unit are connected in series, a second current multiplexing circuit is provided between the third variable gain unit and the fourth variable gain unit, for multiplexing the current of the third variable gain unit to the fourth variable gain unit, two input ends of the second current multiplexing circuit are connected to two output ends of the third variable gain unit, and two input ends of the fourth variable gain unit are connected to the output end of the second current multiplexing circuit. Figure 7 FIG. 4 shows a schematic diagram of the structure of the gain amplification module provided in an embodiment of the present disclosure. Figure 7 As shown, the first current multiplexing circuit includes a first multiplexing unit 510 and a second multiplexing unit 520; the input end of the first multiplexing unit 510 is connected to the I+ output end of the first variable gain unit, and the input end of the second multiplexing unit 520 is connected to the I- output end of the first variable gain unit.

[0070] Specifically, the first multiplexing unit 510 includes a first AC branch and a first DC branch, and the second multiplexing unit 520 includes a second AC branch and a second DC branch; wherein, one end of the first AC branch is connected to the I+ output end of the first variable gain unit, and the other end is connected to the gate of the second main transistor M5' and the second cross-coupling transistor M6'; one end of the second AC branch is connected to the I- output end of the first variable gain unit, and the other end is connected to the gate of the second main transistor M8' and the second cross-coupling transistor M7'; one end of the first DC branch is connected to the I+ output end of the first variable gain unit, and the other end is connected to the source of the second main transistor M5' and the second cross-coupling transistor M6'; one end of the second DC branch is connected to the I- output end of the first variable gain unit, and the other end is connected to the source of the second main transistor M8' and the second cross-coupling transistor M7'.

[0071] In some embodiments, the first AC branch includes an inductor L1 and an inductor L5; the first DC branch includes an inductor L3 and a capacitor C9. The second AC branch includes an inductor L2 and an inductor L6; the second DC branch includes an inductor L4 and a capacitor C10. The capacitance values ​​of capacitors C9 and C10 are large to achieve the effect of isolating DC signals and allowing AC signals to pass. In addition, the inductors L1, L3, L5 in the first multiplexing unit 510 and the inductors L2, L4, L6 in the second multiplexing unit 520 are also used to achieve input / output matching between the first variable gain unit and the second variable gain unit.

[0072] In the embodiment of the present disclosure, the first current multiplexing circuit and the second current multiplexing circuit can realize the voltage division effect of the VDD power supply voltage to meet the application of high power supply voltage. For example, the drain of the transistor in the first variable gain unit can be connected to the VDD power supply voltage, the source of the transistor in the second variable gain unit is grounded, and the transistor in the first variable gain unit and the transistor in the second variable gain unit realize voltage division, thereby improving the high voltage resistance capability of the entire circuit.

[0073] In some embodiments, the impedance of the first AC branch is smaller than the impedance of the first DC branch; the impedance of the second AC branch is smaller than the impedance of the second DC branch, so that the RF signal can be fed into the gate of the transistor in the second variable gain unit to realize the common source connection relationship of the transistor in the second variable gain unit and achieve high gain.

[0074] In the embodiment of the present disclosure, the signal output by the first variable gain unit is fed into the gates of the second main transistors M5', M8' and the second cross-coupled transistors M6', M7' through the AC branches (the first AC branch and the second AC branch), thereby realizing the common source connection structure of the second main transistors M5', M8' and the second cross-coupled transistors M6', M7' in the second variable gain unit, thereby reducing the parasitic phase shift and achieving high gain.

[0075] In the embodiment of the present disclosure, the first current multiplexing circuit divides the drain voltage of the transistor in the first variable gain unit to the source of the transistor in the second variable gain unit, thereby multiplexing the current of the first variable gain unit to the second variable gain unit.

[0076] It should be noted that the structure of the second current multiplexing circuit is the same as that of the first current multiplexing circuit. The connection relationship between the second current multiplexing circuit and the third variable gain unit and the fourth variable gain unit can be understood by referring to the connection relationship between the first current multiplexing circuit and the first variable gain unit and the second variable gain unit, and will not be repeated in this article.

[0077] like Figure 7 As shown, the second variable gain unit includes N second transistor units 610, and the N second transistor units 610 work in parallel; the second variable gain unit implements phase weighted control via one or more second transistor units 610 among the multiple second transistor units 610; N is an integer greater than or equal to 2.

[0078] The second gain control signal includes N second control signals Vb0-VbN-1, each of which controls a second transistor unit. For example, the second control signal Vb0 controls the first second transistor unit, and the second control signal VbN-1 controls the Nth second transistor unit. Here, the second control signal can be a voltage signal.

[0079] The second gain control signal includes N second control signals. The second variable gain unit implements phase weighted control via one or more second transistor units among the plurality of second transistor units, so that the second variable gain unit can implement 2 N Different gain states.

[0080] It should be noted that Figure 7 Taking the first second transistor unit among the N second transistor units as an example, the first second transistor unit 610 includes a pair of second main transistors M5', M8' and a pair of second cross-coupled transistors M6', M7'; the second main transistors M5', M8' are connected to the second control signal Vb0, and the second cross-coupled transistors M6', M7' are connected to the inverted signal of the second control signal Vb0. The signals connected to the second main transistors M5', M8' and the second cross-coupled transistors M6', M7' are inverted by inverters INV3 and INV4, respectively. Among them, the structure of each second transistor unit among the N second transistor units is the same.

[0081] The gates of the second main transistor M5' and the second cross-coupling transistor M6' are connected to the output end of the first multiplexing unit 510, the gates of the second main transistor M8' and the second cross-coupling transistor M7' are connected to the output end of the second multiplexing unit 520, the drains of the second main transistor M5' and the second cross-coupling transistor M7' serve as the I+ output end of the second variable gain unit to output the first orthogonal signal, and the drains of the second main transistor M8' and the second cross-coupling transistor M6' serve as the I- output end of the second variable gain unit to output the second orthogonal signal.

[0082] In the disclosed embodiment, the transistors in the second transistor unit 610 are connected in a common source manner, which can improve gain and reduce parasitic phase shift. Further, the second transistor unit 610 also includes a pair of second cross-coupled transistors M6', M7', which can significantly reduce parasitic phase shift.

[0083] The second transistor unit 610 further includes capacitors C5'-C8' and resistors R5'-R8', wherein the capacitors C5'-C8' are filter capacitors and the resistors R5'-R8' are filter resistors. The capacitors C5'-C8' and the resistors R5'-R8' form a filter network of the second transistor unit 610.

[0084] In an embodiment of the present disclosure, the first variable gain unit includes M first transistor units; the first transistor unit includes a pair of first main transistors and a pair of first cross-coupled transistors; wherein the first gain control signal includes 2M first control signals, each two first control signals of the 2M first control signals control one first transistor unit, and the first main transistor and the first cross-coupled transistor are respectively connected to two different first control signals; the first variable gain unit realizes amplitude weighted adjustment in response to the difference between the two first control signals; M is an integer greater than or equal to 1.

[0085] In the disclosed embodiment, the transistors in the first transistor unit are connected in a common source manner, which can improve gain and reduce parasitic phase shift. Further, the first transistor unit also includes a pair of first cross-coupled transistors, which can significantly reduce parasitic phase shift.

[0086] In some other embodiments, the first variable gain unit and the second variable gain unit have the same structure. Figure 6 Thus, when the structures of the first variable gain unit and the second variable gain unit are the same, the specific circuit structure of the first variable gain unit can refer to Figure 6 The structure of the second variable gain unit shown in the figure can be understood and will not be described in detail in this article.

[0087] In the disclosed embodiment, the second variable gain unit further comprises a plurality of pairs of fixed gain transistors; the gates of the fixed gain transistors are connected to a fixed voltage, and the source and drain of each pair of fixed gain transistors are respectively connected to the source and drain of the second main transistor.

[0088] Figure 8 The structure of the second variable gain unit provided by the embodiment of the present disclosure is shown. Figure 2 ,like Figure 8 As shown, the second variable gain unit includes N second transistor units 610, and the N second transistor units 610 work in parallel; the second variable gain unit implements phase weighted control via one or more second transistor units 610 among the multiple second transistor units 610; N is an integer greater than or equal to 2.

[0089] The second gain control signal includes N second control signals Vb0-VbN-1, each of which controls a second transistor unit. For example, the second control signal Vb0 controls the first second transistor unit, and the second control signal VbN-1 controls the Nth second transistor unit. Here, the second control signal can be a voltage signal.

[0090] The second gain control signal includes N second control signals. The second variable gain unit implements phase weighted control via one or more second transistor units among the plurality of second transistor units, so that the second variable gain unit can implement 2 N Different gain states.

[0091] It should be noted that Figure 8 Taking the first second transistor unit among the N second transistor units as an example, the first second transistor unit 610 includes a pair of second main transistors M5', M8' and a pair of second cross-coupled transistors M6', M7'; the second main transistors M5', M8' are connected to the second control signal Vb0, and the second cross-coupled transistors M6', M7' are connected to the inverted signal of the second control signal Vb0. The signals connected to the second main transistors M5', M8' and the second cross-coupled transistors M6', M7' are inverted by inverters INV3 and INV4, respectively. Among them, the structure of each second transistor unit among the N second transistor units is the same.

[0092] The second variable gain unit 610 also includes a plurality of pairs of fixed gain transistors, and a pair of fixed gain transistors M9 and M10 are used as an example for explanation. The gates of the fixed gain transistors M9 and M10 are connected to a fixed voltage Vc, and the sources of the fixed gain transistors M9 and M10 are connected to the sources of the second main transistors M5', M8' and the second cross-coupled transistors M6' and M7' to form a common source connection structure. The drain of the fixed gain transistor M9 is connected to the drain of the second main transistor M5' and the second cross-coupled transistor M7', and they serve as the I+ output terminal of the second variable gain unit to output the first orthogonal signal; the drain of the fixed gain transistor M10 is connected to the drain of the second main transistor M8' and the second cross-coupled transistor M6', and they serve as the I- output terminal of the second variable gain unit to output the second orthogonal signal.

[0093] In the disclosed embodiment, when the number of transistor units in the first variable gain unit and the second variable gain unit is different, the size of the transistor may be different due to process deviation, thereby affecting the reliability of the gain. Multiple pairs of fixed gain transistors are used to provide fixed gain, and multiple pairs of fixed gain transistors can compensate for the gain instability caused by different transistor sizes, ensuring that the second variable gain unit can achieve the required gain. For example, in a specific example, by selectively setting the number and transistor parameters of multiple pairs of fixed gain transistors, the gain change of the second main transistor M5', M8' and the second cross-coupled transistor M6', M7' can be made 1 / 2 of the gain step of the first variable gain unit.

[0094] In some other embodiments, the structure of the second variable gain unit can be Figure 6 Thus, in the case where the second variable gain unit further includes a plurality of pairs of fixed gain transistors, the specific circuit structure of the second variable gain unit can be combined with Figure 6 and Figure 8 The structure shown in the figure can be understood and will not be described in detail in this article.

[0095] In some embodiments, the structures of the I branch and the Q branch are the same.

[0096] In the embodiment of the present disclosure, the third variable gain unit and the first variable gain unit have the same structure and the same connection method.

[0097] Specifically, the third variable gain unit and Figure 5 Thus, when the third variable gain unit has the same structure as the first variable gain unit, the specific circuit structure and connection method of the third variable gain unit can refer to Figure 5 The structure of the first variable gain unit shown in the figure can be understood and will not be described in detail herein.

[0098] In the embodiment of the present disclosure, the fourth variable gain unit and the second variable gain unit have the same structure and the same connection method.

[0099] Specifically, the fourth variable gain unit and Figure 6 or Figure 8 Thus, when the structure of the fourth variable gain unit is the same as that of the second variable gain unit, the specific circuit structure and connection method of the fourth variable gain unit can refer to Figure 6 or Figure 8 The structure of the second variable gain unit shown in the figure can be understood and will not be described in detail in this article.

[0100] In some embodiments, the ratio of the control bit of the first gain control signal to the control bit of the third gain control signal is the same as the ratio of the control bit of the second gain control signal to the control bit of the fourth gain control signal. In this way, the second variable gain unit and the fourth variable gain unit in the embodiment of the present disclosure can perform amplitude weighting under the premise of unchanged phase.

[0101] In the embodiment of the present disclosure, the gain ratio of the first variable gain unit to the third variable gain unit is the same as the gain ratio of the second variable gain unit to the fourth variable gain unit.

[0102] In some embodiments, the ratio of the phase of the I signal to the phase of the Q signal is the same as the ratio of the amplitude of the I signal to the amplitude of the Q signal. In other words, the second variable gain unit and the fourth variable gain unit in the embodiment of the present disclosure perform amplitude weighting under the premise of unchanged phase.

[0103] For “phase weighting”, the phase of the composite signal of the first phase-shifted signal and the second phase-shifted signal generated by the first variable gain unit and the third phase-shifted signal and the fourth phase-shifted signal generated by the third variable gain unit is: The amplitude is Wherein G1 is the gain of the first variable gain unit of the I branch, and G3 is the gain of the third variable gain unit of the Q branch.

[0104] The phase of the differential output signal Out+ and Out- obtained after I / Q vector synthesis by the vector synthesizer is Where G1 is the gain of the first variable gain unit of the I branch, and G3 is the gain of the third variable gain unit of the Q branch. The amplitude of the differential output signal Vout+ and Vout- obtained after I / Q vector synthesis by the vector synthesizer is Where G2 is the gain of the second variable gain unit of the I branch, and G4 is the gain of the fourth variable gain unit of the Q branch. The differential output signals Out+ and Out- obtained after I / Q vector synthesis by the vector synthesizer must also satisfy the relationship: 20lg((R2+R1) / R1)=deltaG, where deltaG represents the difference between the different gain states and the initial gain state in the dB coordinate system. In order to make the gain control meet the dB linear relationship, for a gain control requirement of an Xbit requirement, deltaG=K1*a should be set, where K1 is the minimum gain step required for gain control, and K1 is a constant. a=0, 1, 2, ..., 2 X .

[0105] The gains of the first variable gain unit to the fourth variable gain unit in the phase shifter depend on the first gain control signal to the fourth gain control signal. In physical terms, the phase shifter has only one state at the same time, and different control states can be formed by different first gain control signals to the fourth gain control signal, and the phase is shifted to any specific phase shift amount based on the step value within the phase shift range. For the Xbit phase shifter, the phase shift step value is 360 / (2 X In a specific example, a 6-bit phase shifter has 64-bit states, and the phase shift step value is 5.625°. The phase shift amount corresponding to the first state is 5.625°, and the phase shift amount corresponding to the 31st state is 174.375°.

[0106] It should be noted that the above structural description of the first variable gain unit to the fourth variable gain unit is only an exemplary description of the present disclosure. The structure of the first variable gain unit to the fourth variable gain unit of the present disclosure is not limited to the above structure, and other devices that can achieve variable gain can be applied to the present disclosure.

[0107] In the scheme disclosed in the present invention, the gain amplification module in the phase shifter can realize phase and amplitude modulation, and there is no need to set up an additional gain amplifier outside the phase shifter for amplitude modulation; the phase shifter is used as a separate module to simultaneously perform phase and amplitude modulation, and there is no need to set up matching circuits between the various units in the phase shifter. For example, there is no need to set up a matching circuit between the first variable gain unit and the second variable gain unit, and there is no need to set up a matching circuit between the third variable gain unit and the fourth variable gain unit, so that the matching circuit between the phase modulation part and the amplitude modulation part can be omitted, which can save chip area and help save power consumption.

[0108] In an embodiment of the present disclosure, a control module is further provided, which is used to output the first gain control signal to the fourth gain control signal to the phase shifter in the above embodiment; the control module is configured as follows:

[0109] Based on the target signal, the phase and amplitude of the target output signal are determined, and the target signal has a corresponding relationship with the phase and amplitude of the target output signal; wherein the target signal is a preset value, which is a predefined set value at different phases and / or different amplitudes of the target output signal. For example, when the phase of the target output signal is a first phase value and the amplitude is a first amplitude value, the target signal is a first target signal; when the phase of the target output signal is a second phase value and the amplitude is a second amplitude value, the target signal is a second target signal, and so on. The target signal is used to indicate the phase and amplitude of the target output signal, and the target signal can be obtained based on the phase and / or amplitude of the phased array beam. For example, according to the phase and / or amplitude of the phased array beam, the phase and amplitude of the signal in each transmitting link or receiving link are obtained, thereby obtaining the target signal. The target signal can be sent by a codec to the control module, and the codec can determine the phase and amplitude of the link signal where the phase shifter is located according to the direction of the current phased array beam, thereby obtaining the target signal corresponding to the phase shifter. The target signal may be a digital signal, and the target signal directly includes the phase value and amplitude value of the target output signal, for example, a phase value of 0101 indicates that the phase of the target output signal is 45°, a phase value of 0111 indicates that the phase of the target output signal is 60°, an amplitude value of 0011 indicates that the amplitude of the target output signal is f2, etc.; or, the target signal includes a code value, and different code values ​​correspond to different phase values ​​and amplitude values, for example, a code value of 0001 indicates that the phase of the target output signal is 0°, and the amplitude is f3, a code value of 0010 indicates that the phase of the target output signal is 10°, and the amplitude is f4, etc. The target output signal is the target of the differential output signal adjustment, and the phase and / or amplitude of the differential output signal is the same or substantially the same as the phase and / or amplitude of the target output signal.

[0110] Based on the phase and amplitude of the target output signal, the first gain control signal to the fourth gain control signal are determined, the phase of the target output signal has a corresponding relationship with the first gain control signal and the third gain control signal, and is used to adjust the phase weighting of the first variable gain unit and the third variable gain unit; the amplitude of the target output signal has a corresponding relationship with the second gain control signal and the fourth gain control signal, and is used to adjust the amplitude weighting of the second variable gain unit and the fourth variable gain unit.

[0111] Here, the target signal is the signal output by the phase shifter under the control of the control module, the target output signal is the signal output by the vector synthesizer in the phase shifter under the control of the control module, and the target output signal is a differential output signal. In other words, under the control of the control module, the phase and amplitude of the signal output by the phase shifter are the same as the phase and amplitude of the target signal, and the phase and amplitude of the differential output signal output by the vector synthesizer in the phase shifter are the same as the phase and amplitude of the target output signal.

[0112] In the disclosed embodiment, a phase shifter with phase and amplitude modulation functions is provided to split the control logic into control logic for controlling the phase and control logic for controlling the amplitude. Since the larger the number of bits of the control logic, the larger the parasitic capacitance, the larger the matching loss, and the lower the gain, high gain can be achieved by splitting the control logic in this way.

[0113] In the disclosed embodiment, Fig. 9 A control module block diagram provided by an embodiment of the present disclosure is shown. Fig. 9 As shown, the control module 700 includes a phase control module 710 and an amplitude control module 720; wherein the phase control module 710 is used to: determine the phase weighting of the target I-path signal and the phase weighting of the target Q-path signal according to the phase of the target output signal; determine the first gain control signal and the third gain control signal based on the phase weighting of the target I-path signal and the phase weighting of the target Q-path signal; the amplitude control module 720 is used to: determine the amplitude weighting of the target I-path signal and the amplitude weighting of the target Q-path signal according to the amplitude of the target output signal under the phase and according to the amplitude under the phase; determine the second gain control signal and the fourth gain control signal based on the amplitude weighting of the target I-path signal and the amplitude weighting of the target Q-path signal.

[0114] Fig.10 A control step flow chart provided by an embodiment of the present disclosure is shown as follows: Fig.10 As shown, the control steps include:

[0115] Step 801: determining the phase and amplitude of the target output signal based on the target signal, wherein the target signal has a corresponding relationship with the phase and amplitude of the target output signal;

[0116] Step 802: determining a phase weighting of a target I-path signal and a phase weighting of a target Q-path signal according to the phase of the target output signal; determining a first gain control signal and a third gain control signal based on the phase weighting of the target I-path signal and the phase weighting of the target Q-path signal;

[0117] Step 803: Determine the amplitude weighting of the target I-path signal and the amplitude weighting of the target Q-path signal according to the amplitude of the target output signal at the phase and the amplitude at the phase; determine the second gain control signal and the fourth gain control signal based on the amplitude weighting of the target I-path signal and the amplitude weighting of the target Q-path signal.

[0118] It should be noted that step 802 is executed by the phase control module 710, and step 803 is executed by the amplitude control module 720. There is no clear sequence relationship between step 802 and step 803, and step 802 and step 803 can be executed in parallel.

[0119] In some embodiments, the first gain control signal is used to control the phase of the target I-channel signal output by the first variable gain unit, and the third gain control signal is used to control the phase of the target Q-channel signal output by the third variable gain unit, so that the phase of the differential output signal obtained after I / Q vector synthesis based on the target I-channel signal and the target Q-channel signal is the same as the phase of the target output signal. The second gain control signal is used to control the amplitude of the target I-channel signal output by the second variable gain unit, and the fourth gain control signal is used to control the amplitude of the target Q-channel signal output by the fourth variable gain unit, so that the amplitude of the differential output signal obtained after I / Q vector synthesis based on the target I-channel signal and the target Q-channel signal is the same as the amplitude of the target output signal.

[0120] In the embodiment of the present disclosure, the ratio of the control bit of the first gain control signal to the control bit of the third gain control signal is the same as the ratio of the control bit of the second gain control signal to the control bit of the fourth gain control signal.

[0121] In a specific example, the control bit of the first gain control signal is w, the control bit of the second gain control signal is x, the control bit of the third gain control signal is y, and the control bit of the fourth gain control signal is z. The control bits of the first gain control signal to the fourth gain control signal must satisfy w / x=y / z.

[0122] Since the gain of VGA is proportional to its control bit, the gains of the first variable gain unit, the second variable gain unit, the third variable gain unit and the fourth variable gain unit can be expressed as G1=kw, G2=kx, G3=ky, G4=kz, respectively. Where k is a constant. For a 6-bit resolution phase shifter with 64-bit states, the gains corresponding to the 1st to 32nd states can be expressed as G1=kw, G2=kx, G3=ky, G4=kz, respectively, where w, x, y, z=0, 1, 2, ..., 31; the gains corresponding to the 33rd to 64th states can be expressed as G1=k(x-32), G2=k(n-32), G3=k(y-32), G4=k(m-32), respectively, where x, n, y, m=32, 33, 34, ..., 63.

[0123] In some embodiments, since the gain of the VGA is proportional to its control bit, the gain ratio of the first variable gain unit to the third variable gain unit is the same as the gain ratio of the second variable gain unit to the fourth variable gain unit. In other words, the ratio of the phase of the target I-channel signal to the phase of the target Q-channel signal is the same as the ratio of the amplitude of the target I-channel signal to the amplitude of the target Q-channel signal. In the disclosed embodiment, the second variable gain unit and the fourth variable gain unit perform amplitude weighting under the premise of keeping the phase unchanged.

[0124] In the embodiments of the present disclosure, Fig. 9 As shown, the control module 700 also includes a digital control module 730 and a DAC module 740. The digital control module 730 provides a digital signal to the DAC module, and the DAC module 740 converts the digital signal into a corresponding control signal. The DAC module 740 outputs the control signal to the gain amplifier module. In a specific example, the DAC module 740 outputs a first gain control signal to the first variable gain unit, outputs a second gain control signal to the second variable gain unit, outputs a third gain control signal to the third variable gain unit, and outputs a fourth gain control signal to the fourth variable gain unit; wherein the first gain control signal includes N first control signals, the second gain control signal includes 2M second control signals, the third gain control signal includes N third control signals, and the fourth gain control signal includes 2M fourth control signals. Each control signal from the first control signal to the fourth control signal corresponds to a control voltage, which is used to control the conduction and shutdown of the corresponding transistor. Here, each of the first control signal and the third control signal corresponds to a control bit, and every two control signals in the second control signal and the fourth control signal correspond to a control bit. In other words, each control bit corresponds to a control voltage. When the control bit is low, the corresponding control voltage is a turn-off voltage, which turns off the transistor. When the control bit is high, the corresponding control voltage is a turn-on voltage of the transistor, which turns on the transistor. The number of transistors turned off and on in the first variable gain unit to the fourth variable gain unit is controlled by a digital signal to change the gain of the first variable gain unit to the fourth variable gain unit.

[0125] As the control bit increases, the parasitic capacitance of the gain amplifier module will increase exponentially, the output matching loss will be large, and the gain of the overall circuit will be reduced. When the first variable gain unit and the second variable gain unit are connected in series, and the third variable gain unit and the fourth variable gain unit are connected in series, the digital signal / control signal of the gain amplifier module can be split into multiple levels. For example, for branch I, the digital signal / control signal is split into two levels, namely the digital signal / control signal of the first variable gain unit and the digital signal / control signal of the second variable gain unit. In this way, the parasitic capacitance of the gain amplifier module can be reduced to achieve high gain.

[0126] In the phase shifter of the embodiment of the present disclosure, the phase shifter includes an orthogonal signal generator, a gain amplifier module and a vector synthesizer, wherein the gain amplifier module includes an I branch and a Q branch, which are respectively used to control the phase weighting and amplitude weighting of the I signal and the phase weighting and amplitude weighting of the Q signal; wherein the I branch includes a first variable gain unit and a second variable gain unit; the first variable gain unit changes the phase weighting of the I signal based on the received first gain control signal; the second variable gain unit changes the amplitude weighting of the I signal based on the received second gain control signal; the Q branch includes a third variable gain unit and a fourth variable gain unit; the third variable gain unit changes the phase weighting of the Q signal based on the received third gain control signal; the fourth variable gain unit changes the amplitude weighting of the Q signal based on the received fourth gain control signal; the signal output by the gain amplifier module is input to the vector synthesizer, and after vector summation by the vector synthesizer, a differential output signal is synthesized. Relative to the input signal of the orthogonal signal generator, the phase and amplitude of the differential output signal are modulated.

[0127] In the scheme of the present application, the gain amplifier module in the phase shifter can realize phase and amplitude modulation, and there is no need to set up an additional gain amplifier outside the phase shifter for amplitude modulation; the phase shifter is used as a separate module to simultaneously perform phase and amplitude modulation, and there is no need to set up matching circuits between the various units in the phase shifter. For example, there is no need to set up a matching circuit between the first variable gain unit and the second variable gain unit, and there is no need to set up a matching circuit between the third variable gain unit and the fourth variable gain unit, so that the matching circuit between the phase modulation part and the amplitude modulation part can be omitted, which can save chip area and help save power consumption.

[0128] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0129] The above description is only a preferred embodiment of the present disclosure, and does not limit the patent scope of the present disclosure. All equivalent structural changes made by using the contents of the present disclosure and the drawings under the inventive concept of the present disclosure, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present disclosure.

Claims

1. A phase shifter, characterized in that: include: An orthogonal signal generator, used for generating an orthogonal I-path signal and a Q-path signal based on a differential input signal; A gain amplifier module, including an I branch and a Q branch; The I branch includes a first variable gain unit and a second variable gain unit; the first variable gain unit changes the phase weighting of the I signal based on the received first gain control signal; the second variable gain unit changes the amplitude weighting of the I signal based on the received second gain control signal; The Q branch includes a third variable gain unit and a fourth variable gain unit; the third variable gain unit changes the phase weighting of the Q branch signal based on the received third gain control signal; the fourth variable gain unit changes the amplitude weighting of the Q branch signal based on the received fourth gain control signal; The vector synthesizer is used to perform vector summation on the signals output by the gain amplification module to obtain a differential output signal.

2. The phase shifter according to claim 1, characterized in that: The first variable gain unit and the second variable gain unit are connected in series, and the third variable gain unit and the fourth variable gain unit are connected in series.

3. The phase shifter according to claim 2, characterized in that: The second variable gain unit is configured to perform amplitude weighted adjustment on the signal output by the first variable gain unit based on the second gain control signal; The fourth variable gain unit is configured to perform amplitude weighted adjustment on the signal output by the third variable gain unit based on the fourth gain control signal.

4. The phase shifter according to claim 2, characterized in that: The I branch further includes a first current multiplexing circuit, configured to multiplex the current of the first variable gain unit to the second variable gain unit; The Q branch further includes a second current multiplexing circuit for multiplexing the current of the third variable gain unit to the fourth variable gain unit.

5. The phase shifter according to claim 1, characterized in that: The first variable gain unit and the second variable gain unit are connected in parallel, and the third variable gain unit and the fourth variable gain unit are connected in parallel.

6. The phase shifter according to claim 1, characterized in that: The first variable gain unit includes N first transistor units, and the N first transistor units work in parallel; the first variable gain unit implements phase weighted control via one or more first transistor units among the plurality of the first transistor units; N is an integer greater than or equal to 2; The first transistor unit includes a pair of first main transistors and a pair of first cross-coupled transistors; wherein the first gain control signal includes N first control signals, each first control signal controls one of the first transistor units; one of the first main transistor and the first cross-coupled transistor is connected to the first control signal, and the other is connected to the inverted first control signal.

7. The phase shifter according to claim 1, characterized in that The first variable gain unit includes M first transistor units; the first transistor unit includes a pair of first main transistors and a pair of first cross-coupled transistors; wherein the first gain control signal includes 2M first control signals, each two first control signals of the 2M first control signals control one first transistor unit, and the first main transistor and the first cross-coupled transistor are respectively connected to two different first control signals; the first variable gain unit realizes amplitude weighted adjustment in response to the difference between the two first control signals; M is an integer greater than or equal to 1.

8. The phase shifter according to claim 1, characterized in that The second variable gain unit includes M second transistor units; the second transistor unit includes a pair of second main transistors and a pair of second cross-coupled transistors; wherein the second gain control signal includes 2M second control signals, every two second control signals of the 2M second control signals control one second transistor unit, and the second main transistor and the second cross-coupled transistor are respectively connected to two different second control signals; the second variable gain unit realizes amplitude weighted adjustment in response to the difference between the two second control signals; M is an integer greater than or equal to 1.

9. The phase shifter according to claim 1, characterized in that: The second variable gain unit includes N second transistor units, and the N second transistor units work in parallel; the second variable gain unit implements phase weighted control via one or more second transistor units among the plurality of the second transistor units; N is an integer greater than or equal to 2; The second transistor unit includes a pair of second main transistors and a pair of second cross-coupled transistors; wherein the second gain control signal includes N second control signals, each second control signal controls one second transistor unit; one of the second main transistor and the second cross-coupled transistor is connected to the second control signal, and the other is connected to the inverted second control signal.

10. The phase shifter according to claim 8 or 9, characterized in that: The second variable gain unit further includes a plurality of pairs of fixed gain transistors; the gates of the fixed gain transistors are connected to a fixed voltage, and the source and drain of each pair of the fixed gain transistors are respectively connected to the source and drain of the second main transistor.

11. The phase shifter according to claim 6 or 7, characterized in that: The third variable gain unit has the same structure as the first variable gain unit.

12. The phase shifter according to any one of claims 1 to 9, characterized in that: The fourth variable gain unit has the same structure as the second variable gain unit.

13. The phase shifter according to any one of claims 1 to 5, characterized in that: Also includes: Input balun and output balun; where, The input balun is used to convert the single-ended input signal into the differential input signal; The output balun is used to convert the differential output signal into a single-ended output signal.

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