Testing device of semiconductor packaging body
By designing a semiconductor package testing device including a conductive probe and a carrier, the problem of the electrical detection probe leaving indentation at the measured point is solved, and the effect of reducing the probability of indentation and improving product yield is achieved.
Patent Information
- Application Number
- CN202420077044.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-01-10
- Publication Date
- 2025-03-07
- Estimated Expiration
- 2034-01-10
AI Technical Summary
In the electrical properties of existing semiconductor packages, the electrical detection probe is prone to leave indentation marks at the measured point (sold ball area), resulting in poor appearance.
A test device for a semiconductor package is designed, including at least one test unit, each of which consists of a first probe, a second probe, a carrier seat and an insulating portion. The carrier seat is provided with a first groove and a second groove, the probe is arranged in the corresponding groove, the groove is located between the grooves, and the insulating portion is arranged in the groove to disperse the pressure of the probe evenly.
By increasing the contact area between the probe and the hot ball, the pressure applied to the hot ball is reduced, and the probability of the probe leaving a thorn mark (indentation) on the hot ball is effectively reduced, and the product yield is improved.
Smart Images
Figure CN222580197U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a testing device for a semiconductor package. Background Art
[0002] Nowadays, in order to meet the needs of various high-density packaging, the semiconductor packaging industry has gradually developed various forms of packaging structures, such as Flip Chip Ball Grid Array (FCBGA), Pin Grid Array (PGA), Land Grid Array (LGA), Chip On Board (COB), etc.
[0003] In the flip chip ball grid array packaging structure, the substrate used must be electrically tested after the production is completed. Only after the electrical test is passed can it be used to combine with the semiconductor chip and carry out the subsequent wire bonding or bumping steps, molding steps and solderball procedures. After the packaging is completed, the package body must also be electrically tested to screen out defective products caused by various factors during the packaging process.
[0004] In the existing electrical test, the electrical probe is generally used to directly contact the test point of the substrate, and then power is applied to detect its electrical performance. This method is easy to leave indentations (needle marks) on the test point (especially the solder ball area), causing poor appearance. Utility Model Content
[0005] In view of this, the present application proposes a testing device for a semiconductor package to reduce the probability of an electrical testing probe leaving an indentation on a test point (solder ball) and improve product yield.
[0006] A test device for a semiconductor package, comprising at least one test unit, each of which comprises a first probe, a second probe, a support seat and an insulating portion. The support seat is provided with a first groove and a second groove, the first probe is provided in the first groove, and the second probe is provided in the second groove. The support seat is also provided with a slot, the slot being located between the first groove and the second groove. The slot passes through the support seat along the height direction of the support seat, and the insulating portion is provided in the slot.
[0007] In one embodiment, when there are multiple test units, the test device further comprises a connecting portion connecting two adjacent test units, wherein one end of the connecting portion is fixed to a bearing seat of one of the test units, and the other end of the connecting portion is fixed to a bearing seat of an adjacent test unit.
[0008] In one embodiment, the bearing seat has a first surface and a second surface arranged opposite to each other. The first groove is formed by the first surface portion being recessed toward the second surface, and the second groove is formed by the first surface portion being recessed toward the second surface.
[0009] In one embodiment, the bearing seat is further provided with a third groove, and the third groove is formed by the second surface portion being recessed toward the first surface.
[0010] In one embodiment, the roughness of the inner wall of the third groove is less than or equal to Ra0.3.
[0011] In one embodiment, the semiconductor package comprises a substrate and a semiconductor element electrically connected to the substrate. The substrate is provided with a packaging portion, and the packaging portion covers the semiconductor element. A ball grid array is provided on a surface of the substrate away from the semiconductor element, and the third groove is configured to accommodate the ball grid array.
[0012] In one embodiment, a first pad is disposed on the semiconductor element, and a second pad is disposed on the substrate, and the first pad and the second pad are electrically connected via a wire.
[0013] In one embodiment, the packaging portion is made of epoxy resin.
[0014] In one embodiment, the first probe, the second probe and the support seat are all made of conductive materials, and the conductive materials include tungsten, steel, copper or gold.
[0015] In one embodiment, the insulating portion is made of polyethylene, polypropylene, polyimide, polyvinyl chloride, polyethylene terephthalate or polyethylene naphthalate.
[0016] The present application sets a supporting seat so that the pressure applied by the first probe and the second probe can be evenly dispersed to the entire solder ball through the supporting seat, that is, the contact area between the probe and the solder ball is increased, thereby reducing the pressure on the solder ball, and further reducing the probability of the probe leaving a puncture mark (indentation) on the solder ball. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figure 1 A front view of a testing device provided in one embodiment of the present application.
[0018] Figure 2 for Figure 1 A top view of the test setup is shown.
[0019] Figure 3 A front view of a testing device provided in accordance with another embodiment of the present application.
[0020] Figure 4 A schematic diagram of a semiconductor package provided in accordance with an embodiment of the present application.
[0021] Figure 5 for Figure 1 Schematic diagram of the test device shown when in use.
[0022] Figure 6 for Figure 3 Schematic diagram of the test device shown when in use.
[0023] Main component symbols
[0024] Test device 100
[0025] Test Unit 10
[0026] Connecting part 20
[0027] The first probe 11
[0028] The second probe 12
[0029] Bearing seat 13
[0030] Insulation part 14
[0031] The first groove 131
[0032] The second groove 132
[0033] The third groove 133
[0034] Slotting 130
[0035] First surface 101
[0036] Second surface 102
[0037] Semiconductor package 200
[0038] Substrate 201
[0039] Ball Grid Array 202
[0040] Solder ball 203
[0041] Semiconductor device 204
[0042] Packaging unit 205
[0043] First pad 206
[0044] Second pad 207
[0045] Wire 208
[0046] The following specific implementation manner will further illustrate the embodiments of the present application in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION
[0047] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the technical field of the present application. The terms used herein are only for the purpose of describing specific implementation methods and are not intended to limit the present application embodiments.
[0048] It should be noted that all directional indications in the embodiments of the present application (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.
[0049] It will be understood that when a layer is referred to as being "on" another layer, it can be directly on the other layer or an intervening layer may be present therebetween. Conversely, when a layer is referred to as being "directly on" another layer, there are no intervening layers. In the description of the present application, "plurality" means at least two, for example, two, three, etc., unless otherwise clearly and specifically defined.
[0050] It should be noted that when a component is referred to as being "fixed to" or "mounted on" another component, it may be directly on the other component or there may be a central component. When a component is considered to be "set on" another component, it may be directly set on the other component or there may be a central component at the same time.
[0051] Some embodiments of the present application are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.
[0052] See also Figure 1 and Figure 2 The present application provides a semiconductor package testing device 100, which can be used to perform electrical testing on a semiconductor package to detect whether the semiconductor package has open circuit or short circuit defects. The testing device 100 includes at least one testing unit 10. Figure 1 and Figure 2 The test device 100 includes only one test unit 10. In other embodiments, Figure 3 As shown, there may be multiple test units 10 .
[0053] like Figure 1 and Figure 2 As shown, each test unit 10 includes a first probe 11, a second probe 12, a bearing seat 13 and an insulating portion 14. The first probe 11, the second probe 12 and the bearing seat 13 are all made of conductive materials. The bearing seat 13 is provided with a first groove 131 and a second groove 132. The shape and size of the first groove 131 are adapted to the shape and size of the first probe 11, and the shape and size of the second groove 132 are adapted to the shape and size of the second probe 12. Therefore, the first probe 11 can be accommodated in the first groove 131, and the second probe 12 can be accommodated in the second groove 132. The first probe 11 can extend from the first groove 131, and the second probe 12 can extend from the second groove 132. The bearing seat 13 is also provided with a slot 130, which is located between the first groove 131 and the second groove 132. The slot 130 passes through the bearing seat 13 along the height direction of the bearing seat 13 (that is, the height direction of the first probe 11 and the second probe 12), and the insulating portion 14 is arranged in the slot 130. The insulating portion 14 is made of insulating material and is used to prevent the first probe 11 and the second probe 12 from being electrically connected.
[0054] like Figure 4 As shown, in some embodiments, the semiconductor package 200 may include a substrate 201 and a semiconductor element 204 electrically connected to the substrate 201. The substrate 201 may be, but not limited to, a printed circuit board (PCB), and the semiconductor element 204 may be, but not limited to, a chip, a diode, a triode, a field effect transistor, a thyristor, etc. A packaging portion 205 is provided on the substrate 201, and the packaging portion 205 covers the semiconductor element 204 and covers at least a portion of the surface of the substrate 201. The material of the packaging portion 205 may be, but not limited to, epoxy resin. A ball grid array (BGA) 202 is provided on the surface of the substrate 201 away from the semiconductor element 204, and the ball grid array 202 may be composed of a plurality of solder balls 203, and the plurality of solder balls 203 may be arranged in a matrix.
[0055] Furthermore, if Figure 4 As shown, a first pad 206 is provided on the semiconductor element 204, and a second pad 207 is provided on the substrate 201. The first pad 206 and the second pad 207 can be electrically connected via a wire 208, so that the substrate 201 is electrically connected to the semiconductor element 204. The wire 208 can be, but is not limited to, a gold wire, a silver wire, etc.
[0056] When in use, the first probe 11 can be connected to a power supply and an ammeter (not shown), and the second probe 12 can be connected to a voltmeter. Figure 5As shown, the surface of the support base 13 facing away from the first probe 11 (or the second probe 12) can be pressed against the solder ball 203 (the solder ball 203 changes from a spherical shape to a truncated cone shape due to being pressed), so that the electrical test of the semiconductor package 200 can be performed. Since the test device 100 of the present application is provided with a conductive support base 13, the support base 13 can evenly distribute the pressure applied by the first probe 11 and the second probe 12 to the entire solder ball 203 without affecting the electrical test function of the first probe 11 and the second probe 12, that is, the contact area between the probe (the first probe 11 and the second probe 12) and the solder ball 203 is increased, thereby reducing the pressure on the solder ball 203, and further reducing the probability of the probe leaving a puncture mark (indentation) on the solder ball 203.
[0057] In some embodiments, the support base 13 may be a cylinder. Figure 1 As shown, the bearing seat 13 has a first surface 101 and a second surface 102 that are arranged opposite to each other. The first groove 131 can be formed by partially recessing the first surface 101 toward the second surface 102, and the second groove 132 can be formed by partially recessing the first surface 101 toward the second surface 102. That is, the openings of the first groove 131 and the second groove 132 are oriented in the same direction, and both of the openings face the first surface 101. The first groove 131 and the second groove 132 can be spaced apart along the radial direction of the bearing seat 13, and the first groove 131 and the second groove 132 only penetrate part of the bearing seat 13 but not the entire bearing seat 13 along the height direction of the bearing seat 13 (that is, the height direction of the bearing seat 13).
[0058] Furthermore, if Figure 2 As shown, the extending direction (length direction) of the slot 130 may be perpendicular to the arrangement direction of the first groove 131 and the second groove 132. The slot 130 divides the support base 13 into two separated parts, so that the first probe 11 and the second probe 12 respectively located in the two grooves of the support base 13 are not conductive.
[0059] In some embodiments, Figure 1 As shown, the bearing seat 13 is further provided with a third groove 133. The third groove 133 can be formed by partially recessing the second surface 102 toward the first surface 101, and only penetrates a portion of the bearing seat 13 along the height direction of the bearing seat 13. The orthographic projection of the third groove 133 in the height direction of the bearing seat 13 can completely cover the orthographic projections of the first probe 11 and the second probe 12. Figure 5 As shown, when in use, the third groove 133 can be used to accommodate and abut a solder ball 203 of the semiconductor package 200, so that the contact between the support base 13 and the solder ball 203 is stable. The abutment means that the third groove 133 and the solder ball 203 are in contact and there is an interaction force between the two. The shape and size of the third groove 133 can be adjusted according to the shape and size of the solder ball 203.
[0060] Furthermore, the roughness of the inner wall (including the side wall and the bottom wall) of the third groove 113 is less than or equal to Ra 0.3 (Ra is the arithmetic mean of the surface roughness profile peak to the reference, and the roughness Ra 0.3 means that the arithmetic mean of the surface profile peak relative to the reference is 0.3 microns). In this way, the support seat 13 can be in more stable contact with the solder ball 203 (the surface of the solder ball 203 is relatively smooth) to prevent the solder ball 203 from turning white or atomizing.
[0061] In some embodiments, Figure 3 As shown, when there are multiple test units 10, the test device 100 further includes a connecting portion 20 connecting two adjacent test units 10. One end of the connecting portion 20 is fixed to the supporting seat 13 of one of the test units 10, and the other end of the connecting portion 20 is fixed to the supporting seat 13 of the test unit 10 adjacent to the test unit 10. When in use, Figure 6 As shown, each test unit 10 can contact a solder ball 203 , and multiple test units 10 can improve the detection efficiency.
[0062] Furthermore, the connecting portion 20 may be made of an insulating material, and the insulating material may be, but is not limited to, polyethylene (PE), polypropylene (PP), polyimide (PI), polyvinyl chloride (PVC), polyethylene terephthalate (PET) or polyethylene naphthalate diformic acid glycol ester (PEN), etc.
[0063] In some embodiments, the materials of the first probe 11, the second probe 12 and the bearing seat 13 are all conductive materials, and the conductive materials may be but are not limited to tungsten, steel, copper, gold, etc. The tungsten probe has good hardness, wear resistance and corrosion resistance, the steel probe has the advantage of being strong and durable, and the copper probe and the gold probe have good conductivity. The shapes of the first probe 11 and the second probe 12 may be but are not limited to round, square, pointed, spherical, conical, etc., and the present application does not limit them. The material of the bearing seat 13 may be the same as or different from the material of the probe, preferably the same, and the present application does not limit them.
[0064] In some embodiments, the material of the insulating portion 14 may be, but is not limited to, polyethylene, polypropylene, polyimide, polyvinyl chloride, polyethylene terephthalate, polyethylene naphthalate, and other polymer insulating materials.
[0065] The present application sets a supporting seat 13 so that the pressure applied by the first probe 11 and the second probe 12 can be evenly dispersed to the entire solder ball 203 through the supporting seat 13, that is, the contact area between the probe (the first probe 11 and the second probe 12) and the solder ball 203 is increased, thereby reducing the pressure on the solder ball 203, and further reducing the probability of the probe leaving a puncture mark (indentation) on the solder ball 203.
[0066] The above descriptions are some specific implementations of the present application, but they are not limited to these implementations in actual application. For ordinary technicians in this field, other variations and changes made according to the technical concept of the present application should all fall within the protection scope of the present application.
Claims
1. A semiconductor package testing device for performing electrical testing on a semiconductor package, characterized in that: The testing device includes at least one testing unit, each of which includes a first probe, a second probe, a supporting seat and an insulating part. The supporting seat is provided with a first groove and a second groove, the first probe is arranged in the first groove, and the second probe is arranged in the second groove; the supporting seat is also provided with a groove, the groove is located between the first groove and the second groove, the groove passes through the supporting seat along the height direction of the supporting seat, and the insulating part is arranged in the groove.
2. The semiconductor package testing device according to claim 1, wherein: When there are multiple test units, the test device further includes a connecting portion connecting two adjacent test units, one end of the connecting portion is fixed to a supporting seat of one of the test units, and the other end of the connecting portion is fixed to a supporting seat of an adjacent test unit.
3. The semiconductor package testing device according to claim 1, wherein: The bearing seat has a first surface and a second surface that are arranged opposite to each other. The first groove is formed by the first surface portion being recessed toward the second surface. The second groove is formed by the first surface portion being recessed toward the second surface.
4. The semiconductor package testing device according to claim 3, wherein: The bearing seat is further provided with a third groove, and the third groove is formed by the second surface portion being recessed toward the first surface.
5. The semiconductor package testing device as claimed in claim 4, wherein: The roughness of the inner wall of the third groove is less than or equal to Ra 0.
3.
6. The semiconductor package testing device as claimed in claim 4, wherein: The semiconductor package includes a substrate and a semiconductor element electrically connected to the substrate. A packaging portion is provided on the substrate, and the packaging portion covers the semiconductor element. A ball grid array is provided on the surface of the substrate away from the semiconductor element. The third groove is configured to accommodate the ball grid array.
7. The semiconductor package testing device according to claim 6, wherein: A first pad is disposed on the semiconductor element, and a second pad is disposed on the substrate. The first pad and the second pad are electrically connected via a wire.
8. The semiconductor package testing device according to claim 6, wherein: The packaging part is made of epoxy resin.
9. The semiconductor package testing device according to claim 1, wherein: The first probe, the second probe and the supporting seat are all made of conductive materials, and the conductive materials include tungsten, steel, copper or gold.
10. The semiconductor package testing device according to claim 1, wherein: The material of the insulating part includes polyethylene, polypropylene, polyimide, polyvinyl chloride, polyethylene terephthalate or polyethylene naphthalate.