Wafer test structure
By designing a wafer test structure with disconnected metal welding pads and connected to different devices to be tested, the problem of limited number of devices to be tested in the prior art is solved, and stronger testing capabilities and better device performance analysis are achieved.
Patent Information
- Application Number
- CN202421246766.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-03
- Publication Date
- 2025-03-07
- Estimated Expiration
- 2034-06-03
Smart Images
Figure CN222581164U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the field of integrated circuit manufacturing, in particular to a wafer testing structure. Background Art
[0002] WAT (Wafer Acceptance Test) is a wafer acceptance test. In order to conduct WAT testing, a wafer test structure (Testkey) is usually formed based on the wafer. The WAT test uses the wafer test structure to perform electrical testing on the device under test. The purpose is to detect whether there are any abnormalities in the process and to determine whether the device under test meets the electrical specification requirements of the corresponding process technology platform, so as to analyze and improve the device performance.
[0003] The existing wafer test structure usually includes a plurality of devices to be tested (such as resistors, capacitors, inductors or transistors, etc.) formed outside the chip area, such as the scribe line area, and a plurality of metal pads connecting the devices to be tested. Figure 1 Through the back-end process, each connection end of the device under test 10 is connected to the metal connection line M1-a of the first metal layer M1 through the contact plug (CT), and is connected to the metal pad PAD set in the first metal layer M1 through the metal connection line M1-a. M1 , metal pad PAD M1 The metal pad PAD provided in the second metal layer M2 is connected to the metal through hole (V1) between the first metal layer M1 and the second metal layer M2. M2 , and so on, so that each connection end of the device under test 10 is connected to the corresponding metal pad in each metal layer, so the device under test 10 can be subjected to WAT test in each metal layer.
[0004] In the above-mentioned wafer test structure, each metal layer is provided with a metal pad connected to all the devices under test. Therefore, the larger the number of devices under test is, the more metal pads need to be provided in each metal layer, so that the wafer occupies a larger area. However, in practice, the wafer occupancy area of the wafer test structure is limited. When the area of each metal layer is not sufficient to arrange a sufficient number of metal pads, the number of devices under test that can be tested by the wafer test structure is also limited, which will result in more devices under test being unable to use this wafer test structure for WAT testing, resulting in low testing capability and affecting the analysis and improvement of device performance. Utility Model Content
[0005] In order to increase the number of devices to be tested by a wafer test structure to improve the test capability when the wafer test structure occupies the same wafer area, the utility model provides a wafer test structure.
[0006] The wafer testing structure provided by the utility model comprises:
[0007] a plurality of devices under test formed in a surface area of the substrate; and
[0008] A plurality of metal layers are stacked in sequence in a direction away from the substrate, the device under test and the metal layers and the plurality of metal layers are isolated by dielectric materials, a plurality of metal pad areas are distributed laterally in the stacked structure of the plurality of metal layers, and each of the metal layers has a plurality of metal pads formed corresponding to the metal pad areas;
[0009] Wherein, at least two adjacent metal pads corresponding to the same metal pad area are disconnected and respectively connected to different devices under test.
[0010] Optionally, at least two adjacent metal pads corresponding to the same metal pad area are connected via a metal through hole provided in the dielectric material.
[0011] Optionally, the plurality of metal pads in each of the metal layers are arranged in an array.
[0012] Optionally, in a top view, a plurality of metal pads formed corresponding to the same metal pad area overlap.
[0013] Optionally, all the metal pads in any of the metal layers are connected to only a portion of the devices under test.
[0014] Optionally, at least one of the devices under test is connected to the metal pads in at least two of the metal layers.
[0015] Optionally, the multiple metal layers include a first metal layer closest to the substrate; wherein, some of the devices under test are connected to the metal wires of the first metal layer through contact plugs arranged in the dielectric material, and are connected to the metal pads in the first metal layer through the metal wires in the first metal layer, and another part of the devices under test are connected to the metal wires in the first metal layer through contact plugs arranged in the dielectric material, but are disconnected from the metal pads in the first metal layer.
[0016] Optionally, the multiple metal layers include a second metal layer adjacent to the first metal layer; the other part of the device under test is connected to the metal wire of the second metal layer through a metal through hole set in the dielectric material, and is connected to the metal pad in the second metal layer through the metal wire in the second metal layer.
[0017] Optionally, the multiple metal layers include an Nth metal layer located on the first metal layer, where N is an integer greater than or equal to three; the other part of the device under test is connected to the metal wire of the Nth metal layer, and is connected to the metal pad in the Nth metal layer through the metal wire in the Nth metal layer.
[0018] Optionally, the other part of the device under test is disconnected from any of the metal pads located below the Nth metal layer; or, the other part of the device under test is connected to part of the metal pads located below the Nth metal layer.
[0019] The wafer test structure provided by the utility model includes a plurality of devices to be tested formed on the surface area of the substrate and a plurality of metal layers arranged in sequence in a direction away from the substrate, the stacked structure of the plurality of metal layers is laterally distributed with a plurality of metal pad areas, each of the metal layers has a plurality of metal pads formed corresponding to the metal pad areas, and at least two adjacent metal pads corresponding to the same metal pad area are disconnected and respectively connected to different devices to be tested. Compared with a test structure in which the metal pads corresponding to the same metal pad area are all connected to the same device to be tested, the wafer test structure provided by the utility model can connect different devices to be tested with the metal pads corresponding to the same metal pad area, so that the number of devices to be tested can be greater while the wafer area occupied remains unchanged, thereby having a stronger test capability, which is helpful for analyzing and improving device performance. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] Figure 1 The present invention is a cross-sectional schematic diagram of an existing wafer test structure.
[0021] Figure 2 It is a cross-sectional schematic diagram of a wafer testing structure in one embodiment of the utility model.
[0022] Figure 3 It is a top view schematic diagram of a first device under test connected to a first metal layer in an embodiment of the utility model.
[0023] Figure 4 It is a top view schematic diagram of a second device under test connected to a second metal layer in an embodiment of the utility model. DETAILED DESCRIPTION
[0024] The wafer test structure of the utility model is further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the utility model will become clearer. It should be understood that the drawings in the specification are all in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the utility model. It should be understood that spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation described in the figure. For example, if the structure in the figure is inverted or positioned in other different ways (such as rotated), the exemplary term "on..." may also include "under..." and other orientation relationships.
[0025] In an embodiment of the utility model, a wafer test structure includes a plurality of devices to be tested formed in a surface area of a substrate and a plurality of metal layers arranged sequentially in a direction away from the substrate, the devices to be tested and the metal layers and the plurality of metal layers are isolated by dielectric materials, a stacked structure of the plurality of metal layers is laterally distributed with a plurality of metal pad areas, each of the metal layers has a plurality of metal pads formed corresponding to the metal pad areas, wherein at least two adjacent metal pads corresponding to the same metal pad area are disconnected and respectively connected to different devices to be tested.
[0026] The substrate may be a silicon substrate, a silicon germanium substrate, a silicon carbide substrate, a silicon on insulator (SOI) substrate, a germanium on insulator substrate, a silicon germanium on insulator substrate or a III-V compound substrate (such as a gallium nitride substrate or a gallium arsenide substrate), etc., or may be other substrates for carrying semiconductor components known to those skilled in the art. The device to be tested and the metal layer may be formed outside the chip area of the substrate, such as in the cutting path area, and may be manufactured simultaneously with the device and the metal layer in the chip area. The device to be tested may include a resistor, a capacitor, an inductor or a transistor, etc. As an example, the multiple devices to be tested in the wafer test structure include, for example, Figures 2 to 4 The first device under test D1 and the second device under test D2 are shown. Each device under test, for example, includes two independent connection terminals, and in each of the metal layers in the wafer test structure, at least two metal pads are connected to one device under test, and at least two metal pads are connected to another device under test. However, it is not limited thereto, for example, in another embodiment, at least one device under test may also include more than three connection terminals, and / or at least two devices under test have a common connection terminal.
[0027] Reference Figures 2 to 4, multiple metal layers (such as the first metal layer M1 and the second metal layer M2) are stacked in sequence in a direction away from the substrate (not shown), and the device under test and the metal layers and the multiple metal layers are isolated by dielectric materials (not shown). The stacked structure of the multiple metal layers has multiple metal pad areas distributed laterally, such as Figure 2 The first metal pad area A1 and the second metal pad area A2 are shown, and each of the metal layers has a plurality of metal pads formed corresponding to the metal pad areas. For example, the first metal layer M1 corresponds to the first metal pad area A1 and the second metal pad area A2 to form a first metal pad PAD M1 , and the second metal layer M2 corresponds to the second metal pad area A1 and the second metal pad area A2 to form a second metal pad PAD M2 , so that the number of metal pads in each metal layer is the same and corresponds to each other. In a top view, the multiple metal pads formed corresponding to the same metal pad area overlap, for example, partially overlap or completely overlap. The multiple metal pad areas are, for example, arranged in an array, so that the multiple metal pads in each metal layer are, for example, arranged in an array, such as arranged in multiple rows and columns.
[0028] like Figures 2 to 4 As shown, the multiple metal layers in the wafer test structure include a first metal layer M1 closest to the substrate and a second metal layer M2 formed on the first metal layer M1. Through a contact plug CT in a dielectric material disposed between the device under test and the first metal layer M1, each of the devices under test, such as the first device under test D1 and the second device under test D2, is connected to a metal connection line of the first metal layer M1. As an example, the first device under test D1 is connected to a first metal connection line M1-a in the first metal layer M1, the second device under test D2 is connected to a second metal connection line M1-b in the first metal layer M1, and the first metal connection line M1-a and the second metal connection line M1-b are disconnected.
[0029] In order to ensure that the metal pads that can be set in multiple metal layers can meet the test requirements of as many devices under test as possible when the wafer test structure occupies an unchanged wafer area, this embodiment enables the metal pads corresponding to the same metal pad area to test different devices under test. To this end, in the wafer test structure, at least two adjacent metal pads corresponding to the same metal pad area are disconnected and respectively connected to different devices under test, such as Figure 2 As shown, the two first metal pads PAD in the first metal layer M1 M1 Connect the first device under test D1 and the two first metal pads PAD M1 Two second metal pads PAD corresponding to the same metal pad area M2Connect the second device under test D2, and the first metal pad PAD corresponding to the first metal pad area A1 M1 and the second metal pad PAD M2 Disconnect, corresponding to the first metal pad PAD of the second metal pad area A2 M1 and the second metal pad PAD M2 disconnect.
[0030] Compared to Figure 1 Each device under test is connected to the test structure of the metal pad in the same metal layer. In this embodiment, in order to reduce the wafer area occupied by the wafer test structure while the number of devices under test remains unchanged, or to increase the number of devices under test while the wafer test structure occupies the same wafer area, the test capability is improved, so that the metal pads corresponding to the same metal pad area can test different devices under test, and all the metal pads in any of the multiple metal layers are only connected to part of the devices under test. Figure 2 , part of the DUT (i.e., part of the number of DUTs, taking the first DUT D1 as an example) is connected to the first metal pad PAD in the first metal layer M1 through the metal connection M1-a in the first metal layer M1. M1 The other part of the DUT (i.e., another part of the number of DUTs, taking the second DUT D2 as an example) is connected to the metal connection line M1-b in the first metal layer M1 through the contact plug CT set in the dielectric material, and is not connected to the first metal pad PAD in the first metal layer M1. M1 connection, that is, the other part of the device under test is not on the first metal pad PAD M1 After forming, test it.
[0031] Reference Figures 2 to 4 As an example, the other part of the device under test, such as the second device under test D2, is connected to the metal connection line M2-a of the second metal layer M2 through the metal through hole V1 in the dielectric material between the first metal layer M1 and the second metal layer M2, and is connected to the second metal pad PAD in the second metal layer M2 through the metal connection line M2-a. M2 connect( Figure 2 In the embodiment, part of the metal connection line M2-a and the second metal pad PAD M2 Not in the same cross section, so it is indicated by a dotted line), that is, the other part of the device under test can be on the second metal pad PAD of the second metal layer M2 M2 After the formation, the test is performed. The second metal pad PAD to which the second device under test D2 is connected M2 A first metal pad PAD connected to the first device under test D1 M1It can be seen that the wafer test structure uses the metal pads formed in the first metal pad area A1 and the second metal pad area A2 to test the first device under test D1 and the second device under test D2. Figure 1 The test structure shown increases the number of devices to be tested without increasing the wafer occupied area.
[0032] Not connected to the first metal pad PAD in the first metal layer M1 M1 The other part of the DUT (such as the second DUT D2) connected is not limited to the second metal pad PAD provided by the second metal layer M2. M2 For example, in another embodiment, the plurality of metal layers include an Nth metal layer (not shown) located on the first metal layer M1, N is an integer greater than or equal to three, and the second device under test D2 can be connected to the metal connection line of the Nth metal layer through the metal through hole between the Nth metal layer and the (N-1)th metal layer, and connected to the metal pad provided in the Nth metal layer through the metal connection line in the Nth metal layer; further, the second device under test D2 and any metal pad below the Nth metal layer can be disconnected, that is, the second device under test D2 is not tested below the Nth metal layer, or the second device under test D2 can also be connected to some metal pads below the Nth metal layer, that is, the second device under test D2 can be tested not only in the Nth metal layer, but also in the metal layer below the Nth metal layer.
[0033] In order to allow some specified DUTs to be tested on more than two metal layers, in the wafer test structure of the above embodiment, two metal pads located in adjacent metal layers and corresponding to the same metal pad area may also be connected to each other. Optionally, at least two adjacent metal pads corresponding to the same metal pad area are connected via metal vias provided in the dielectric material. By connecting metal pads of different metal layers, in some embodiments, at least one DUT is connected to metal pads in at least two metal layers (i.e., at least one DUT is connected to two or more metal layers and to metal pads in corresponding metal layers), for example, some DUTs are connected to the first metal pad PAD of the first metal layer M1. M1 , the first metal pad PAD M1 Further connected to the metal pads corresponding to the same metal pad area in the upper metal layer, the part of the device under test is connected to the metal pads in each metal layer, so that the test can be performed after each metal layer is formed.
[0034] In the wafer test structure described in the above embodiment, by using metal pads corresponding to the same metal pad area to perform testing in different metal layers, each metal layer does not need to be provided with metal pads that meet the testing requirements of all devices to be tested, and all the metal pads in any metal layer can be connected only to a part of the devices to be tested, that is, the number of metal pads in each metal layer is only sufficient to connect to a part of the devices to be tested.
[0035] In the wafer test structure described in the above embodiment, the metal pads corresponding to the same metal pad area can be connected to different devices to be tested, so that the wafer test structure can test more devices to be tested while occupying the same wafer area, compared with the test structure in which all the metal pads corresponding to the same metal pad area are connected to the same devices to be tested. The wafer test structure of the utility model has a stronger testing capability and is helpful for analyzing and improving device performance.
[0036] The above description is only a description of the preferred embodiment of the utility model, and is not any limitation on the scope of rights of the utility model. Any technical personnel in this field can make possible changes and modifications to the technical solution of the utility model by using the methods and technical contents disclosed above without departing from the spirit and scope of the utility model. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the utility model without departing from the content of the technical solution of the utility model are within the protection scope of the technical solution of the utility model.
Claims
1. A wafer testing structure, characterized in that: include: a plurality of devices under test formed in a surface area of the substrate; as well as A plurality of metal layers are stacked in sequence in a direction away from the substrate, the device under test and the metal layers and the plurality of metal layers are isolated by dielectric materials, a plurality of metal pad areas are distributed laterally in the stacked structure of the plurality of metal layers, and each of the metal layers has a plurality of metal pads formed corresponding to the metal pad areas; Wherein, at least two adjacent metal pads corresponding to the same metal pad area are disconnected and respectively connected to different devices under test.
2. The wafer testing structure according to claim 1, characterized in that: At least two adjacent metal pads corresponding to the same metal pad area are connected via a metal through hole disposed in the dielectric material.
3. The wafer testing structure according to claim 1, characterized in that: The plurality of metal pads in each of the metal layers are arranged in an array.
4. The wafer testing structure according to claim 1, wherein: In a top view, a plurality of metal pads formed corresponding to the same metal pad region overlap.
5. The wafer testing structure according to claim 1, wherein: All the metal pads in any one of the metal layers are connected to only a portion of the devices under test.
6. The wafer testing structure according to claim 1, characterized in that: At least one of the devices under test is connected to the metal pads in at least two of the metal layers.
7. The wafer testing structure according to claim 1, characterized in that: The multiple metal layers include a first metal layer closest to the substrate; wherein, part of the devices under test are connected to the metal wires of the first metal layer through contact plugs arranged in the dielectric material, and are connected to the metal pads in the first metal layer through the metal wires in the first metal layer, and another part of the devices under test are connected to the metal wires in the first metal layer through contact plugs arranged in the dielectric material, but are disconnected from the metal pads in the first metal layer.
8. The wafer testing structure according to claim 7, characterized in that: The multiple metal layers include a second metal layer adjacent to the first metal layer; the other part of the device under test is connected to the metal wire of the second metal layer through a metal through hole set in the dielectric material, and is connected to the metal pad in the second metal layer through the metal wire in the second metal layer.
9. The wafer testing structure according to claim 7, characterized in that: The multiple metal layers include an Nth metal layer located on the first metal layer, where N is an integer greater than or equal to three; the other part of the device under test is connected to the metal wire of the Nth metal layer, and is connected to the metal pad in the Nth metal layer through the metal wire in the Nth metal layer.
10. The wafer testing structure according to claim 9, characterized in that: The other part of the device under test is disconnected from any of the metal pads located below the Nth metal layer; or, the other part of the device under test is connected to part of the metal pads located below the Nth metal layer.