Display panel

Abstract

The utility model discloses a display panel which comprises a display area and a non-display area and further comprises a plurality of test terminals, a plurality of thin film transistors, a plurality of first data signal lines, a plurality of second data signal lines and a plurality of control signal lines. The first data signal line, the test terminal, the thin film transistor, the second data signal line and the control signal line are arranged in the non-display area, and the thin film transistor comprises a semiconductor layer, a first insulating layer arranged on the semiconductor layer, a grid electrode arranged on the first insulating layer, a source electrode electrically connected with the semiconductor layer and a drain electrode electrically connected with the semiconductor layer. One of the source electrode and the drain electrode is electrically connected with the first data signal line, the other one of the source electrode and the drain electrode is electrically connected with the second data signal line, the control signal line is electrically connected with the grid electrode, the semiconductor layer is further provided with an open hole, and the open hole is located between the source electrode and the grid electrode or / and the open hole is located between the drain electrode and the grid electrode.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel. Background Art

[0002] The data signal line in the non-display area of ​​the OLED display panel is electrically connected to the test terminal between the signal input terminal at the input end of the driver chip and the signal output terminal at the output end of the driver chip, and is connected to the detection circuit. During the production process of the OLED display panel, static electricity is easily accumulated on the test terminal. The charge accumulated on the test terminal will be transmitted to the detection circuit of the OLED display panel through the data signal line, causing static electricity damage to the thin film transistor of the detection circuit. Utility Model Content

[0003] The embodiments of the present application provide a display panel to improve the problem that the thin film transistors of the detection circuit of the display panel are prone to electrostatic damage.

[0004] In a first aspect, an embodiment of the present application provides a display panel, the display panel comprising a display area and a non-display area, the non-display area being provided with a plurality of test terminals and a plurality of detection circuits, the detection circuit being electrically connected to the test terminals, the detection circuit comprising a plurality of thin film transistors, a plurality of first data signal lines, a plurality of second data signal lines and a plurality of control signal lines, the thin film transistor comprising a semiconductor layer, a first insulating layer disposed on the semiconductor layer, a gate disposed on the first insulating layer, a source electrode electrically connected to the semiconductor layer and a drain electrode electrically connected to the semiconductor layer, one of the source electrode or the drain electrode being electrically connected to the first data signal line, the other of the source electrode or the drain electrode being electrically connected to the second data signal line, and the control signal line being electrically connected to the gate electrode; the semiconductor layer comprising a first portion and a second portion located on both sides of the first portion, in a top view of the display panel, the first portion overlaps with the gate electrode, the second portion is located between the source electrode and the gate electrode or the second portion is located between the drain electrode and the gate electrode, the length of the first portion in the first direction is greater than the length of the second portion in the first direction, wherein the first direction is the same as the extension direction of the control signal line.

[0005] Furthermore, the second part is provided with an opening.

[0006] Furthermore, a notch is provided on the second portion, and the notch is recessed from the edge of the semiconductor layer toward the center of the semiconductor layer.

[0007] Furthermore, the display panel further includes a substrate and a first metal layer. The first metal layer is disposed on a surface of the first insulating layer away from the substrate. The gate and the first data signal line are located on the first metal layer.

[0008] Furthermore, the display panel further includes a second insulating layer, which is disposed on a surface of the first insulating layer away from the substrate, and covers the first data signal line and the control signal line.

[0009] Furthermore, the display panel also includes a second metal layer, which is arranged on a surface of the second insulating layer away from the substrate, and the source and the drain are located in the second metal layer, the source is electrically connected to the semiconductor layer through a first via hole penetrating the film layer between the second metal layer and the semiconductor layer, and the drain is electrically connected to the semiconductor layer through a second via hole penetrating the film layer between the second metal layer and the semiconductor layer.

[0010] Furthermore, the first data signal line is electrically connected to one of the source or the drain through a third via hole penetrating the film layer between the first metal layer and the second metal layer.

[0011] Furthermore, in the top view of the display panel, the source electrode does not overlap with the edge of the opening, and the drain electrode does not overlap with the edge of the opening.

[0012] Furthermore, an opening is provided between the source and the gate, an opening is provided between the drain and the gate, and the number of the openings between the source and the gate is equal to the number of the openings between the drain and the gate.

[0013] Furthermore, a ratio of a distance between the source and the gate or a distance between the drain and the gate to a length of an overlapping region between the gate and the semiconductor layer in a second direction ranges from 1.5 to 2.5, wherein the second direction is perpendicular to the first direction.

[0014] Beneficial effects of this application:

[0015] The display panel provided in the present application is configured such that the semiconductor layer includes a first portion and a second portion located on both sides of the first portion, wherein the first portion overlaps the gate electrode, the second portion is located between the source electrode and the gate electrode or the second portion is located between the drain electrode and the gate electrode, and the length of the first portion in the first direction is greater than the length of the second portion in the first direction, thereby reducing the area of ​​the semiconductor layer in the first direction, thereby increasing the resistance between the source electrode and the gate electrode and / or the resistance between the drain electrode and the gate electrode, and enhancing the antistatic capability of the thin film transistor of the detection circuit, thereby improving the problem that the thin film transistor of the detection circuit is easily damaged by electrostatic explosion due to static electricity being introduced into the detection circuit from the test terminal. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a schematic diagram of a display panel in the present application;

[0017] Figure 2 yes Figure 1 A schematic diagram of position A of the display panel shown;

[0018] Figure 3 yes Figure 2 A schematic diagram of position B of the display panel shown;

[0019] Figure 4 yes Figure 3 A cross-sectional view of a display panel taken at position CC′ is shown.

[0020] 100-display area, 110-first data signal line; 200-non-display area, 210-test terminal, 220-thin film transistor, 221-semiconductor layer, 221a-first part, 221b-second part, 2211-opening, 222-first insulating layer, 223-gate, 224-source, 225-drain, 226-second insulating layer, 227-first via hole, 228-second via hole, 229-third insulating layer, 230-second data signal line, 240-control signal line, 250 signal input terminal, 260-signal output terminal, 270-detection circuit, 300-substrate. DETAILED DESCRIPTION

[0021] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. The technical solutions described below are only used to explain and illustrate the ideas of the present application and should not be regarded as limiting the scope of protection of the present application.

[0022] In addition, the terms "first", "second" and similar words do not indicate any order, quantity or importance, but are only used to distinguish different technical features. The term "plurality" and similar words mean two or more, unless otherwise clearly defined.

[0023] The data signal line in the non-display area of ​​the OLED display panel is electrically connected to the test terminal between the signal input terminal at the input end of the driver chip and the signal output terminal at the output end of the driver chip, and is connected to the detection circuit. During the production process of the OLED display panel, static electricity is easily accumulated on the test terminal. The charge accumulated on the test terminal will be transmitted to the detection circuit of the OLED display panel through the data signal line, causing static electricity damage to the thin film transistor of the detection circuit.

[0024] The embodiment of the present application provides a display panel, referring to Figure 1-Figure 4 The display panel includes a display area 100 and a non-display area 200, the non-display area 200 surrounds the display area 100, the display panel includes a plurality of test terminals 210, a plurality of first data signal lines 110 and a detection circuit 270, the detection circuit 270 includes a plurality of thin film transistors 220, a plurality of second data signal lines 230 and a plurality of control signal lines 240, the first data signal lines 110, the test terminals 210, the thin film transistors 220, the second data signal lines 230 and the control signal lines 240 are arranged in the non-display area 200, the thin film transistor 220 includes a semiconductor layer 221, a first insulating layer 222 arranged on the semiconductor layer 221, a gate 223 arranged on the first insulating layer 222, a source 224 electrically connected to the semiconductor layer 221 and a source 224 electrically connected to the semiconductor layer 221. The connected drain 225, one of the source 224 or the drain 225 is electrically connected to the first data signal line 110, the other of the source 224 or the drain 225 is electrically connected to the second data signal line 230, the control signal line 240 is electrically connected to the gate 223, the semiconductor layer 221 includes a first portion 221a and a second portion 221b located on both sides of the first portion 221a, in the top view of the display panel, the first portion 221a overlaps with the gate, the second portion 221b is located between the source 224 and the gate 223 or the second portion 221b is located between the drain 225 and the gate 223, the length of the first portion 221a in the first direction is greater than the length of the second portion 221b in the first direction, wherein the first direction Y is the same as the extension direction of the control signal line 240.

[0025] By arranging the semiconductor layer 221 to include a first portion 221a and a second portion 221b located on both sides of the first portion 221a, the first portion 221a overlaps with the gate, the second portion 221b is located between the source 224 and the gate 223 or the second portion 221b is located between the drain 225 and the gate 223, and the length of the first portion 221a in the first direction is greater than the length of the second portion 221b in the first direction, the area of ​​the semiconductor layer 221 in the first direction can be reduced, thereby increasing the resistance between the source 224 and the gate 223 and / or the resistance between the drain 225 and the gate 223, and enhancing the antistatic ability of the thin film transistor 220 of the detection circuit 270, thereby improving the problem that the thin film transistor 220 of the detection circuit 270 is easily damaged by electrostatic explosion caused by static electricity introduced into the detection circuit 270 from the test terminal 210.

[0026] In this embodiment, the second portion 211b is provided with an opening 2211. Since the second portion 211b is located between the source 224 and the gate 223 or between the drain 225 and the gate 223, the second portion 211b is provided with the opening 2211, so that the area of ​​the semiconductor layer 221 in the first direction can be reduced, thereby increasing the resistance between the source and the gate or / and the resistance between the drain and the gate, and enhancing the antistatic ability of the thin film transistor of the detection circuit.

[0027] In this embodiment, the display panel further includes a plurality of signal input terminals 250 and a plurality of signal output terminals 260 , wherein the test terminal 210 is located between the signal input terminals 250 and the signal output terminals 260 .

[0028] In this embodiment, the display panel further includes a substrate 300 and a first metal layer, the first metal layer is disposed on a surface of the first insulating layer 222 away from the substrate, and the gate 223 and the first data signal line 110 are located in the first metal layer. By disposing the gate 223 and the first data signal line 110 in the first metal layer, the gate 223 and the first data signal line 110 are in the same layer, which reduces the number of layers in the display panel during preparation, and reduces the cost and difficulty in the preparation of the display panel.

[0029] In this embodiment, the display panel further includes a second insulating layer 226 . The second insulating layer 226 is disposed on a surface of the first insulating layer 222 away from the substrate, and the second insulating layer 226 covers the first data signal line 110 and the control signal line 240 .

[0030] In the present embodiment, the display panel further includes a second metal layer, which is disposed on a surface of the second insulating layer 226 away from the substrate, the source electrode 224 and the drain electrode 225 are located in the second metal layer, the source electrode 224 is electrically connected to the semiconductor layer 221 through a first via hole 227 penetrating the film layer between the second metal layer and the semiconductor layer 221, and the drain electrode 225 is electrically connected to the semiconductor layer 221 through a second via hole 228 penetrating the film layer between the second metal layer and the semiconductor layer 221. By arranging the source electrode 224 and the drain electrode 225 in the second metal layer, the source electrode 224 is electrically connected to the semiconductor layer 221 through the first via hole 227 penetrating the film layer between the second metal layer and the semiconductor layer 221, and the drain electrode 225 is electrically connected to the semiconductor layer 221 through the second via hole 228 penetrating the film layer between the second metal layer and the semiconductor layer 221, it is ensured that the static electricity introduced from the test terminal can enter the detection circuit.

[0031] In this embodiment, the display panel further includes a second metal layer, which is disposed on a surface of the second insulating layer 226 away from the substrate, and the source electrode 224 is located in the second metal layer, and the source electrode 224 is electrically connected to the semiconductor layer 221 through a first via hole 227 penetrating the film layer between the second metal layer and the semiconductor layer 221. By arranging the source electrode 224 in the second metal layer, the source electrode 224 is electrically connected to the semiconductor layer 221 through the first via hole 227 penetrating the film layer between the second metal layer and the semiconductor layer 221, so as to ensure that the static electricity introduced from the test terminal can enter the detection circuit.

[0032] The display panel further includes a second metal layer, which is disposed on a surface of the second insulating layer 226 away from the substrate, and the drain electrode 225 is located on the second metal layer, and the drain electrode 225 is electrically connected to the semiconductor layer 221 through a second via hole 228 penetrating the film layer between the second metal layer and the semiconductor layer 221. By arranging the drain electrode 225 on the second metal layer, and the drain electrode 225 being electrically connected to the semiconductor layer 221 through the second via hole 228 penetrating the film layer between the second metal layer and the semiconductor layer 221, the resistance between the drain electrode 225 and the gate 223 can be increased, so as to ensure that the static electricity entering the detection circuit can be drawn out.

[0033] In this embodiment, the first data signal line 110 is electrically connected to one of the source electrode 224 or the drain electrode 225 through a third via hole (not shown in the figure) penetrating the film layer between the first metal layer and the second metal layer.

[0034] In this embodiment, the display panel further includes a third insulating layer 229 , and the third insulating layer 229 is located between the substrate 300 and the semiconductor layer 221 .

[0035] In this embodiment, in the top view of the display panel, the source electrode 224 does not overlap with the edge of the opening 2211. By setting the source electrode 224 and the edge of the opening 2211 not to overlap, it is possible to prevent the metal used to prepare the source electrode 224 from entering the opening 2211 and causing the thin film transistor 220 to be abnormal.

[0036] In this embodiment, in the top view of the display panel, the drain electrode 225 does not overlap with the edge of the opening 2211. By setting the drain electrode 225 and the edge of the opening 2211 not to overlap, it is possible to prevent the metal used to prepare the drain electrode 225 from entering the opening 2211 and causing the thin film transistor 220 to be abnormal.

[0037] In this embodiment, in the top view of the display panel, the gate 223 does not overlap with the edge of the opening 2211. By setting the gate 223 and the edge of the opening 2211 not to overlap, it is possible to prevent the metal used to prepare the gate 223 from entering the opening 2211 and causing the thin film transistor 220 to be abnormal.

[0038] In this embodiment, an opening 2211 is disposed between the source 224 and the gate 223 , and an opening 2211 is disposed between the drain 225 and the gate 223 .

[0039] In this embodiment, the number of openings 2211 between the source 224 and the gate 223 is equal to the number of openings 2211 between the drain 225 and the gate 223. By setting the number of openings 2211 between the source 224 and the gate 223 to be equal to the number of openings 2211 between the drain 225 and the gate 223, the voltage and current at different positions of the semiconductor layer 221 can be more balanced, thereby improving the working stability of the thin film transistor.

[0040] In this embodiment, the number of the openings 2211 located between the source 224 and the gate 223 is four, and the number of the openings 2211 located between the drain 225 and the gate 223 is four.

[0041] In this embodiment, the number of the openings 2211 between the source 224 and the gate 223 is five, and the number of the openings 2211 between the drain 225 and the gate 223 is five.

[0042] In this embodiment, the number of the openings 2211 located between the source 224 and the gate 223 is 6, and the number of the openings 2211 located between the drain 225 and the gate 223 is 6.

[0043] In this embodiment, a notch is provided on the second portion 221b, and the notch is recessed from the edge of the semiconductor layer 221 toward the center of the semiconductor layer 221. Since the second portion 211b is located between the source 224 and the gate 223 or between the drain 225 and the gate 223, a notch is provided on the second portion 211b, and the notch is recessed from the edge of the semiconductor layer 221 toward the center of the semiconductor layer 221, which can reduce the area of ​​the semiconductor layer 221 in the first direction, thereby increasing the resistance between the source and the gate or / and the resistance between the drain and the gate, and enhancing the antistatic ability of the thin film transistor of the detection circuit.

[0044] In this embodiment, in the top view of the display panel, the source electrode 224 does not overlap with the edge of the notch. By setting the source electrode 224 not to overlap with the edge of the notch, it is possible to prevent the metal used to prepare the source electrode 224 from entering the notch and causing the thin film transistor 220 to be abnormal.

[0045] In this embodiment, in the top view of the display panel, the drain electrode 225 does not overlap with the edge of the notch. By setting the drain electrode 225 not to overlap with the edge of the notch, it is possible to prevent the metal used to prepare the drain electrode 225 from entering the notch and causing the thin film transistor 220 to be abnormal.

[0046] In this embodiment, in the top view of the display panel, the gate 223 does not overlap with the edge of the notch. By setting the gate 223 not to overlap with the edge of the notch, it is possible to prevent the metal used to make the gate 223 from entering the notch and causing the thin film transistor 220 to be abnormal.

[0047] In this embodiment, a gap is provided between the source electrode 224 and the gate electrode 223 , and a gap is provided between the drain electrode 225 and the gate electrode 223 .

[0048] In this embodiment, the number of the gaps between the source electrode 224 and the gate electrode 223 is equal to the number of the gaps between the drain electrode 225 and the gate electrode 223. By setting the number of the gaps between the source electrode 224 and the gate electrode 223 to be equal to the number of the gaps between the drain electrode 225 and the gate electrode 223, the voltage and current at different positions of the semiconductor layer 221 can be more balanced, thereby improving the working stability of the thin film transistor.

[0049] In this embodiment, the ratio of the spacing a between the source electrode 224 and the gate electrode 223 or the spacing a between the drain electrode 225 and the gate electrode 223 to the length b of the overlapping area of ​​the gate electrode 223 and the semiconductor layer 221 in the second direction X is in the range of 1.5 to 2.5, wherein the second direction X is perpendicular to the first direction Y. By setting the ratio of the spacing a between the source electrode 224 and the gate electrode 223 or the spacing a between the drain electrode 225 and the gate electrode 223 to the length b of the overlapping area of ​​the gate electrode 223 and the semiconductor layer 221 in the second direction X to be in the range of 1.5 to 2.5, compared with the solution in which the spacing between the source electrode 224 and the gate electrode 223 or the spacing between the drain electrode 225 and the gate electrode 223 is the same as the length of the overlapping area of ​​the semiconductor layer 221 in the second direction X, the length of the semiconductor layer in the second direction X is increased, which, on the one hand, increases the resistance of the semiconductor layer and enhances the antistatic ability of the thin film transistor 220 of the detection circuit 270, and on the other hand, is more conducive to setting the opening on the second part, thereby improving the convenience of display panel manufacturing.

[0050] The technical solution of this application is specifically as follows:

[0051] The display panel includes a display area 100 and a non-display area 200. The non-display area 200 is provided with a signal input terminal 250, a plurality of signal output terminals 260 and a test terminal 210, wherein the test terminal 210 is located between the signal input terminal 250 and the signal output terminal 260. The non-display area also includes a detection circuit 270. The first data signal line 110 connected to the test terminal 210 is led out from the signal output terminal 260 and connected to the detection circuit 270, and then passes through the detection circuit 270 and is connected to the display area 100. The detection circuit 270 includes A plurality of thin film transistors 220, a plurality of second data signal lines 230 and a plurality of control signal lines 240, wherein the control signal line 240 is used to control the switching state of the thin film transistor 220, and the second data signal line 230 is used to provide a data voltage for the pixel unit. When detecting the display panel, the lighting detection circuit 270, when the voltage of the control signal line 240 is a low voltage, the thin film transistor 220 is turned on, and the data voltage of the second data signal line 230 is transmitted to the first data signal line 110 through the thin film transistor 220, and then sent to the display area 100.

[0052] However, since static electricity is easily accumulated on the test terminal 210, the charge accumulated on the test terminal 210 is transmitted to the detection circuit 270 of the OLED display panel through the first data signal line 110, causing static electricity to damage the thin film transistor 220 of the detection circuit 270. Therefore, the present application sets an opening 2211 on the semiconductor layer 221, and the opening 2211 is located between the source 224 and the gate 223 or / and the opening 2211 is located between the drain 225 and the gate 223, which can increase the resistance between the source 224 and the gate 223 or / and the resistance between the drain 225 and the gate 223, thereby enhancing the anti-static ability of the thin film transistor 220 of the detection circuit 270, thereby improving the problem of damage to the thin film transistor 220 of the detection circuit 270 caused by static electricity introduced into the detection circuit 270 from the test terminal 210.

[0053] The above is a detailed description of the specific implementation of the present application. The above implementation disclosed in the present application is only the preferred implementation of the present application. For ordinary technicians in this field, many modifications and improvements can be made without departing from the concept of the present application. These modifications and improvements all fall within the scope of protection defined by the claims of the present application.

Claims

1. A display panel, characterized in that: The display panel includes a display area and a non-display area. A plurality of test terminals and a plurality of detection circuits are arranged in the non-display area. The detection circuit is electrically connected to the test terminals. The detection circuit includes a plurality of thin film transistors, a plurality of first data signal lines, a plurality of second data signal lines, and a plurality of control signal lines. The thin film transistor includes a semiconductor layer, a first insulating layer arranged on the semiconductor layer, a gate arranged on the first insulating layer, a source electrode electrically connected to the semiconductor layer, and a drain electrode electrically connected to the semiconductor layer. One of the source electrode or the drain electrode is electrically connected to the first data signal line, the other of the source electrode or the drain electrode is electrically connected to the second data signal line, and the control signal line is electrically connected to the gate electrode. The semiconductor layer includes a first portion and a second portion located on both sides of the first portion. In a top view of the display panel, the first portion overlaps with the gate electrode, the second portion is located between the source electrode and the gate electrode, or the second portion is located between the drain electrode and the gate electrode. The length of the first portion in a first direction is greater than the length of the second portion in the first direction. The first direction is the same as the extending direction of the control signal line.

2. The display panel according to claim 1, characterized in that: The second part is provided with an opening.

3. The display panel according to claim 1 or 2, characterized in that: The second portion is provided with a notch, and the notch is recessed from the edge of the semiconductor layer toward the center of the semiconductor layer.

4. The display panel according to claim 1, characterized in that: The display panel further includes a substrate and a first metal layer. The first metal layer is disposed on a surface of the first insulating layer away from the substrate. The gate and the first data signal line are located on the first metal layer.

5. The display panel according to claim 4, characterized in that: The display panel further includes a second insulating layer, which is disposed on a surface of the first insulating layer away from the substrate, and covers the first data signal line and the control signal line.

6. The display panel according to claim 5, characterized in that: The display panel also includes a second metal layer, which is arranged on a surface of the second insulating layer away from the substrate, and the source and the drain are located in the second metal layer. The source is electrically connected to the semiconductor layer through a first via hole penetrating the film layer between the second metal layer and the semiconductor layer, and the drain is electrically connected to the semiconductor layer through a second via hole penetrating the film layer between the second metal layer and the semiconductor layer.

7. The display panel according to claim 6, characterized in that: The first data signal line is electrically connected to one of the source electrode or the drain electrode through a third via hole penetrating through a film layer between the first metal layer and the second metal layer.

8. The display panel according to claim 2, characterized in that: In a top view of the display panel, the source electrode does not overlap with an edge of the opening, and the drain electrode does not overlap with an edge of the opening.

9. The display panel according to claim 2, characterized in that: An opening is provided between the source electrode and the gate electrode, an opening is provided between the drain electrode and the gate electrode, and the number of the openings between the source electrode and the gate electrode is equal to the number of the openings between the drain electrode and the gate electrode.

10. The display panel according to claim 1, characterized in that: A ratio of a distance between the source and the gate or a distance between the drain and the gate to a length of an overlapping region between the gate and the semiconductor layer in a second direction ranges from 1.5 to 2.5, wherein the second direction is perpendicular to the first direction.

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