Multi-channel programmable frequency division coefficient frequency measuring device

Abstract

The utility model aims to provide the multi-channel programmable frequency division coefficient frequency measuring device which is low in testing cost, flexible, wide in measuring range and high in adaptability. The high-speed multi-channel time-sharing frequency divider comprises a high-speed multi-channel time-sharing selection module, a high-frequency shaping module, a programmable frequency divider module, a logic control module and a main control board, a tested frequency is accessed to the high-speed multi-channel time-sharing selection module, and the high-speed multi-channel time-sharing selection module is divided into three paths, a first path is connected to the programmable frequency divider module through the high-frequency shaping module, a second path is connected to the programmable frequency divider module through the logic control module, a third path is connected to the main control board through GPIO, and the programmable frequency divider module is connected with the main control board. The utility model is applied to the technical field of frequency measurement.

Description

Technical Field

[0001] The utility model is applied to the technical field of frequency measurement, and particularly relates to a multi-channel programmable frequency division coefficient frequency measuring device. Background Art

[0002] A frequency divider is an electronic circuit that makes the frequency of the output signal an integer fraction of the frequency of the input signal. For any N-times frequency divider, the output signal can have a phase of 2pi / N if the input signal remains unchanged. DUT refers to the device under test; MCU refers to the microcontroller unit; MLB refers to the master logic board; MUX refers to the multiplexer; GPIO refers to the general purpose input and output; ESD refers to electrostatic discharge.

[0003] The clock system is the core content of the benchmark of consumer electronic products. The internal clock of electronic products is often multiplied / divided according to the crystal oscillator clock to provide the clock benchmark for various functional modules such as SOC / MCU. Therefore, the clock accuracy directly affects the working performance of the product system. In the motherboard test of 3C products, in addition to testing the most basic crystal oscillator clock, the clock after multiplication / division is often required to be measured. Clock frequency measurement is an important measurement content; multi-channel frequency measurement and wide-range frequency measurement have become common requirements for test system design.

[0004] Currently, in MLB test systems, frequency meters or high-speed FPGAs are commonly used to measure high-speed clock frequencies. However, the existing frequency divider technology has few channels, a single frequency division number, a narrow measurement range, a large size, and a high cost. Therefore, it is necessary to provide a multi-channel programmable frequency division coefficient measurement device with low test cost, flexibility, a wide measurement range, and strong adaptability. Utility Model Content

[0005] The technical problem to be solved by the utility model is to overcome the deficiencies of the prior art and provide a multi-channel programmable frequency division coefficient measuring device which has low test cost, flexibility, wide measuring range and strong adaptability.

[0006] The technical solution adopted by the utility model is: the utility model includes a high-speed multi-channel time-sharing selection module, a high-frequency shaping module, a programmable frequency divider module, a logic control module and a main control board. The measured frequency is connected to the high-speed multi-channel time-sharing selection module. The high-speed multi-channel time-sharing selection module is divided into three paths. The first path is connected to the programmable frequency divider module via the high-frequency shaping module, the second path is connected to the programmable frequency divider module via the logic control module, and the third path is connected to the main control board via GPIO. The programmable frequency divider module is connected to the main control board.

[0007] As can be seen from the above scheme, the present application proposes a low-cost and simple-to-use solution for the needs of multi-channel frequency measurement and wide-range frequency measurement, aiming to simplify the structure, reduce costs, and improve the reliability and maintainability of the system, thereby overcoming the problems of large size, high cost, and insufficient measurement range of the prior art. Compared with the existing optimal technology, the present application has the following significant advantages:

[0008] Flexibility: This application realizes independent and flexible frequency division processing of different channel signals through a programmable frequency division module, and can dynamically adjust the frequency division coefficient according to the characteristics of the frequency to be measured, greatly improving the system's ability to adapt to different frequency ranges;

[0009] Resource optimization: Compared with the traditional fixed-division ratio measurement method, this application can optimize the allocation of hardware resources for specific application scenarios, reduce unnecessary hardware overhead, thereby reducing test costs and improving cost-effectiveness;

[0010] In summary, the present application provides a more efficient, accurate and adaptable multi-channel frequency measurement solution, which breaks through the limitations of the prior art in multi-channel, wide frequency range and high-precision applications.

[0011] A preferred solution is that the measured frequency is connected to the CH1_85_E85_ATC0_USB_RX2_P pin, CH1_85_E85_ATC0_USB_RX2_N pin, CH1_85_E85_ATC0_USB_RX1_P pin, and CH1_85_E85_ATC0_USB_RX1_N pin of the high-speed multi-channel time-sharing selection module, and the CH1_FREQ_IN pin of the high-speed multi-channel time-sharing selection module is connected to the same-direction input end of the high-frequency shaping module.

[0012] A preferred solution is that the output end of the high-frequency shaping module is connected to the CH1_E85_USB_P pin of the programmable divider module, and the CH1_S7 pin, CH1_S6 pin, and CH1_S5 pin of the programmable divider module are connected to the corresponding pins of the logic control module.

[0013] A preferred solution is that the IO pin of the high-speed multi-channel time-sharing selection module, the CH1_CLK_OUT pin of the programmable frequency divider module, and the pin of the logic control module are connected to the corresponding pins of the main control board. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a structural block diagram of the utility model;

[0015] Figure 2 is a circuit schematic diagram of the high-speed multi-channel time-sharing selection module;

[0016] Figure 3 is a circuit schematic diagram of the high-frequency shaping module;

[0017] Figure 4 is a circuit schematic diagram of the programmable frequency divider module;

[0018] Figure 5 is a circuit schematic diagram of the logic control module;

[0019] Figure 6 It is the truth table of the corresponding relationship between AD9515 logic level and frequency division coefficient. DETAILED DESCRIPTION

[0020] like Figure 1 As shown, in this embodiment, the utility model includes a high-speed multi-channel time-sharing selection module 1, a high-frequency shaping module 2, a programmable frequency divider module 3, a logic control module 4 and a main control board 5. The measured frequency is connected to the high-speed multi-channel time-sharing selection module 1. The high-speed multi-channel time-sharing selection module 1 is divided into three paths. The first path is connected to the programmable frequency divider module 3 via the high-frequency shaping module 2, the second path is connected to the programmable frequency divider module 3 via the logic control module 4, and the third path is connected to the main control board 5 via GPIO. The programmable frequency divider module 3 is connected to the main control board 5.

[0021] The measured frequency is input into the high-speed multi-channel time-sharing selection module 1 after ESD protection and low-pass filtering. The high-speed multi-channel time-sharing selection module 1 can be controlled by the GPIO of the main control board 5 to select the required measured frequency and input it into the high-frequency shaping module 2 at the back end. The high-frequency shaping module 2 first removes the DC component in the measured frequency, and re-adds the DC component with the Vref voltage as a reference, and compares it with the Vref voltage to output a regular square wave signal with a rated amplitude and input it into the programmable divider module 3 at the back end. The programmable divider module 3 selects the division coefficient through the special logic control module 4. By controlling the programmable divider module 3, the measured frequency can be divided into 1-32 and the high-speed measured frequency can be converted into the timer frequency and level testable range of the main control board 5.

[0022] like Figure 2 and Figure 3As shown, in this embodiment, the measured frequency is connected to the CH1_85_E85_ATC0_USB_RX2_P pin, CH1_85_E85_ATC0_USB_RX2_N pin, CH1_85_E85_ATC0_USB_RX1_P pin, and CH1_85_E85_ATC0_USB_RX1_N pin of the high-speed multi-channel time-sharing selection module 1, and the CH1_FREQ_IN pin of the high-speed multi-channel time-sharing selection module 1 is connected to the same-direction input end of the high-frequency shaping module 2.

[0023] The high-speed multi-channel time-sharing selection module 1 is mainly composed of ESD protection, low-pass filtering and high-speed MUX. The main function of ESD protection is to prevent external electrostatic discharge from damaging the tested frequency signal circuit of the test loop; the high-speed MUX can realize the program-controlled selection of the tested frequency through the MCU. The selection of high-speed MUX can be selected according to the amplitude, bandwidth and number of tested frequencies of the measured signal. The high-speed MUX in this application uses SN74CB3Q3251, which has a -3db bandwidth of 500MHz and has the advantages of low on-resistance, programmable and low cost.

[0024] like Figure 3 and Figure 4 As shown, in this embodiment, the output end of the high frequency shaping module 2 is connected to the CH1_E85_USB_P pin of the programmable divider module 3, and the CH1_S7 pin, CH1_S6 pin, and CH1_S5 pin of the programmable divider module 3 are connected to the corresponding pins of the logic control module 4.

[0025] The high-frequency shaping module 2 is mainly composed of a DC blocking capacitor, a DC component, and a high-speed comparator. The high-frequency shaping module 2 first removes the DC component in the measured frequency, and re-adds the DC component with the Vref voltage as a reference, and compares it with the Vref voltage to output a regular square wave signal of the rated amplitude. The high-speed comparator can select different models according to the actual input frequency. The high-speed comparator in this application adopts LTC6752ISC6, which has the advantages of input and output power rail components, 280MHz high-speed switching frequency, less than 2.9ns transmission delay, low dead zone voltage, low static power consumption, and adjustable hysteresis.

[0026] like Figure 4 and Figure 5 As shown, in this embodiment, the IO pin of the high-speed multi-channel time-sharing selection module 1, the CH1_CLK_OUT pin of the programmable frequency divider module 3, and the pin of the logic control module 4 are connected to the corresponding pins of the main control board 5.

[0027] The programmable frequency divider module 3 mainly realizes the frequency division output of the high-speed measured frequency. The frequency divider in this application adopts AD9515BCPZ of ADI Company, which supports 1.6GHz differential frequency input / output, and also supports single-ended input, 800 MHz / 250 MHz LVDS / CMOS level output, and can select LVPECL / LVDS / CMOS level output, with a minimum input voltage of 150mV. The chip has logic control input pins S0-S10, which can use four levels to program the frequency division coefficient.

[0028] This application uses CMOS level output, and programs S5-S7 with 4 logic levels to achieve programmable control of the frequency division coefficient from 1 to 32. Figure 5 As shown, the 4-level logic control of the divider S5-S7 is realized by a four-choice MUX, and the GPIO control MUX can realize any logic level control of S5-S7; Figure 6 As shown in the figure, the corresponding relationship between different logic levels of AD9515BCPZ S5-S7 pins and the frequency division coefficient.

Claims

1. A multi-channel programmable frequency division coefficient frequency measuring device, characterized in that: It comprises a high-speed multi-channel time-sharing selection module (1), a high-frequency shaping module (2), a programmable frequency divider module (3), a logic control module (4) and a main control board (5); the measured frequency is connected to the high-speed multi-channel time-sharing selection module (1); the high-speed multi-channel time-sharing selection module (1) is divided into three paths, the first path is connected to the programmable frequency divider module (3) via the high-frequency shaping module (2); the second path is connected to the programmable frequency divider module (3) via the logic control module (4); the third path is connected to the main control board (5) via GPIO; the programmable frequency divider module (3) is connected to the main control board (5).

2. A multi-channel programmable frequency division coefficient frequency measuring device according to claim 1, characterized in that: The measured frequency is connected to the CH1_85_E85_ATC0_USB_RX2_P pin, the CH1_85_E85_ATC0_USB_RX2_N pin, the CH1_85_E85_ATC0_USB_RX1_P pin, and the CH1_85_E85_ATC0_USB_RX1_N pin of the high-speed multi-channel time-sharing selection module (1), and the CH1_FREQ_IN pin of the high-speed multi-channel time-sharing selection module (1) is connected to the same-direction input terminal of the high-frequency shaping module (2).

3. A multi-channel programmable frequency division coefficient frequency measuring device according to claim 1, characterized in that: The output end of the high-frequency shaping module (2) is connected to the CH1_E85_USB_P pin of the programmable frequency divider module (3), and the CH1_S7 pin, CH1_S6 pin, and CH1_S5 pin of the programmable frequency divider module (3) are connected to corresponding pins of the logic control module (4).

4. A multi-channel programmable frequency division coefficient frequency measuring device according to claim 1, characterized in that: The IO pins of the high-speed multi-channel time-sharing selection module (1), the CH1_CLK_OUT pin of the programmable frequency divider module (3), and the pins of the logic control module (4) are connected to corresponding pins of the main control board (5).

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