Chip packaging structure

Abstract

The utility model discloses a chip packaging structure, which is characterized in that the chip packaging structure comprises a substrate and a chip, and the chip is a stress sensitive chip; the area, where the chip is to be mounted, of the surface of the substrate is provided with a box dam structure, an adhesive is arranged in a space enclosed by the box dam structure, and the height of the adhesive is greater than that of the box dam structure in the thickness direction of the substrate; and the chip is fixedly connected with the substrate through the adhesive. According to the chip packaging structure, the dam structure is arranged in the area, where the chip is to be mounted, of the surface of the substrate, and the adhesive is arranged in the space defined by the dam structure, so that the height of the adhesive is ensured, the consistency of the thickness of the adhesive is ensured, the stress transmitted to the chip by the substrate is reduced, and the reliability of the chip packaging structure is improved. And the detection sensitivity and reliability of the chip are improved.

Description

Technical Field

[0001] The utility model relates to the field of semiconductor packaging, in particular to a chip packaging structure. Background Art

[0002] The traditional packaging method is to apply glue on a flat substrate and place the chip. For stress-sensitive chips, a softer adhesive glue is needed to stack them into a higher shape. However, the softer the glue, the higher the stacking. The softer the glue, the easier it is to collapse and cannot be stacked to the set height, thus failing to play a good stress isolation role. As a result, stress-sensitive chips will still be subjected to excessive stress, affecting the detection sensitivity of the product.

[0003] One common implementation method is to use an anti-dry etchant to pattern the chip surface. The disadvantage of this method is that the patterns of these special-shaped structures on the chip surface will affect chip thinning, and this type of anti-dry etchant has a high halogen content and does not meet SGS requirements. Utility Model Content

[0004] In view of the above problems, an object of the present invention is to provide a chip packaging structure to solve the problems existing in the prior art.

[0005] According to one aspect of the utility model, a chip packaging structure is provided, the chip packaging structure comprising a substrate and a chip, the chip being a stress-sensitive chip; a dam structure is provided in an area on the surface of the substrate where the chip is to be mounted, an adhesive is provided in a space enclosed by the dam structure, and in a thickness direction of the substrate, a height of the adhesive is greater than a height of the dam structure; the chip is fixedly connected to the substrate via the adhesive.

[0006] In some embodiments, the dam structure is made of a hard material.

[0007] In some embodiments, the dam structure is integrally formed with the substrate.

[0008] In some embodiments, the dam structure and the substrate are separate, and the dam structure is attached to the surface of the substrate in an area where the chip is to be mounted by attaching.

[0009] In some embodiments, the geometric shape of the dam structure is polygonal or circular.

[0010] In some embodiments, the adhesive includes a first adhesive layer and a second adhesive layer stacked together, wherein the first adhesive layer is accommodated in the dam structure in the thickness direction of the substrate, and the height of the first adhesive layer is less than or equal to the height of the dam structure, and the second adhesive layer is connected to the first adhesive layer.

[0011] In some embodiments, the first adhesive layer and the second adhesive layer are different adhesive materials.

[0012] In some embodiments, in the thickness direction of the substrate, a projection of a portion of the dam structure on a surface of the substrate facing the chip is outside a projection range of the chip on a surface of the substrate facing the chip.

[0013] In some embodiments, in the thickness direction of the substrate, a projection of a portion of the chip on a surface of the substrate facing the chip is outside a projection range of the dam structure on the surface of the substrate facing the chip.

[0014] In some embodiments, at least one supporting structure is further provided in the space enclosed by the dam structure, and the adhesive covers the at least one supporting structure.

[0015] In some embodiments, in the thickness direction of the substrate, a height of the at least one support structure is greater than or equal to a height of the dam structure.

[0016] In some embodiments, the substrate is provided with a through hole penetrating through the thickness of the substrate, and the dam structure is provided around the through hole.

[0017] In some embodiments, the dam structure includes an inner dam wall and an outer dam wall, and in the thickness direction of the substrate, the height of the outer dam wall is equal to the height of the inner dam wall.

[0018] In some embodiments, at least one pad is disposed on the substrate, and the chip is electrically connected to the corresponding pad via a connecting wire.

[0019] In some embodiments, a signal processor chip is disposed on the substrate, and the signal processor chip is electrically connected to the chip.

[0020] In the chip packaging structure provided by the utility model, the dam structure is formed by etching, machining or mounting, and the dam structure is higher than the surface of the substrate facing the chip in the thickness direction of the substrate. An adhesive is provided in the space enclosed by the dam structure, which not only ensures the height of the adhesive, but also ensures the consistency of the thickness of the adhesive, reduces the stress transmitted from the substrate to the chip, and improves the detection sensitivity and reliability of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings of the embodiments are briefly introduced below. Obviously, the drawings described below only relate to some embodiments of the present application, but are not intended to limit the present application, wherein:

[0022] Figure 1 A cross-sectional view of a chip packaging structure provided according to a first embodiment of the utility model;

[0023] Figure 2 A top view of a chip packaging structure provided according to a first embodiment of the utility model;

[0024] Figure 3 A top view of another chip packaging structure provided according to the first embodiment of the utility model;

[0025] Figure 4 is a top view of a chip packaging structure provided with a support structure according to the first embodiment of the utility model;

[0026] Figure 5 is a top view of a chip packaging structure with a through hole reserved on a substrate provided according to a second embodiment of the utility model;

[0027] Figure 6 is a cross-sectional view of a chip packaging structure with a through hole reserved on a substrate provided according to a second embodiment of the utility model;

[0028] Figure 7 It is a top view of a chip packaging structure provided with connecting wires and pads according to an embodiment of the utility model;

[0029] Figure 8 It is a top view of a chip packaging structure provided with a signal processor according to an embodiment of the utility model. DETAILED DESCRIPTION

[0030] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0031] In the drawings, the shapes and dimensions may be exaggerated for clarity, and the same reference numerals will be used throughout to designate the same or like components.

[0032] Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by persons of ordinary skill in the field to which this application belongs. The words "first", "second" and similar words used in the patent application specification and claims of this application do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "one" or "the" do not indicate a quantitative limitation, but indicate the existence of at least one. Words such as "include" or "comprise" and similar words mean that the elements or objects appearing before "include" or "comprise" include the elements or objects listed after "include" or "comprise" and their equivalents, and do not exclude other elements or objects. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0033] In the following description, words such as center, thickness, height, length, front, back, rear, left, right, top, bottom, upper, lower, etc. are defined relative to the structure shown in the drawings. In particular, "height" is equivalent to the dimension from top to bottom, "width" is equivalent to the dimension from left to right, and "depth" is equivalent to the dimension from front to back. They are relative concepts and may change accordingly according to their different positions and different usage states. Therefore, these or other directions should not be interpreted as restrictive terms.

[0034] Terms related to attachment, coupling, and the like (eg, "connected" and "attached") refer to either a fixed or attached relationship between structures, either directly or indirectly, and either movable or rigid attachments or relationships, unless expressly stated otherwise, of the structures to one another through intermediate structures.

[0035] The specific implementation of the utility model is further described in detail below in conjunction with the drawings and embodiments.

[0036] Figure 1 It is a cross-sectional view of a chip packaging structure provided according to the first embodiment of the utility model.

[0037] refer to Figure 1 A chip packaging structure of the present application includes a substrate 1 and a chip 5, wherein the chip 5 is a stress-sensitive chip. A dam structure 2 is provided on the surface 11 of the substrate 1 in the area where the chip is to be mounted, and an adhesive 8 is provided in the space enclosed by the dam structure 2. In the thickness direction of the substrate 1, the height of the adhesive 8 is greater than the height of the dam structure 2; the chip 5 is bonded to the substrate 1 through the adhesive 8.

[0038] For example, in the embodiment of the utility model, the substrate 1 is a PCB (Printed Circuit Board). The PCB is a support for electronic components (such as MEMS devices and AEIC devices), and is also a carrier for the electrical connection of electronic components. For example, a copper layout is performed on the PCB substrate to serve as a connecting wire. The substrate 1 is based on a multi-layer copper layout design to serve as a circuit board for connecting wires, for example, it may include a substrate layer, a metal layer, and a solder mask layer.

[0039] Exemplarily, in the embodiment, the chip 5 is a MEMS chip. In order to reduce the stress caused by deformation of the PCB board due to welding between the bottom surface of the substrate of the MEMS chip 5 and the PCB board, glue is applied around the bottom surface of the substrate of the MEMS chip and then fixed to the PCB board. However, since the MEMS chip is sensitive to stress, a larger amount of glue is required to fix the MEMS chip, and the softer the glue, the easier it is to collapse and cannot be accumulated to the set height, thereby failing to play a good stress isolation role.

[0040] The technical solution provided by the utility model aims to provide a dam structure on the surface of the substrate in the area where the chip is to be mounted, and to provide an adhesive in the space enclosed by the dam structure, thereby ensuring both the height of the adhesive and the consistency of the thickness of the adhesive, reducing the stress transmitted from the substrate to the chip, and improving the detection sensitivity and reliability of the chip.

[0041] refer to Figure 1 In this embodiment, a dam structure 2 is provided on the surface 11 of the substrate 1 in the area where the chip is to be mounted. The dam structure 2 is made of a hard material, and the hard material may be metal, plastic, or the like.

[0042] In some embodiments, the dam structure 2 can be integrally formed with the substrate 1. Specifically, the dam structure 2 is formed by etching or machining on the surface 11 of the chip-facing side of the substrate 1. In this formation method, the depth of the dam structure 2 from the bottom of the dam structure 2 to the surface 11 of the chip-facing side of the substrate 1 in the thickness direction of the substrate is less than the thickness of the substrate 1.

[0043] In other embodiments, the dam structure 2 and the substrate 1 may also be separate, and the dam structure 2 is attached to the surface 11 of the substrate 1 facing the chip in the area where the chip is to be mounted, and the dam structure 2 may be prefabricated by mold opening, machining, etc. as needed. The geometric shape of the dam structure 2 is polygonal or circular. For example, in this embodiment, the bottom of the dam structure 2 may be slightly higher than the surface 11 of the substrate 1 facing the chip.

[0044] refer to Figure 1In this embodiment, an adhesive 8 is provided in the accommodation space formed by the dam structure 2 and the surface of the substrate facing the chip. The adhesive 8 includes a first adhesive layer 8a stacked inside the dam structure 2 and a second adhesive layer 8b overflowing the dam structure 2. In the thickness direction of the substrate, the first adhesive layer 8a is accommodated in the dam structure 2, and the height of the first adhesive layer 8a is less than or equal to the height of the dam structure 2, and the second adhesive layer 8b is connected to the first adhesive layer 8a. The first adhesive layer 8a and the second adhesive layer 8b can use the same adhesive material, or different adhesive materials according to actual needs. The overflowing second adhesive layer 8b not only increases the thickness of the adhesive, but also prevents the chip 5 from contacting the dam structure 2 over a large area, and uses the interference adhesive to act as a bonding layer. Furthermore, the chip 5 is bonded to the substrate 1 by an adhesive 8, and the dam structure 2 is higher than the surface 11 of the substrate 1 facing the chip, thereby increasing the distance between the chip and the surface 11 of the substrate 1 facing the chip, thereby ensuring the thickness of the adhesive and reducing the stress transmitted from the substrate 1 to the chip 5.

[0045] In this embodiment, reference Figure 2 In the thickness direction of the substrate, the projection of part of the chip on the surface of the substrate facing the chip is outside the projection range of the dam structure on the surface of the substrate facing the chip. The dam structure 2 can play a supporting role when the chip 5 collapses in the adhesive 8, preventing the chip 5 from completely collapsing in the adhesive 8.

[0046] In other embodiments, reference Figure 3 In the thickness direction of the substrate, the projection of part of the dam structure on the surface of the substrate facing the chip is outside the projection range of the chip on the surface of the substrate facing the chip. In this embodiment, the surface where the chip 5 is connected to the adhesive 8 is basically covered by the adhesive 8, ensuring sufficient contact between the chip 5 and the adhesive 8. First, it prevents the chip 5 from collapsing when the bonding surface between the chip 5 and the adhesive 8 is small; second, when the bonding surface is large, the thickness of the second adhesive layer 8b that overflows the height of the dam structure 2 can be increased to reduce the stress transmitted to the chip 5.

[0047] refer to Figure 4 In this embodiment, at least one supporting structure 9 is further provided in the space enclosed by the dam structure 2, and the adhesive 8 covers the at least one supporting structure 9. The supporting structure 9 can play a supporting role when the chip 5 is bonded to the adhesive 8, preventing it from collapsing in the adhesive 8, and can prevent the chip 5 from directly contacting the dam structure 2, thereby avoiding the stress on the substrate 1 from being directly transferred to the chip 5 through the dam structure 2, and reducing the stress transferred to the chip 5.

[0048] Furthermore, in the thickness direction of the substrate, the height of the at least one supporting structure is greater than or equal to the height of the dam structure.

[0049] Figure 5 is a top view of a chip packaging structure with a through hole reserved on a substrate provided according to a second embodiment of the utility model; Figure 6 It is a cross-sectional view of a chip packaging structure with a through hole reserved on a substrate provided according to the second embodiment of the utility model.

[0050] In the second embodiment, referring to Figure 5 , Figure 6 A through hole 4 penetrating the thickness of the substrate is provided on the substrate 1, and a dam structure 2 is arranged around the through hole 4. The dam structure 2 includes a dam inner wall 2a and a dam outer wall 2b. In the thickness direction of the substrate, the height of the dam outer wall 2a is equal to the height of the dam inner wall 2b.

[0051] Furthermore, the outer wall 2a and the inner wall 2b of the dam are filled with adhesive 8, and the chip 5 is bonded to the substrate 1 through the adhesive 8. The overflowing second adhesive layer 8b is used to prevent the chip 5 from directly contacting the dam structure 2. In addition, using excess adhesive as a bonding layer increases the thickness of the adhesive, further reducing the transfer of stress.

[0052] In some embodiments, a projection of a portion of the inner wall of the dam on the surface of the substrate facing the chip is outside the projection range of the chip on the surface of the substrate facing the chip;

[0053] In other embodiments, the projection of part of the chip on the surface of the substrate facing the chip is outside the projection range of the inner wall of the dam on the surface of the substrate facing the chip. The inner wall 2b of the dam can play a supporting role when the chip 5 collapses in the adhesive, preventing the chip 5 from completely collapsing in the adhesive.

[0054] Furthermore, at least one supporting structure can be added in the space enclosed by the outer wall 2a and the inner wall 2b of the dam. The supporting structure is covered with an adhesive and can play a supporting role when the chip 5 is bonded to the adhesive to prevent it from collapsing in the adhesive. It can also prevent the chip 5 from directly contacting the outer wall 2a and the inner wall 2b of the dam, thereby avoiding the stress on the substrate 1 from being directly transferred to the chip 5 through the outer wall 2a and the inner wall 2b of the dam, thereby reducing the stress transferred to the chip 5.

[0055] Figure 7 It is a top view of a chip packaging structure provided with connecting wires and pads according to an embodiment of the utility model; Figure 8 It is a top view of a chip packaging structure provided with a signal processor according to an embodiment of the utility model.

[0056] In this embodiment, at least one signal port is included, referring to Figure 7 , the pad 7 is mounted on the substrate 1 and connected to the chip 5 through the connecting wire 6. Figure 8 A signal processor 10 is connected to the substrate. The signal processor 10 is connected to at least one chip and at least one pad 7.

[0057] Furthermore, the pad 7 is connected to the port of the chip 5 through the connection wire 6, and the signal from the chip 5 is transmitted to the substrate, so as to realize the connection and conduction of the electrical signal between the chip and the substrate. The connection wire 6 is generally a gold wire, a copper wire, or an alloy wire, and the connection wire 6 is generally connected to the pad 7 by welding.

[0058] Furthermore, the port of the signal processor 10 is connected to the pad 7 via a connecting wire, and the port of the signal processor 10 is connected to the chip 5 via a connecting wire. The signal processor 10 receives the signal from the chip 5, and after processing, transmits the processed signal to the substrate 1 via the pad 7, which is convenient for customers to use.

[0059] The embodiments of the present invention are described above, and these embodiments do not describe all the details in detail, nor do they limit the present invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modifications based on the present invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A chip packaging structure, characterized in that: The chip packaging structure comprises a substrate and a chip, and the chip is a stress-sensitive chip; A dam structure is provided in the area on the surface of the substrate where the chip is to be mounted, and an adhesive is provided in the space enclosed by the dam structure, and in the thickness direction of the substrate, the height of the adhesive is greater than the height of the dam structure; The chip is fixedly connected to the substrate via the adhesive.

2. The packaging structure according to claim 1, characterized in that: The dam structure is made of hard material.

3. The packaging structure according to claim 1, characterized in that: The dam structure is integrally formed with the substrate.

4. The packaging structure according to claim 1, characterized in that: The dam structure and the substrate are separate, and the dam structure is attached to the surface of the substrate in an area where the chip is to be mounted by attaching.

5. The packaging structure according to claim 1, characterized in that: The geometric shape of the dam structure is polygonal or circular.

6. The packaging structure according to claim 1, characterized in that: The adhesive includes a first adhesive layer and a second adhesive layer which are stacked. In the thickness direction of the substrate, the first adhesive layer is accommodated in the dam structure, and the height of the first adhesive layer is less than or equal to the height of the dam structure. The second adhesive layer is connected to the first adhesive layer.

7. The packaging structure according to claim 6, characterized in that: The first adhesive layer and the second adhesive layer are made of different adhesive materials.

8. The packaging structure according to claim 1, characterized in that: In the thickness direction of the substrate, a projection of a portion of the dam structure on a surface of the substrate facing the chip is outside a projection range of the chip on the surface of the substrate facing the chip.

9. The packaging structure according to claim 1, characterized in that: In the thickness direction of the substrate, a projection of part of the chip on a surface of the substrate facing the chip is outside a projection range of the dam structure on the surface of the substrate facing the chip.

10. The packaging structure according to claim 1, characterized in that: At least one supporting structure is also provided in the space enclosed by the dam structure, and the adhesive covers the at least one supporting structure.

11. The packaging structure according to claim 10, characterized in that: In the thickness direction of the substrate, a height of the at least one supporting structure is greater than or equal to a height of the dam structure.

12. The packaging structure according to claim 1, characterized in that: The substrate is provided with a through hole penetrating through the thickness of the substrate, and the dam structure is arranged around the through hole.

13. The packaging structure according to claim 1, characterized in that: The dam structure comprises an inner dam wall and an outer dam wall. In the thickness direction of the substrate, the height of the outer dam wall is equal to the height of the inner dam wall.

14. The packaging structure according to claim 1, characterized in that: At least one pad is provided on the substrate, and the chip is electrically connected to the corresponding pad via a connecting lead.

15. The packaging structure according to claim 1, characterized in that: A signal processor chip is arranged on the substrate, and the signal processor chip is electrically connected to the chip.

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