Two-stage architecture AFE cascade isolation circuit

Abstract

The utility model discloses an AFE cascade isolation circuit with a two-stage architecture. The circuit is connected with the MCU; comprising a first AFE chip U3, a second AFE chip U2, a power supply isolation circuit (100) and a communication isolation circuit (200). The first AFE chip U3 is connected with the MCU through the power supply isolation circuit (100); the communication isolation circuit (200) comprises a first communication isolation circuit (201) and a second communication isolation circuit (202); an SDA pin of the second AFE chip U2 is connected with an SDA pin of the first AFE chip U3 through a first communication isolation circuit (201); and the SCL pin of the second AFE chip U2 is connected with the SCL pin of the first AFE chip U3 through the second communication isolation circuit (202). According to the utility model, the power supply isolation between the AFE chips of the two-stage AFE cascade architecture and the MCU and the communication isolation between the two AFE chips can be realized.

Description

Technical Field

[0001] The utility model relates to the technical field of isolation circuits, in particular to an AFE cascade isolation circuit with a two-stage architecture. Background Art

[0002] Lithium battery packs have safety risks when their temperature, voltage, and current exceed a certain range, so a battery management system (BMS) is needed to collect and protect the voltage, current, and temperature. The AFE chip is a highly integrated analog front-end chip that can mainly collect the voltage of lithium battery pack cells, the temperature of lithium battery packs, and the total current of lithium battery packs to protect lithium battery packs; at the same time, the AFE chip can be connected to the MCU for data transmission for MCU control. Most of the AFE chips of BMS use the IIC communication interface to directly connect to the MCU and communicate with the MCU, but the direct connection of the AFE chip to the MCU has certain limitations; one of the AFE chips in the two-level architecture is a high-side AFE chip, and the other is a low-side AFE chip; the low-side AFE chip is generally connected to the protection board and draws power from the protection board; the high-side AFE chip is connected to the lithium battery pack and draws power from the lithium battery pack. The voltage output by the high-side AFE chip is high voltage for the MCU. At this time, if the high-side AFE chip is directly connected to the MCU without an isolation circuit, it may cause damage to the MCU; and the communication between the high-side AFE and the low-side AFE also needs to be connected to an isolation circuit; therefore, there are currently few lithium battery packs on the market that use the IIC communication interface to directly connect to the MCU and communicate with the MCU; a two-level AFE cascade isolation circuit is needed to meet the application scenarios with a large number of lithium battery packs. Utility Model Content

[0003] The purpose of the utility model is to provide an AFE cascade isolation circuit with a two-stage architecture. The utility model can achieve power isolation between an AFE chip and an MCU in a two-stage AFE cascade architecture and communication isolation between two AFE chips.

[0004] The technical solution of the utility model: a two-stage AFE cascade isolation circuit, the circuit is connected to the MCU; it includes a first AFE chip U3, a second AFE chip U2, a power isolation circuit and a communication isolation circuit; the first AFE chip U3 is connected to the MCU via the power isolation circuit; the communication isolation circuit includes a first communication isolation circuit and a second communication isolation circuit; the SDA pin of the second AFE chip U2 is connected to the SDA pin of the first AFE chip U3 via the first communication isolation circuit, and the first communication isolation circuit is used to achieve isolation of data signals; the SCL pin of the second AFE chip U2 is connected to the SCL pin of the first AFE chip U3 via the second communication isolation circuit, and the second communication isolation circuit is used to achieve isolation of clock signals.

[0005] The above-mentioned two-stage AFE cascade isolation circuit, the power isolation circuit includes a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7, a capacitor C1, a voltage stabilizing diode DZ1, a MOS tube Q1, a transistor Q2 and a photoelectric coupler U1; one end of the resistor R4 is connected to the MCU; the other end of the resistor R4 is connected to the positive electrode of the input photodiode of the photoelectric coupler U1; the negative electrode of the input photodiode of the photoelectric coupler U1 is grounded; the collector of the output transistor of the photoelectric coupler U1 is connected to one end of the resistor R3; the other end of the resistor R3 is connected to one end of the resistor R1 and the G pole of the MOS tube Q1; the other end of the resistor R1 is connected to the S pole of the MOS tube Q1, and the The other end is connected to the V11 pin of the first AFE chip U3; the D pole of the MOS tube Q1 is connected to one end of the resistor R2 and the collector of the transistor Q2; the other end of the resistor R2 is connected to the base of the transistor Q2 and one end of the resistor R5; the other end of the resistor R5 is grounded; the emitter of the transistor Q2 is connected to one end of the capacitor C1 and one end of the resistor R6; one end of the resistor R6 is connected to the cathode of the Zener diode DZ1 and one end of the resistor R7, and the other end of the resistor R6 is connected to the LD0_P pin of the first AFE chip U3; the emitter of the output transistor of the photocoupler U1 is connected to one end of the capacitor C1, the anode of the Zener diode DZ1 and the other end of the resistor R7, and the emitter of the output transistor of the photocoupler U1 is grounded.

[0006] The aforementioned two-stage AFE cascade isolation circuit, the first communication isolation circuit includes resistor R8, resistor R9, resistor R10, resistor R11, resistor R12, resistor R13, resistor R14, resistor R21, transistor Q3, transistor Q4, transistor Q5, transistor Q6, photocoupler U4 and photocoupler U5; one end of the resistor R12 is connected to the base of the transistor Q3, and one end of the resistor R12 is connected to the SDA pin of the first AFE chip U3; the other end of the resistor R12 is connected to one end of the resistor R9, the collector of the transistor Q5 and the positive electrode of the input photodiode of the photocoupler U4; the other end of the resistor R9 is connected to one end of the resistor R10, and the other end of the resistor R9 is connected to the VCC pin of the first AFE chip U3; the other end of the resistor R10 is connected to the collector of the output transistor of the photocoupler U5; the negative electrode of the input photodiode of the photocoupler U4 is connected to the emitter of the transistor Q3; the transistor Q3 The collector of the transistor Q5 is connected to the emitter of the transistor Q5 and one end of the resistor R21, and the collector of the transistor Q3 is grounded; the collector of the output transistor of the photocoupler U4 is connected to one end of the resistor R11; the other end of the resistor R11 is connected to one end of the resistor R8, and the other end of the resistor R11 is connected to the VCC pin of the second AFE chip U2; the other end of the resistor R8 is connected to the collector of the transistor Q4, one end of the resistor R14 and the positive electrode of the input photodiode of the photocoupler U5; the base of the transistor Q4 is connected to the emitter of the output transistor of the photocoupler U4 and one end of the resistor R13; the emitter of the transistor Q4 is connected to the other end of the resistor R13 and the collector of the transistor Q6, and the emitter of the transistor Q4 is grounded; the other end of the resistor R14 is connected to the base of the transistor Q6, and the other end of the resistor R14 is connected to the SDA pin of the second AFE chip U2; the emitter of the transistor Q6 is connected to the negative electrode of the input photodiode of the photocoupler U5.

[0007] The aforementioned two-stage AFE cascade isolation circuit, the second communication isolation circuit includes a resistor R2, a resistor R16, a resistor R17, a resistor R18, a resistor R19, a resistor R20, a transistor Q7, a transistor Q8 and a photocoupler U6; one end of the resistor R19 is connected to the SCL pin of the first AFE chip U3; the other end of the resistor R19 is connected to one end of the resistor R17 and the collector of the transistor Q7; the other end of the resistor R17 is connected to one end of the resistor R16, and the other end of the resistor R17 is connected to the VCC pin of the first AFE chip U3; the other end of the resistor R16 is connected to the collector of the output transistor of the photocoupler U6; the transistor The base of transistor Q7 is connected to the emitter of the output transistor of the photocoupler U6 and one end of the resistor R2; the emitter of the transistor Q7 is connected to the other end of the resistor R2, and the emitter of the transistor Q7 is grounded; the positive electrode of the input photodiode of the photocoupler U6 is connected to one end of the resistor R18 and one end of the address R20; the other end of the resistor R18 is connected to the VCC pin of the second AFE chip U2; the other end of the resistor R20 is connected to the base of the transistor Q8, and the other end of the resistor R20 is connected to the SCL pin of the second AFE chip U2; the emitter of the transistor Q8 is connected to the cathode of the output diode of the photocoupler U6; the collector of the transistor Q8 is grounded.

[0008] In the aforementioned two-stage AFE cascade isolation circuit, the second AFE chip U2 is a BMS low-side AFE chip.

[0009] In the aforementioned two-stage AFE cascade isolation circuit, the first AFE chip U3 is a BMS high-side AFE chip.

[0010] In the aforementioned two-stage AFE cascade isolation circuit, the resistor R6 is connected to the external interface VPRO1.

[0011] Compared with the prior art, the utility model has the following beneficial effects:

[0012] The first AFE chip U3 of the utility model is connected to the MCU via a power isolation circuit, and the high-voltage signal output by the first AFE chip U3 is reduced by the power isolation circuit before communicating with the MCU, which can protect the MCU from being damaged by the high-voltage signal; the second AFE chip U2 is connected to the first AFE chip U3 via a communication isolation circuit, and the high-voltage signal output by the first AFE chip U3 is reduced by the communication isolation circuit before communicating with the second AFE chip U2, which can protect the second AFE chip U2 from being damaged by the high-voltage signal; in addition, the first AFE chip U3 of the utility model is connected to the MCU, and when the MCU outputs a high level, the optocoupler U1 works, and at this time the MOS tube Q1 is turned on, and the V11-S pin of the first AFE chip U3 passes through the MOS tube Q1, the triode Q2, and the voltage regulator diode DZ1 to limit the voltage output by the first AFE chip U3 to about 8V, thereby realizing power isolation; the utility model can realize power isolation between the AFE chip and the MCU of the two-stage AFE cascade architecture and communication isolation between the two AFE chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a circuit diagram of the utility model;

[0014] Figure 2 is a circuit diagram of a power isolation circuit;

[0015] Figure 3 is a circuit diagram of a first communication isolation circuit;

[0016] Figure 4 is a circuit diagram of a second communication isolation circuit.

[0017] The markings in the accompanying drawings are: 100-power isolation circuit, 200-communication isolation circuit, 201-first communication isolation circuit, 202-second communication isolation circuit. DETAILED DESCRIPTION

[0018] The present invention is further described below in conjunction with the accompanying drawings and embodiments, but they are not intended to limit the present invention.

[0019] Embodiment: A two-stage AFE cascade isolation circuit, the structure is as follows Figure 1As shown, the circuit is connected to the MCU; it includes a first AFE chip U3, a second AFE chip U2, a power isolation circuit 100 and a communication isolation circuit 200; the second AFE chip U2 is a BMS low-side AFE chip. The first AFE chip U3 is a BMS high-side AFE chip. The first AFE chip U3 is connected to the MCU via a power isolation circuit; the communication isolation circuit 200 includes a first communication isolation circuit 201 and a second communication isolation circuit 202; the SDA pin of the second AFE chip U2 is connected to the SDA pin of the first AFE chip U3 via the first communication isolation circuit 201, and the first communication isolation circuit 201 is used to achieve isolation of data signals; the SCL pin of the second AFE chip U2 is connected to the SCL pin of the first AFE chip U3 via the second communication isolation circuit 202, and the second communication isolation circuit 202 is used to achieve isolation of clock signals.

[0020] The power isolation circuit 100 includes a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7, a capacitor C1, a voltage stabilizing diode DZ1, a MOS tube Q1, a transistor Q2 and a photocoupler U1; one end of the resistor R4 is connected to the MCU; the other end of the resistor R4 is connected to the positive electrode of the input photodiode of the photocoupler U1; the negative electrode of the input photodiode of the photocoupler U1 is grounded; the collector of the output transistor of the photocoupler U1 is connected to one end of the resistor R3; the other end of the resistor R3 is connected to one end of the resistor R1 and the G electrode of the MOS tube Q1; the other end of the resistor R1 is connected to the S electrode of the MOS tube Q1, and the other end of the resistor R1 is connected to the V11 pin of the first AFE chip U3. pin; the D pole of the MOS tube Q1 is connected to one end of the resistor R2 and the collector of the transistor Q2; the other end of the resistor R2 is connected to the base of the transistor Q2 and one end of the resistor R5; the other end of the resistor R5 is grounded; the emitter of the transistor Q2 is connected to one end of the capacitor C1 and one end of the resistor R6; one end of the resistor R6 is connected to the cathode of the voltage zener diode DZ1 and one end of the resistor R7, and the other end of the resistor R6 is connected to the LD0_P pin of the first AFE chip U3; the other end of the resistor R6 is connected to the external interface VPRO1; the emitter of the output transistor of the photocoupler U1 is connected to one end of the capacitor C1, the anode of the voltage zener diode DZ1 and the other end of the resistor R7, and the emitter of the output transistor of the photocoupler U1 is grounded.

[0021] The first AFE chip U3 is connected to the MCU, and the output signal of the MCU is marked as VPRO_S_EN; when VPRO_S_EN is at a high level, the optocoupler U1 works, and the MOS tube Q1 is turned on at this time. The V11-S pin of the first AFE chip U3 passes through the MOS tube Q1 and the transistor Q2, and the voltage regulator diode DZ1 limits the programming voltage VPRO-S output by the first AFE chip U3 to about 8V, thereby realizing power isolation.

[0022] The first communication isolation circuit 201 includes a resistor R8, a resistor R9, a resistor R10, a resistor R11, a resistor R12, a resistor R13, a resistor R14, a resistor R21, a transistor Q3, a transistor Q4, a transistor Q5, a transistor Q6, a photocoupler U4 and a photocoupler U5; one end of the resistor R12 is connected to the base of the transistor Q3, and one end of the resistor R12 is connected to the SDA pin of the first AFE chip U3; the other end of the resistor R12 is connected to one end of the resistor R9, the collector of the transistor Q5 and the positive electrode of the input photodiode of the photocoupler U4; the other end of the resistor R9 is connected to one end of the resistor R10, and the other end of the resistor R9 is connected to the VCC pin of the first AFE chip U3; the other end of the resistor R10 is connected to the collector of the output transistor of the photocoupler U5; the negative electrode of the input photodiode of the photocoupler U4 is connected to the emitter of the transistor Q3; the collector of the transistor Q3 is connected to the transistor The emitter of transistor Q5 and one end of resistor R21, and the collector of transistor Q3 is grounded; the collector of the output transistor of the photoelectric coupler U4 is connected to one end of resistor R11; the other end of the resistor R11 is connected to one end of resistor R8, and the other end of resistor R11 is connected to the VCC pin of the second AFE chip U2; the other end of the resistor R8 is connected to the collector of transistor Q4, one end of resistor R14 and the positive electrode of the input photodiode of the photoelectric coupler U5; the base of the transistor Q4 is connected to the emitter of the output transistor of the photoelectric coupler U4 and one end of resistor R13; the emitter of the transistor Q4 is connected to the other end of resistor R13 and the collector of the transistor Q6, and the emitter of the transistor Q4 is grounded; the other end of the resistor R14 is connected to the base of the transistor Q6, and the other end of the resistor R14 is connected to the SDA pin of the second AFE chip U2; the emitter of the transistor Q6 is connected to the negative electrode of the input photodiode of the photoelectric coupler U5.

[0023] The second communication isolation circuit 202 includes a resistor R2, a resistor R16, a resistor R17, a resistor R18, a resistor R19, a resistor R20, a transistor Q7, a transistor Q8 and a photocoupler U6; one end of the resistor R19 is connected to the SCL pin of the first AFE chip U3; the other end of the resistor R19 is connected to one end of the resistor R17 and the collector of the transistor Q7; the other end of the resistor R17 is connected to one end of the resistor R16, and the other end of the resistor R17 is connected to the VCC pin of the first AFE chip U3; the other end of the resistor R16 is connected to the collector of the output transistor of the photocoupler U6; the base of the transistor Q7 is connected to The output transistor emitter of the photocoupler U6 and one end of the resistor R2 are connected; the emitter of the transistor Q7 is connected to the other end of the resistor R2, and the emitter of the transistor Q7 is grounded; the positive electrode of the input photodiode of the photocoupler U6 is connected to one end of the resistor R18 and one end of the address R20; the other end of the resistor R18 is connected to the VCC pin of the second AFE chip U2; the other end of the resistor R20 is connected to the base of the transistor Q8, and the other end of the resistor R20 is connected to the SCL pin of the second AFE chip U2; the emitter of the transistor Q8 is connected to the cathode of the output diode of the photocoupler U6; the collector of the transistor Q8 is grounded.

[0024] The signal mark of the SDA pin of the first AFE chip U3 is SDA-HI, and the signal mark of the SCL pin of the first AFE chip U3 is SCL-HI; the signal SDA-HI and the signal SCL-HI are both high level in normal state; the model mark of the SDA pin of the second AFE chip U2 is SDA-H; the signal mark of the SCL pin of the second AFE chip U2 is SCL-H; when the signal SDA-H is high level, the transistor Q6 does not work, the photoelectric coupler U5 does not work, so that the transistor Q5 is not turned on, the transistor Q3 is not turned on, and the photoelectric coupler U5 is turned off. Coupler U4 does not work, and signal SDA-HI remains at a high level; when signal SDA-H is at a low level, transistor Q6 is turned on, photocoupler U5 works, transistor Q5 is turned on, and the level of signal SDA-HI is pulled down to a low level at the same time; when signal SCL-H is at a high level, transistor Q8 does not work, photocoupler U6 does not work, and signal SCL-HI remains at a high level; when signal SCL-H is at a low level, transistor Q8 works, photocoupler U6 works, transistor Q8 works, transistor Q7 works, and the level of signal SCL-HI is pulled down to a low level.

[0025] Working principle: The first AFE chip U3 of the utility model is connected to the MCU via the power isolation circuit 100, and the high-voltage signal output by the first AFE chip U3 is reduced by the power isolation circuit 100 before communicating with the MCU, which can protect the MCU from being damaged by the high-voltage signal; the second AFE chip U2 is connected to the first AFE chip U3 via the communication isolation circuit 200, and the high-voltage signal output by the first AFE chip U3 is reduced by the communication isolation circuit 200 before communicating with the second AFE chip U2, which can protect the second AFE chip U2 from being damaged by the high-voltage signal; in addition, the first AFE chip U3 of the utility model is connected to the MCU, and when the MCU outputs a high level, the optocoupler U1 works, at this time the MOS tube Q1 is turned on, and the V11-S pin of the first AFE chip U3 passes through the MOS tube Q1, the transistor Q2, and the voltage regulator diode DZ1 to limit the voltage output by the first AFE chip U3 to about 8V, thereby realizing power isolation; the utility model can realize the power isolation between the AFE chip and the MCU of the two-stage AFE cascade architecture and the communication isolation between the two AFE chips.

[0026] The above embodiments only express the implementation methods of the utility model, and the description is relatively specific and detailed, but it cannot be understood as limiting the scope of the utility model patent. In this embodiment, up, down, left, right, front, and back only represent their relative positions and do not represent their absolute positions. It should be pointed out that for ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of the utility model, which all belong to the protection scope of the utility model. Therefore, the protection scope of the utility model patent shall be based on the attached claims.

Claims

1. A two-stage AFE cascade isolation circuit connected to an MCU; characterized in that: The invention comprises a first AFE chip U3, a second AFE chip U2, a power isolation circuit (100) and a communication isolation circuit (200); the first AFE chip U3 is connected to an MCU via the power isolation circuit (100); the communication isolation circuit (200) comprises a first communication isolation circuit (201) and a second communication isolation circuit (202); the SDA pin of the second AFE chip U2 is connected to the SDA pin of the first AFE chip U3 via the first communication isolation circuit (201), and the first communication isolation circuit (201) is used to realize the isolation of data signals; the SCL pin of the second AFE chip U2 is connected to the SCL pin of the first AFE chip U3 via the second communication isolation circuit (202), and the second communication isolation circuit (202) is used to realize the isolation of clock signals.

2. The two-stage AFE cascade isolation circuit according to claim 1, characterized in that: The power isolation circuit (100) comprises a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7, a capacitor C1, a voltage stabilizing diode DZ1, a MOS tube Q1, a transistor Q2 and a photoelectric coupler U1; one end of the resistor R4 is connected to the MCU; the other end of the resistor R4 is connected to the positive electrode of the input photodiode of the photoelectric coupler U1; the negative electrode of the input photodiode of the photoelectric coupler U1 is grounded; the collector of the output transistor of the photoelectric coupler U1 is connected to one end of the resistor R3; the other end of the resistor R3 is connected to one end of the resistor R1 and the G electrode of the MOS tube Q1; the other end of the resistor R1 is connected to the S electrode of the MOS tube Q1, and the other end of the resistor R1 is connected to the first V11 pin of the AFE chip U3; the D pole of the MOS tube Q1 is connected to one end of the resistor R2 and the collector of the transistor Q2; the other end of the resistor R2 is connected to the base of the transistor Q2 and one end of the resistor R5; the other end of the resistor R5 is grounded; the emitter of the transistor Q2 is connected to one end of the capacitor C1 and one end of the resistor R6; one end of the resistor R6 is connected to the cathode of the Zener diode DZ1 and one end of the resistor R7, and the other end of the resistor R6 is connected to the LD0_P pin of the first AFE chip U3; the emitter of the output transistor of the photocoupler U1 is connected to one end of the capacitor C1, the anode of the Zener diode DZ1 and the other end of the resistor R7, and the emitter of the output transistor of the photocoupler U1 is grounded.

3. The two-stage AFE cascade isolation circuit according to claim 1, characterized in that: The first communication isolation circuit (201) comprises a resistor R8, a resistor R9, a resistor R10, a resistor R11, a resistor R12, a resistor R13, a resistor R14, a resistor R21, a transistor Q3, a transistor Q4, a transistor Q5, a transistor Q6, a photoelectric coupler U4 and a photoelectric coupler U5; one end of the resistor R12 is connected to the base of the transistor Q3, and one end of the resistor R12 is connected to the SDA pin of the first AFE chip U3; the other end of the resistor R12 is connected to one end of the resistor R9, the collector of the transistor Q5 and the positive electrode of the input photodiode of the photoelectric coupler U4; the other end of the resistor R9 is connected to one end of the resistor R10, and the other end of the resistor R9 is connected to the VCC pin of the first AFE chip U3; the other end of the resistor R10 is connected to the collector of the output transistor of the photoelectric coupler U5; the negative electrode of the input photodiode of the photoelectric coupler U4 is connected to the emitter of the transistor Q3; the collector of the transistor Q3 is connected to the positive electrode of the transistor Q5; the collector of the transistor Q3 is connected to the positive electrode of the transistor Q6; the collector of the transistor Q3 is connected to the positive electrode of the transistor Q7; the collector of the transistor Q7 is connected to the positive electrode of the transistor Q8; the collector of the transistor Q8 is connected to the positive electrode of the transistor Q9; the collector of the transistor Q9 is connected to the positive electrode of the transistor Q10; the collector of the transistor Q10 is connected to the positive electrode of the transistor Q2; the collector of the transistor Q3 is connected to the positive electrode of the transistor Q3; the collector of the transistor Q3 is connected to the positive electrode of the transistor Q11; the collector of the transistor Q3 is connected to the positive electrode of the transistor Q12; the collector of the transistor Q3 is connected to the positive electrode of the transistor Q13; the collector of the transistor Q3 is connected to the positive electrode The emitter of transistor Q5 and one end of resistor R21, and the collector of transistor Q3 is grounded; the collector of the output transistor of the photoelectric coupler U4 is connected to one end of resistor R11; the other end of the resistor R11 is connected to one end of resistor R8, and the other end of resistor R11 is connected to the VCC pin of the second AFE chip U2; the other end of the resistor R8 is connected to the collector of transistor Q4, one end of resistor R14 and the positive electrode of the input photodiode of the photoelectric coupler U5; the base of the transistor Q4 is connected to the emitter of the output transistor of the photoelectric coupler U4 and one end of resistor R13; the emitter of the transistor Q4 is connected to the other end of resistor R13 and the collector of the transistor Q6, and the emitter of the transistor Q4 is grounded; the other end of the resistor R14 is connected to the base of the transistor Q6, and the other end of the resistor R14 is connected to the SDA pin of the second AFE chip U2; the emitter of the transistor Q6 is connected to the negative electrode of the input photodiode of the photoelectric coupler U5.

4. The two-stage AFE cascade isolation circuit according to claim 1, characterized in that: The second communication isolation circuit (202) comprises a resistor R2, a resistor R16, a resistor R17, a resistor R18, a resistor R19, a resistor R20, a transistor Q7, a transistor Q8 and a photoelectric coupler U6; one end of the resistor R19 is connected to the SCL pin of the first AFE chip U3; the other end of the resistor R19 is connected to one end of the resistor R17 and the collector of the transistor Q7; the other end of the resistor R17 is connected to one end of the resistor R16, and the other end of the resistor R17 is connected to the VCC pin of the first AFE chip U3; the other end of the resistor R16 is connected to the collector of the output transistor of the photoelectric coupler U6; the base of the transistor Q7 The emitter of the output transistor of the photocoupler U6 is connected to one end of the resistor R2; the emitter of the transistor Q7 is connected to the other end of the resistor R2, and the emitter of the transistor Q7 is grounded; the positive electrode of the input photodiode of the photocoupler U6 is connected to one end of the resistor R18 and one end of the address R20; the other end of the resistor R18 is connected to the VCC pin of the second AFE chip U2; the other end of the resistor R20 is connected to the base of the transistor Q8, and the other end of the resistor R20 is connected to the SCL pin of the second AFE chip U2; the emitter of the transistor Q8 is connected to the cathode of the output diode of the photocoupler U6; the collector of the transistor Q8 is grounded.

5. The two-stage AFE cascade isolation circuit according to claim 1, characterized in that: The second AFE chip U2 is a BMS low-side AFE chip.

6. The two-stage AFE cascade isolation circuit according to claim 1, characterized in that: The first AFE chip U3 is a BMS high-side AFE chip.

7. The two-stage AFE cascade isolation circuit according to claim 2, characterized in that: The resistor R6 is connected to the external interface VPRO1.

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