Electric energy quality monitoring terminal

Abstract

The utility model discloses an electric energy quality monitoring terminal, which comprises a power supply module, a data acquisition unit and a data processing unit, the data acquisition unit is used for acquiring voltage and current signals of a monitored object and transmitting the voltage and current signals to the data processing unit; and the power supply module is used for supplying power. According to the utility model, a mainstream voltage transformer is replaced by the cylindrical thin-film resistor, and the electrical reliability is ensured by using an electrical isolation technology while the PCB is compactly designed. Meanwhile, in order to guarantee the power quality monitoring and measuring performance, a dual-core construction design is adopted, and the main method for improving the precision is that three-phase voltage is selectively input into a band-pass filter through a multi-way switch; an input signal passes through a 0-2M low-pass filter and is sampled through an FPGA, and data is collected and finally enters a DSP for processing through a DDR data cache, so that electric energy quality monitoring is realized.

Description

Technical Field

[0001] The utility model relates to a power quality monitoring terminal, belonging to the field of distribution network power system operation and analysis. Background Art

[0002] In order to effectively evaluate the power quality problems of the power grid and solve the problem of excessive power quality, a large number of power quality monitoring devices need to be deployed. Ideally, all power quality indicators of the entire network should be satisfactory. However, the large size and high cost of existing power quality monitoring devices hinder the realization of this goal and delay the development and application of power quality. Therefore, it is necessary to provide a new type of power quality monitoring device, and the design of a power quality monitoring device needs to consider its composition and connection. Summary of the invention

[0003] The utility model provides a power quality monitoring terminal, which constructs a circuit structure for power quality monitoring through reasonable composition and connection.

[0004] The technical solution of the utility model is: a power quality monitoring terminal, including a power module, a data acquisition unit, and a data processing unit; the data acquisition unit is used to collect voltage and current signals of the monitored object and transmit them to the data processing unit; the power module is used to supply power.

[0005] The data acquisition unit includes a voltage transformer, a current transformer, a differential circuit, an A\D module, a low-pass filter, an FPGA, and a storage system; the voltage and current signals of the monitored object are transformed by the voltage transformer and the current transformer, processed by the differential circuit, and the analog signals are converted into digital signals by the A\D module, and then passed through the low-pass filter, and the signals are sampled by the FPGA and stored in the storage system.

[0006] The voltage transformer adopts a cylindrical resistor.

[0007] The low-pass filter adopts a 0-2 MHz low-pass filter.

[0008] The data processing unit adopts a dual-core CPU architecture, including a first CPU and a second CPU; wherein the first CPU is connected to the second CPU and the data acquisition unit respectively.

[0009] The power module is designed with two groups of capacitor energy storage circuits, and each group of capacitor energy storage circuits uses a plurality of Farad capacitors connected in series.

[0010] The beneficial effects of the utility model are as follows: the utility model has a circuit structure for power quality monitoring through an ingenious structural design, which can be effectively used for power quality monitoring. In addition, the structure replaces the mainstream voltage transformer with a cylindrical thin film resistor, and uses electrical isolation technology to ensure its electrical reliability while compactly designing the PCB. At the same time, in order to ensure the power quality monitoring and measurement performance, a dual-core construction design is adopted, and the main method to improve the accuracy is to select the input bandpass filter of the three-phase voltage through a multi-way switch; the input signal passes through a 0-2M low-pass filter, and the signal is sampled through the FPGA. The collected data finally enters the DSP for processing through the DDR data cache. Furthermore, after evaluation, the power quality monitoring terminal designed by the utility model is small in size and low in cost, and can effectively support the large-scale deployment and use of power quality monitoring in the entire network. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a framework diagram of the utility model;

[0012] Figure 2 It is a data collection diagram of the utility model;

[0013] Figure 3 It is the principle diagram of FPGA of the utility model;

[0014] Figure 4 It is a structural diagram of the storage system of the utility model;

[0015] Figure 5 This is a structural diagram of the capacitor energy storage circuit of the utility model;

[0016] Figure 6 This is the Ethernet electrical port transformer isolation structure diagram. DETAILED DESCRIPTION

[0017] Example 1: Figure 1-6 As shown, a power quality monitoring terminal includes a power module, a data acquisition unit, and a data processing unit; the data acquisition unit is used to collect voltage and current signals of the monitored object and transmit them to the data processing unit; the power module is used to supply power;

[0018] Furthermore, the data acquisition unit includes a voltage transformer, a current transformer, a differential circuit, an A\D module, a low-pass filter, an FPGA, and a storage system; the voltage and current signals of the monitored object are transformed by the voltage transformer and the current transformer, processed by the differential circuit, and the analog signals are converted into digital signals by the A\D module, and then passed through the low-pass filter, and the signals are sampled by the FPGA and stored in the storage system.

[0019] Furthermore, the voltage transformer adopts a cylindrical resistor, such as CSR0204FTDV4990.

[0020] Furthermore, the low-pass filter adopts a 0-2 MHz low-pass filter.

[0021] Furthermore, the data processing unit adopts a dual-core CPU architecture, including a first CPU and a second CPU; wherein the first CPU is respectively connected to the second CPU and the data acquisition unit.

[0022] Furthermore, the optional specific implementation modes of the present invention are described as follows:

[0023] The power quality monitoring terminal includes a power module, a voltage transformer, a current transformer, a differential circuit, an A\D module, a 0~2MHz low-pass filter, an FPGA, a storage system, a DSP as the first CPU, and an ARM as the second CPU; the power circuit converts the 85V~264V voltage into a 5V voltage signal, which is connected to the differential circuit to provide power for the power quality monitoring terminal; and the voltage and current signals of the monitored object are transformed by the voltage transformer and the current transformer, processed by the differential circuit, and converted into digital signals by the A\D (digital\analog chip), and then retained by the low-pass filter 0~2M Hz signal, and then the FPGA samples the signal, and then stores it in the storage system, and then the signal sampling is transmitted to the DSP for Fourier transformation, and the power quality index calculation is carried out to realize the power quality function. At the same time, the ARM module is used to connect the timing receiving module, the wireless communication module, the Ethernet module, the display module, and the RS485 module, and the ARM is responsible for timing, communication (wireless module, Ethernet module), liquid crystal display, RS485 and other processing.

[0024] The data processing module mentioned above adopts a dual-core CPU architecture, integrating a Cortex-A8 ARM core and a C674x DSP core, supporting DDR3 interface, 8 UART ports, 1 Ethernet 10 / 100 / 1000MMII / RMII / RGMIIEMAC interface, 1 4G interface, MMC / SD storage interface, etc. The ARM core is responsible for the human-machine interface, Ethernet communication, RS485 communication, time synchronization, internal large-capacity storage and other functions, and the DSP core is responsible for AC signal acquisition, algorithm processing, switch input and output and other functions. With the dual-core CPU architecture, the data interaction between the ARM core and the DSP core is realized inside the chip, and the hardware design complexity is reduced through the host access interface and dual-port RAM implementation, and the reliability is higher.

[0025] In order to achieve high-precision sampling of the power quality monitoring terminal, especially to ensure the accuracy of voltage transient recording. The AC signal acquisition module architecture of the power quality monitoring terminal is as follows: Figure 2As shown, the three-phase voltage is selected by a multi-way switch to input the bandpass filter; the input signal passes through a 0-2MHz low-pass filter, and the signal is sampled by the FPGA. The collected data finally enters the DSP for processing through the DDR data cache. The FPGA module architecture is as follows Figure 3 The specific implementation steps are as follows:

[0026] Step 1: Capture accurate time and output second pulse signal

[0027] Through the clock module task, FPGA uses the query method every second to obtain the status of the 1ms time pin input for the IRIG-B signal, performs IRIG-B decoding, and calculates the year, month, day, hour, minute, and second; controls GPIO to output a high-level PPS-GATE signal within 10ms before the IRIG-B second pulse signal; inputs PPS-GATE and IRIG-B into the AND gate to obtain a second pulse signal PPS with a theoretical error of nanoseconds, which can be used for output.

[0028] Step 2: Calibrate the crystal oscillator

[0029] The terminal uses a 1ppm crystal oscillator, that is, the deviation in the absolute time 1s is 1us. The timer driven directly by this crystal oscillator cannot meet the accuracy requirements, so the crystal oscillator needs to be calibrated. The precise second pulse signal PPS in step one triggers an interrupt, and the time modulation module inside the FPGA records the count of the timer every second. Calculate the timer count difference (number of clock pulses) between two adjacent second pulses; through multiple measurements and optimization (sliding window calculation), obtain the number of pulses N of the absolute time 1s timer in the current environment as the 1s benchmark inside the device to achieve calibration.

[0030] Step 3: Drive AD sampling

[0031] Through step 2, the speed of 2M sampling per 1s in the current environment is obtained, and accurate 2M high-speed time sampling is achieved through SPI configuration AD; the sampling data is differenced by channel to compensate for the angle difference, or multiplied by the compensation vector in vector calculation to ensure high accuracy.

[0032] Step 4: Add a time stamp to the sampling data window

[0033] The sampling data is read through EDMA, and the count of the current timer is recorded and converted into a time stamp; the data of the whole second is selected as the starting position, each half wave forms a data window, and the time stamp is added and provided to the operation module.

[0034] The storage system includes serial NorFlash, DDR3, eMMC, and ferroelectric FRAM. When the power quality monitoring terminal is started, the dual-core CPU reads the device program from the serial NorFlash. DDR3 provides space for program operation when the power quality terminal is operating normally. The eMMC stores the waveform records and other power quality data generated by the power quality terminal. The ferroelectric FRAM stores important configuration parameters and operating parameters. Through the combination of multiple storage media, data is stored independently according to function and data importance. The storage system is as follows: Figure 4 As shown, the dual-core CPU has an SPI interface, a DDR3 controller, and an MMC interface. The CPU exchanges data with the serial NorFlash through the SPI interface, exchanges data with the DDR3 through the DDR3 controller, exchanges data with the eMMC through the MMC interface, and exchanges data with the ferroelectric FRAM through the SPI interface.

[0035] In order to realize the miniaturization of the power quality monitoring terminal, improve the degree, reduce the volume, reduce the cost, and compactly design the PCB board, improvements and optimizations are made in the following aspects:

[0036] (1) The power supply adopts a Farad capacitor energy storage circuit design, using seven 7F, 2.7V capacitors in series to design two sets of capacitor energy storage circuits. The structure is as follows Figure 5 shown.

[0037] (2) Cylindrical resistors are used to replace conventional voltage transformers for traditional voltage measurement.

[0038] Traditional transformers are relatively large, with a single transformer diameter of 32mm and a height of 27mm. They are replaced with high-precision cylindrical thin-film resistors, with a single cylindrical resistor size of 5.9mm long and 2.2mm in diameter. After the power quality monitoring terminal adopts cylindrical resistors, the height of the device is greatly reduced, greatly reducing the space occupied by the voltage measurement circuit.

[0039] (3) Electrical isolation

[0040] To ensure stable operation of the compactly designed power quality monitoring terminal, transformer isolation is used for 85V~264V AC / DC power input; optocoupler isolation is used for RS-485 communication circuit signal part, and isolated DC / DC is used for power supply part; electromagnetic isolation is used for current measurement loop; transformer isolation is used for Ethernet electrical port. Figure 6 shown.

[0041] By applying the above technical solutions, the volume of the power quality monitoring terminal can be strictly controlled within 14.5cm×7.6cm×11.6cm; in particular, high-reliability cylindrical resistors are used instead of traditional voltage transformers for voltage measurement, which reduces the voltage loop acquisition loop cost by more than 20% while reducing the volume. The use of industrial-grade mass-produced miniaturized power modules and communication modules can further reduce the overall cost by more than 60% while ensuring reliability.

[0042] The specific implementation modes of the present invention are described in detail above in conjunction with the accompanying drawings, but the present invention is not limited to the above implementation modes, and various changes can be made within the knowledge scope of ordinary technicians in this field without departing from the purpose of the present invention.

Claims

1. A power quality monitoring terminal, characterized in that: It includes a power supply module, a data acquisition unit, and a data processing unit; the data acquisition unit is used to collect voltage and current signals of the monitored object and transmit them to the data processing unit; the power supply module is used to supply power; The data acquisition unit includes a voltage transformer, a current transformer, a differential circuit, an A\D module, a low-pass filter, an FPGA, and a storage system; the voltage and current signals of the monitored object are transformed by the voltage transformer and the current transformer, processed by the differential circuit, and converted into digital signals by the A\D module, and then passed through the low-pass filter, and the signals are sampled by the FPGA and stored in the storage system; The voltage transformer adopts a cylindrical resistor.

2. The power quality monitoring terminal according to claim 1, characterized in that: The low-pass filter adopts a 0~2MHz low-pass filter.

3. The power quality monitoring terminal according to claim 1, characterized in that: The data processing unit adopts a dual-core CPU architecture, including a first CPU and a second CPU; wherein the first CPU is connected to the second CPU and the data acquisition unit respectively.

4. The power quality monitoring terminal according to claim 1, characterized in that: The power module is designed with two groups of capacitor energy storage circuits, and each group of capacitor energy storage circuits uses a plurality of Farad capacitors connected in series.

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