Double-CPU circuit suitable for doubled 2-vote-2 architecture

Abstract

The utility model provides a double CPU circuit suitable for a 2 * 2-vote-2 architecture, and relates to the technical field of network communication, the double CPU circuit comprises two CPUs, and different sub-circuits and comparison circuits corresponding to the CPUs, the different sub-circuits comprise a temperature detection sub-circuit, an external voltage reference sub-circuit, a watchdog sub-circuit, a storage sub-circuit and a voltage monitoring sub-circuit; the CPUs are respectively connected with the corresponding temperature detection sub-circuit, the external voltage reference sub-circuit, the watchdog sub-circuit, the storage sub-circuit and the voltage monitoring sub-circuit, and the watchdog sub-circuit is connected with the two CPUs; the comparison circuit comprises two serial port sub-circuits, two PWM wave transmit-receive sub-circuits and four GPIO sub-circuits, and the two serial port sub-circuits, the two PWM wave transmit-receive sub-circuits and the four GPIO sub-circuits are all connected with the two CPUs. The circuit structure can realize the function of system board card core business logic processing, and meets the 2 * 2-vote-2 architecture requirement of the system.

Description

Technical Field

[0001] The utility model relates to the technical field of network communication, in particular to a dual CPU circuit suitable for a 2-by-2-by-2 architecture. Background Art

[0002] With the development of railway transportation, the demand for driving safety is increasing, and the requirements for driving safety equipment are improving. As a train control device that controls train operation and ensures railway driving safety, safety computers are gradually becoming the core of train control equipment in recent years. Safety computers are mainly divided into two architectures: 3 out of 2 and 2x2 out of 2. Since 2x2 out of 2 safety computers are easy to maintain, can be tested offline, and their safety performance is several times that of 3 out of 2 systems, 2x2 out of 2 safety computers have been increasingly widely used in train control equipment that emphasizes safety first. The 2x2 out of 2 architecture consists of four computers (CPUs) forming two subsystems, one of which is used as the host to output control instructions, and the other is hot standby. The two computers in the subsystem each execute a set of programs with the same code, and then compare the calculation results. If they are consistent, they drive the output; if they are inconsistent, it is considered that a computer is faulty and immediately switches to another subsystem for output. The existing circuit does not meet the core business logic processing requirements in the 2x2 out of 2 architecture. Therefore, it is very necessary to design a dual CPU circuit suitable for the 2x2 out of 2 architecture. Utility Model Content

[0003] The purpose of the utility model is to provide a dual CPU circuit suitable for a 2x2 take 2 architecture. The circuit structure of the utility model can realize the function of core business logic processing of the system board, and meet the 2x2 take 2 architecture requirements of the system.

[0004] To achieve the above purpose, the utility model provides the following solutions:

[0005] A dual CPU circuit suitable for a 2-by-2-take-2 architecture, comprising: a first CPU and a second CPU, and further comprising: a first CPU peripheral circuit, a second CPU peripheral circuit and a comparison circuit;

[0006] The first CPU peripheral circuit includes: a first temperature detection subcircuit, a first external voltage reference subcircuit, a first watchdog subcircuit, a first storage subcircuit and a first voltage monitoring subcircuit; the first CPU is respectively connected to the first temperature detection subcircuit, the first external voltage reference subcircuit, the first watchdog subcircuit, the first storage subcircuit and the first voltage monitoring subcircuit, and the first watchdog subcircuit is connected to the second CPU;

[0007] The second CPU peripheral circuit includes: a second temperature detection subcircuit, a second external voltage reference subcircuit, a second watchdog subcircuit, a second storage subcircuit and a second voltage monitoring subcircuit; the second CPU is respectively connected to the second temperature detection subcircuit, the second external voltage reference subcircuit, the second watchdog subcircuit, the second storage subcircuit and the second voltage monitoring subcircuit, and the second watchdog subcircuit is connected to the first CPU;

[0008] The comparison circuit includes: 2 serial port sub-circuits, 2 PWM wave transceiver sub-circuits and 4 GPIO sub-circuits, and the 2 serial port sub-circuits, 2 PWM wave transceiver sub-circuits and 4 GPIO sub-circuits are connected to the first CPU and the CPU respectively.

[0009] Optionally, the first temperature detection subcircuit has a built-in first temperature monitoring chip, and the first temperature monitoring chip is an M117B chip.

[0010] Optionally, both the first watchdog sub-circuit and the second watchdog sub-circuit are equipped with a built-in watchdog circuit chip, and the watchdog circuit chip is a TPL5010DDCR chip; the TPL5010DDCR chip is used to reset the first CPU and the second CPU simultaneously.

[0011] Optionally, the first storage sub-circuit has a first FLASH storage chip built in, and the first FLASH storage chip is a W25Q128JVSIM chip.

[0012] Optionally, the second temperature detection subcircuit is built with a second temperature monitoring chip, and the second temperature monitoring chip is a TMP101NA / 3K chip.

[0013] Optionally, the second storage sub-circuit is equipped with a second FLASH storage chip, and the second FLASH storage chip is a GD25Q128CSIG chip.

[0014] Optionally, the serial port sub-circuit is used to send and receive status information and data information of the first CPU and the second CPU, the PWM wave transceiver sub-circuit is used to provide an information transmission path, the information transmission path is used to enable the first CPU and the second CPU to confirm clock frequency information with each other, and the GPIO sub-circuit is used to transmit lock-step signals and restart signals during the execution of the programs of the first CPU and the second CPU.

[0015] According to the specific embodiments provided by the utility model, the utility model discloses the following technical effects: a dual CPU circuit suitable for a 2-by-2-take-2 architecture, comprising: a first CPU and a second CPU, and also comprising: a first CPU peripheral circuit, a second CPU peripheral circuit and a comparison circuit; the first CPU peripheral circuit comprises: a first temperature detection subcircuit, a first external voltage reference subcircuit, a first watchdog subcircuit, a first storage subcircuit and a first voltage monitoring subcircuit; the first CPU is respectively connected to the first temperature detection subcircuit, the first external voltage reference subcircuit, the first watchdog subcircuit, the first storage subcircuit and the first voltage monitoring subcircuit, and the first watchdog subcircuit is connected to the first The second CPU is connected; the second CPU peripheral circuit includes: a second temperature detection subcircuit, a second external voltage reference subcircuit, a second watchdog subcircuit, a second storage subcircuit and a second voltage monitoring subcircuit; the second CPU is respectively connected to the second temperature detection subcircuit, the second external voltage reference subcircuit, the second watchdog subcircuit, the second storage subcircuit and the second voltage monitoring subcircuit, and the second watchdog subcircuit is connected to the first CPU; the comparison circuit includes: a 2-way serial port subcircuit, a 2-way PWM wave transceiver subcircuit and a 4-way GPIO subcircuit, and the 2-way serial port subcircuit, the 2-way PWM wave transceiver subcircuit and the 4-way GPIO subcircuit are respectively connected to the first CPU and the CPU. The circuit structure of the utility model can realize the function of the core business logic processing of the system board, meet the system's 2x2 take 2 architecture requirements, and has low cost and simple structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the utility model or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0017] Figure 1 This is a circuit structure block diagram of an embodiment of the utility model;

[0018] Figure 2 A circuit schematic diagram of a first CPU peripheral circuit of an embodiment of the utility model; Figure 2 Part (a) is a circuit schematic diagram of the first temperature detection sub-circuit of an embodiment of the utility model; Figure 2 Part (b) is a circuit schematic diagram of a first external voltage reference sub-circuit according to an embodiment of the present utility model; Figure 2 Part (c) is a schematic diagram of a first watchdog sub-circuit according to an embodiment of the present utility model; Figure 2 Part (d) is a circuit diagram of the first storage sub-circuit of an embodiment of the utility model; Figure 2Part (e) is a circuit schematic diagram of the first voltage monitoring sub-circuit of an embodiment of the utility model;

[0019] Figure 3 A schematic diagram of a second CPU peripheral circuit of an embodiment of the utility model; Figure 3 Part (a) is a circuit schematic diagram of a second temperature detection sub-circuit of an embodiment of the utility model; Figure 3 Part (b) is a circuit schematic diagram of a second external voltage reference sub-circuit according to an embodiment of the present utility model; Figure 3 Part (c) is a schematic diagram of a second watchdog sub-circuit according to an embodiment of the present utility model; Figure 3 Part (d) is a circuit diagram of the second storage sub-circuit of an embodiment of the utility model; Figure 3 Part (e) is a circuit schematic diagram of a second voltage monitoring sub-circuit according to an embodiment of the present utility model;

[0020] Figure 4 This is a schematic diagram of a comparative circuit according to an embodiment of the present utility model.

[0021] Figure numerals: 1. first CPU; 2. first temperature detection sub-circuit; 3. first external voltage reference sub-circuit; 4. first watchdog sub-circuit; 5. first storage sub-circuit; 6. first voltage monitoring sub-circuit; 7. second CPU; 8. second temperature detection sub-circuit; 9. second external voltage reference sub-circuit; 10. second watchdog sub-circuit; 11. second storage sub-circuit; 12. second voltage monitoring sub-circuit. DETAILED DESCRIPTION

[0022] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0023] The purpose of the utility model is to provide a dual CPU circuit suitable for a 2x2 take 2 architecture, which circuit structure can realize the function of core business logic processing of the system board, meet the system's 2x2 take 2 architecture requirements, and has low cost and simple structure.

[0024] In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0025] like Figure 1As shown, the utility model provides a dual CPU circuit suitable for a 2-by-2-by-2 architecture, including: a first CPU 1 and a second CPU 7, and also including: a first CPU 1 peripheral circuit, a second CPU 7 peripheral circuit and a comparison circuit.

[0026] Specifically, the first CPU1 and the second CPU7 both use an ARM microcontroller model TMS5704357BZWTQQ1, which has a 16 / 32-bit secure Arm Cortex-R5F security core and SIL3-level hardware security certification, has passed Q-100 automotive certification, and has a 4MB program flash memory that supports ECC function, a 512KB RAM that supports ECC function, and a 128KB EERPOM data flash memory that supports ECC function for simulation. According to the microcontroller technical manual, an external 16MHz active crystal oscillator is set to provide a high-speed external clock input for the microcontroller.

[0027] like Figure 2 As shown, the peripheral circuit of the first CPU 1 includes: a first temperature detection subcircuit 2, a first external voltage reference subcircuit 3, a first watchdog subcircuit 4, a first storage subcircuit 5 and a first voltage monitoring subcircuit 6; the first CPU 1 is respectively connected to the first temperature detection subcircuit 2, the first external voltage reference subcircuit 3, the first watchdog subcircuit 4, the first storage subcircuit 5 and the first voltage monitoring subcircuit 6, and the first watchdog subcircuit 4 is connected to the second CPU 7;

[0028] like Figure 2 As shown in part (a), the first temperature detection subcircuit 2 is composed of a first temperature monitoring chip U1, a resistor and a capacitor, and the U1 chip is an M117B chip. Among them, the 5th pin of the M117B chip is connected to the 3.3V input voltage of the first CPU1, the 2nd pin is connected to the ground electrode of the first CPU1, the capacitor C1 is connected between the 2nd pin and the 5th pin, and the capacitor C1 is used to provide a decoupling function for the input power supply of the M117B chip. The capacitance of the capacitor C1 is 100nF, and the withstand voltage value is 50V. The 1st pin, the 6th pin and the 3rd pin are respectively connected to the 3.3V input voltage of the first CPU1 through the resistor R14, the resistor R15 and the resistor R16. The resistance values ​​of the resistors R14 to R16 are all 10K ohms. The resistors R14 to R16 are all used as pull-up resistors to ensure the stability of the communication level of the first CPU1, and the 4th pin is an empty pin. The operating temperature of the M117B chip is -55°C to 125°C, which satisfies the operating temperature range of the first CPU 1 of -40°C to 125°C.

[0029] like Figure 2As shown in part (b), the first external voltage reference subcircuit 3 is composed of a transistor U2, a capacitor and a resistor. The model of the transistor U2 is AZ432ANTR-G1. The first external voltage reference subcircuit 3 is used to provide an independent stable reference voltage of 1.25V for the first CPU1. Pin 2 of the transistor U2 is connected to the 3.3V input voltage of the first CPU1 through a resistor R13. The resistance value of the resistor R13 is 1K ohm. The resistor R13 is a current limiting resistor output by the transistor. Pin 3 is connected to the ground electrode of the first CPU1, pin 1 is connected to pin 2, and capacitor C2 is connected to pins 2 and 3. Capacitor C2 is used to filter the output power supply of the U2 chip. The capacitance of capacitor C2 is 100nF and the withstand voltage value is 50V.

[0030] like Figure 2 As shown in part (c), the first watchdog subcircuit 4 is composed of a watchdog circuit chip U3, a resistor, a capacitor and a switch. The U3 chip adopts a TPL5010DDCR chip; the TPL5010DDCR chip is used to reset the first CPU1 and the second CPU7 simultaneously. Among them, the pin 1 of the TPL5010DDCR chip is connected to the 3.3V input voltage of the first CPU1 and the capacitor C3, the pin 4 is connected to the M3 pin of the first CPU1, the pin 5 is connected to the H3 pin of the first CPU1, the capacitor C3 is connected to the grounding electrode of the first CPU1, and the capacitor C3 is used to provide a decoupling function for the input power supply of the U3 chip. The capacitance of the capacitor C3 is 100nF and the withstand voltage is 50V. The pin 2 is connected to the grounding electrode of the first CPU1, and the pin 3 is connected to the grounding electrode of the first CPU1 through the resistor R17. The resistance value of the resistor R17 is 2. 5K ohms, with an accuracy of 1%. The reset time of the TPL5010DDCR chip is adjusted by adjusting the resistance value of resistor R17, and the time range is 100ms to 7200s. Pin 6 is connected to the normally closed patch switch S1, which is connected to the first CPU1 and to the second CPU7 through resistor R12. The model of the normally closed patch switch S1 is DSHP01TSGER. The patch switch S1 is used for manual burning of the board chip. The resistance value of resistor R12 is 10 ohms. Resistor R12 is used to eliminate the influence of the level difference between the two CPUs.

[0031] like Figure 2As shown in part (d), the first storage subcircuit 5 is composed of a first FLASH storage chip U4 and a resistor. The U4 chip adopts a W25Q128JVSIM chip. The pins 1, 2, 3, 5, 6 and 7 of the W25Q128JVSIM chip are connected to the 3.3V input voltage of the first CPU1 through resistors R25, R21, R26, R20, R22 and R27 respectively. The pin 8 of the W25Q128JVSIM chip is connected to the 3.3V input voltage of the first CPU1 and the resistor R25, R21, R26, R20, R22 and R27 respectively. Capacitor C4 is connected, capacitor C4 is connected to the ground electrode of the first CPU1, capacitor C4 is used to provide decoupling function for the input power supply of U3 chip, the capacitance of capacitor C4 is 100nF, the withstand voltage value is 50V, the resistance values ​​of resistors R20, R21, R22, R25, R26 and R27 are all 10K ohms, resistors R20, R21, R22 and R25 are used as pull-up resistors to ensure the stability of the communication level of the first CPU1, resistors R26 and R27 are function configuration resistors of U4 chip.

[0032] The core operating voltage of the first CPU1 is 1.14V to 1.32V, the I / O power supply voltage of the first CPU1 is 3.0V to 3.6V, and the voltage fluctuation range is within ±5%. The first CPU1 can work normally. The embodiment of the utility model uses 1.2V and 3.3V power supply voltages to power the first CPU1. Figure 2 As shown in (e), the first voltage monitoring subcircuit 6 is composed of a plurality of resistors. Resistor R18 is connected to the 3.3V input voltage of the first CPU1 and resistor R23 respectively. The connection end of resistor R18 and resistor R23 is connected to the external monitoring module. Resistor R23 is connected to the grounding electrode of the first CPU1. The resistance value of resistor R18 is 10K ohms with an accuracy of 1%. The resistance value of resistor R23 is 3K with an accuracy of 1%. Resistor R19 is connected to the 1.2V input voltage of the first CPU1 and resistor R24 ​​respectively. The connection end of resistor R19 and resistor R24 ​​is connected to the external monitoring module. Resistor R24 ​​is connected to the grounding electrode of the first CPU1. The resistance values ​​of resistor R19 and resistor R24 ​​are both 10K ohms with an accuracy of 1%. Resistor R18 and resistor R23 are used to divide the 3.3V input voltage. Resistor R19 and resistor R24 ​​are used to divide the 1.2V input voltage.

[0033] like Figure 3 As shown, the peripheral circuit of the second CPU7 includes: a second temperature detection sub-circuit 8, a second external voltage reference sub-circuit 9, a second watchdog sub-circuit 10, a second storage sub-circuit 11 and a second voltage monitoring sub-circuit 12; the second CPU7 is respectively connected to the second temperature detection sub-circuit 8, the second external voltage reference sub-circuit 9, the second watchdog sub-circuit 10, the second storage sub-circuit 11 and the second voltage monitoring sub-circuit 12, and the second watchdog sub-circuit 10 is connected to the first CPU1.

[0034] like Figure 3 As shown in part (a), the second temperature detection subcircuit 8 is composed of a second temperature monitoring chip U5, a resistor and a capacitor. The U5 chip is a TMP101NA / 3K chip. Among them, pin 4 of the TMP101NA / 3K chip is connected to the 3.3V input voltage of the second CPU7, pin 2 is connected to the ground electrode of the second CPU7, capacitor C5 is connected between pins 2 and 4, capacitor C5 is used to provide decoupling function for the input power supply of the TMP101NA / 3K chip, the capacitance of capacitor C5 is 100nF, and the withstand voltage value is 50V, pin 1, pin 6 and pin 3 are respectively connected to the 3.3V input voltage of the second CPU7 through resistors R29, resistor R30 and resistor R31, the resistance values ​​of resistors R29~R31 are all 10K ohms, and resistors R29~R31 are all used as pull-up resistors to ensure the stability of the communication level of the second CPU7, pin 5 is connected to the ground electrode of the second CPU7 through resistor R33, and the resistance value of resistor R33 is 10K ohms. The operating temperature of the TMP101NA / 3K chip is -55°C to 125°C, which satisfies the operating temperature range of the second CPU 7 of -40°C to 125°C.

[0035] like Figure 3 As shown in part (b), the second external voltage reference subcircuit 9 is composed of a transistor U6, a capacitor and a resistor. The model of the transistor U6 is SE432L-HF. The second external voltage reference subcircuit 9 is used to provide an independent stable reference voltage of 1.25V for the second CPU 7. Pin 2 of the transistor U6 is connected to the 3.3V input voltage of the second CPU 7 through a resistor R28. The resistance value of the resistor R28 is 1K ohm. The resistor R28 is a current limiting resistor output by the transistor. Pin 3 is connected to the ground electrode of the second CPU 7. Pin 1 is connected to pin 2 through a resistor R32. The resistance value of the resistor R32 is 0 ohm. The resistor R32 is a configuration resistor of the transistor U6, which cannot be omitted. The capacitor C6 is connected to pins 2 and 3. The capacitor C6 is used to filter the output power supply of the SE432L-HF. The capacitance of the capacitor C6 is 100nF and the withstand voltage value is 50V.

[0036] like Figure 3As shown in part (c), the second watchdog sub-circuit 10 is composed of a watchdog circuit chip U7, a resistor, a capacitor and a switch. The U7 chip adopts a TPL5010DDCR chip, and the TPL5010DDCR chip is used to reset the first CPU1 and the second CPU7 simultaneously; the pin 1 of the TPL5010DDCR chip is connected to the 3.3V input voltage of the second CPU7 and the capacitor C7, the capacitor C7 is connected to the ground electrode of the second CPU7, the capacitance of the capacitor C7 is 100nF, and the withstand voltage value is 50V, the pin 2 is connected to the ground electrode of the second CPU7, and the pin 3 is connected to the ground electrode of the first CPU1 through the resistor R17. The ground electrode is connected, the resistance of resistor R17 is 2.5K ohms, and the accuracy is 1%. The reset time of the TPL5010DDCR chip is adjusted by adjusting the resistance of resistor R34, and the time range is 100ms~7200s. Pin 6 is connected to the normally closed patch switch S2, the patch switch S2 is connected to the second CPU7, and is connected to the first CPU1 through the resistor R11. The model of the normally closed patch switch S2 is DSHP01TSGER. The patch switch S2 is used for manual burning of the board chip. The resistance of resistor R11 is 10 ohms. Resistor R11 is used to eliminate the influence of the level difference between the two CPUs.

[0037] like Figure 3 As shown in part (d), the second storage subcircuit 11 is composed of a second FLASH storage chip U8 and a resistor. The U8 chip adopts a GD25Q128CSIG chip. The 1st, 2nd, 3rd, 5th, 6th and 7th pins of the GD25Q128CSIG chip are connected to the 3.3V input voltage of the second CPU 7 through resistors R42, R40, R43, R39, R41 and R44 respectively. The 8th pin of the GD25Q128CSIG chip is connected to the 3.3V input voltage of the second CPU 7. The voltage is connected to the capacitor C8, and the capacitor C8 is connected to the ground electrode of the second CPU7. The capacitor C8 is used to provide a decoupling function for the input power supply of the U8 chip. The capacitance of the capacitor C8 is 100nF, and the withstand voltage is 50V. The resistance values ​​of the resistors R39, R40, R41, R42, R43 and R44 are all 10K ohms. The resistors R39~R42 are used as pull-up resistors to ensure the stability of the communication level of the second CPU7. The resistors R43 and R44 are the functional configuration resistors of the U8 chip.

[0038] The core operating voltage of the second CPU 7 is 1.14V to 1.32V, the I / O power supply voltage of the second CPU 7 is 3.0V to 3.6V, and the voltage fluctuation range is within ±5%, so the second CPU 7 can work normally. The embodiment of the utility model adopts 1.2V and 3.3V power supply voltages to power the second CPU 7. Figure 3As shown in (e), the second voltage monitoring subcircuit 12 is composed of a plurality of resistors. Resistor R35 is connected to the 3.3V input voltage of the second CPU 7 and resistor R37 respectively. The connection end of resistor R35 and resistor R37 is connected to the external monitoring module. Resistor R37 is connected to the grounding electrode of the second CPU 7. The resistance value of resistor R35 is 10K ohms with an accuracy of 1%. The resistance value of resistor R37 is 3K with an accuracy of 1%. Resistor R36 is connected to the 1.2V input voltage of the second CPU 7 and resistor R38 respectively. The connection end of resistor R36 and resistor R38 is connected to the external monitoring module. Resistor R38 is connected to the grounding electrode of the second CPU 7. The resistance values ​​of resistor R36 and resistor R38 are both 10K ohms with an accuracy of 1%. Resistor R35 and resistor R37 are used to divide the 3.3V input voltage, and resistor R36 and resistor R38 are used to divide the 1.2V input voltage.

[0039] like Figure 4 As shown, the comparison circuit includes: 2 serial port sub-circuits, 2 PWM wave transceiver sub-circuits and 4 GPIO sub-circuits, and the 2 serial port sub-circuits, 2 PWM wave transceiver sub-circuits and 4 GPIO sub-circuits are respectively connected to the first CPU1 and the CPU.

[0040] The 2-way serial port sub-circuit, the 2-way PWM wave transceiver sub-circuit and the 4-way GPIO sub-circuit are all composed of two ends of a resistor with a resistance value of 10 ohms connected to the first CPU 1 and the second CPU 7 respectively. Among them, the subcircuit where the resistor R1 in the serial port subcircuit is located is used by the first CPU1 to transmit the first CPU1 status information to the second CPU7, the subcircuit where the resistor R2 is located is used by the second CPU7 to transmit the second CPU7 status information to the first CPU1, the subcircuit where the resistor R3 is located is used by the first CPU1 to transmit the first CPU1 data information to the second CPU7, and the subcircuit where the resistor R4 is located is used by the second CPU7 to transmit the second CPU7 data information to the first CPU1; the subcircuit where the resistor R5 in the PWM wave transceiver subcircuit is used by the second CPU7 to transmit the second CPU7 clock frequency information to the first CPU1, and the subcircuit where the resistor R6 is located is used by the first CPU1 to transmit the first CPU1 clock frequency information to the second CPU7; the subcircuit where the resistor R7 and the resistor R9 in the GPIO subcircuit are used by the first CPU1 to transmit the lock step signal and the restart signal during the program running of the first CPU1 to the second CPU7, and the subcircuit where the resistor R8 and the resistor R10 are located is used by the second CPU7 to transmit the lock step signal and the restart signal during the program running of the second CPU7 to the first CPU1; the resistors R1~R10 are used to eliminate the influence caused by the level difference between the two CPUs.

[0041] The beneficial effects of the utility model are as follows:

[0042] The circuit structure of the utility model can realize the functions of temperature detection, voltage regulation, simultaneous reset, manual burning and data storage of the core business of the system board, and meets the 2x2 take 2 architecture requirements of the system, with low cost and simple structure.

[0043] This article uses specific examples to illustrate the principles and implementation methods of the utility model. The above examples are only used to help understand the method and core ideas of the utility model. At the same time, for those skilled in the art, according to the ideas of the utility model, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the utility model.

Claims

1. A dual CPU circuit suitable for a 2x2-take-2 architecture, comprising: The first CPU and the second CPU are characterized by further comprising: a first CPU peripheral circuit, a second CPU peripheral circuit and a comparison circuit; The first CPU peripheral circuit includes: a first temperature detection subcircuit, a first external voltage reference subcircuit, a first watchdog subcircuit, a first storage subcircuit and a first voltage monitoring subcircuit; the first CPU is respectively connected to the first temperature detection subcircuit, the first external voltage reference subcircuit, the first watchdog subcircuit, the first storage subcircuit and the first voltage monitoring subcircuit, and the first watchdog subcircuit is connected to the second CPU; The second CPU peripheral circuit includes: a second temperature detection subcircuit, a second external voltage reference subcircuit, a second watchdog subcircuit, a second storage subcircuit and a second voltage monitoring subcircuit; the second CPU is respectively connected to the second temperature detection subcircuit, the second external voltage reference subcircuit, the second watchdog subcircuit, the second storage subcircuit and the second voltage monitoring subcircuit, and the second watchdog subcircuit is connected to the first CPU; The comparison circuit includes: 2 serial port sub-circuits, 2 PWM wave transceiver sub-circuits and 4 GPIO sub-circuits, and the 2 serial port sub-circuits, 2 PWM wave transceiver sub-circuits and 4 GPIO sub-circuits are respectively connected to the first CPU and the CPU.

2. A dual CPU circuit suitable for a 2x2-take-2 architecture according to claim 1, characterized in that: The first temperature detection subcircuit has a built-in first temperature monitoring chip, and the first temperature monitoring chip is an M117B chip.

3. The dual CPU circuit suitable for 2x2x2 architecture according to claim 1, characterized in that: The first watchdog sub-circuit and the second watchdog sub-circuit are both equipped with a built-in watchdog circuit chip, and the watchdog circuit chip adopts a TPL5010DDCR chip; the TPL5010DDCR chip is used to reset the first CPU and the second CPU simultaneously.

4. The dual CPU circuit applicable to the 2x2-take-2 architecture according to claim 1, characterized in that: The first storage sub-circuit has a built-in first FLASH storage chip, and the first FLASH storage chip is a W25Q128JVSIM chip.

5. The dual CPU circuit applicable to the 2x2-take-2 architecture according to claim 1, characterized in that: The second temperature detection subcircuit has a built-in second temperature monitoring chip, and the second temperature monitoring chip is a TMP101NA / 3K chip.

6. The dual CPU circuit applicable to 2x2-take-2 architecture according to claim 1, characterized in that: The second storage sub-circuit has a built-in second FLASH storage chip, and the second FLASH storage chip is a GD25Q128CSIG chip.

7. The dual CPU circuit applicable to 2x2-take-2 architecture according to claim 1, characterized in that: The serial port subcircuit is used to send and receive status information and data information of the first CPU and the second CPU, the PWM wave transceiver subcircuit is used to provide an information transmission path, and the information transmission path is used to enable the first CPU and the second CPU to confirm clock frequency information with each other, and the GPIO subcircuit is used to transmit lock-step signals and restart signals during program execution of the first CPU and the second CPU.

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