Semiconductor structure and electronic equipment

Abstract

The utility model relates to a semiconductor structure and electronic equipment. The semiconductor structure comprises a first type region and a second type region which are adjacent and alternately arranged in sequence. The semiconductor structure further comprises a channel layer, a barrier layer, a first electrode, a second electrode and a grid electrode. The barrier layer is located on the channel layer. And the grids are positioned on one side, back to the channel layer, of the barrier layer. The first electrode and the second electrode are located on the two opposite sides of the grid electrode, make contact with the channel layer and extend out of the barrier layer in the direction from the channel layer to the barrier layer. The portions, located in the first type region and the second type region, of the first electrode, the grid electrode, the barrier layer and the channel layer are separated from one another. And the parts, located in the same first type region, of the first electrode and the grid electrode are electrically connected with each other.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a semiconductor structure and an electronic device. Background Art

[0002] In the related art, high electron mobility transistors (HEMTs) are increasingly used in production and life due to their properties. HEMT devices used in half-bridge circuits have a reverse freewheeling process, and HEMT itself has the ability to conduct in the reverse direction, but its turn-on voltage is determined by the threshold voltage, which is usually greater than 1.5V, and there will be large reverse conduction losses. Therefore, it is necessary to find a structure to replace HEMT to achieve the reverse freewheeling process to reduce the reverse conduction loss. However, while the current solution solves the problem, it will also bring about a more influential problem. Therefore, how to reduce the loss of HEMT devices in the reverse freewheeling process is still a problem that needs to be solved urgently. Summary of the invention

[0003] According to a first aspect of an embodiment of the present application, a semiconductor structure is provided, comprising first-type regions and second-type regions arranged adjacently and alternately; the semiconductor structure further comprises: a channel layer, a barrier layer, a first electrode, a second electrode and a gate;

[0004] The barrier layer is located on the channel layer; the gates are located on a side of the barrier layer facing away from the channel layer; the first electrode and the second electrode are located on opposite sides of the gate and in contact with the channel layer, and extend out of the barrier layer in a direction from the channel layer to the barrier layer;

[0005] The first electrode, the gate, the barrier layer and the channel layer are located between the first type region and the second type region and are separated from each other; the first electrode and the gate are located in the same first type region and are electrically connected to each other.

[0006] In some embodiments, the distance from the side of the gate facing the barrier layer to the side of the channel layer facing the barrier layer is a control performance distance;

[0007] The semiconductor structure is configured to be turned on when a voltage lower than a threshold voltage of the gate is applied to the gate, and the control performance distance located in the first type region is greater than the control performance distance located in the second type region.

[0008] In some embodiments, a portion of the barrier layer located in the first type region includes a control groove; and at least a portion of the gate located in the first type region is located in the control groove.

[0009] In some embodiments, the barrier layer includes a first sub-barrier layer and a second sub-barrier layer; the first sub-barrier layer is located on the side of the second sub-barrier layer facing away from the channel layer, and the second sub-barrier layer is located between the first sub-barrier layer and the channel layer; the gate includes a contact portion in contact with the first sub-barrier layer, and the first sub-barrier layer is formed by epitaxial growth at least synchronously with the contact portion.

[0010] In some embodiments, the gate includes a first sub-gate and a second sub-gate; the first sub-gate is located on the side of the second sub-gate facing away from the barrier layer, and the portion of the first sub-gate located in the first type region is used to be electrically connected to the first electrode located in the same first type region; the second sub-gate is located between the first sub-gate and the barrier layer, and is made of a different material from that of the first sub-gate; the contact portion includes the second sub-gate.

[0011] In some embodiments, the first sub-barrier layer and the second sub-barrier layer are made of the same material.

[0012] In some embodiments, the control performance distance within the first type of area is at least twice the control performance distance within the second type of area.

[0013] In some embodiments, it further includes: an isolation portion;

[0014] The isolation portion starts from a surface of the barrier layer facing away from the channel layer and extends into the channel layer, and the length of the isolation portion extending into the channel layer is at least half of the thickness of the channel layer;

[0015] The isolation portion is located at the junction of the first type region and the second type region; the isolation portion extends from the first electrode to a side of the gate facing away from the first electrode, and extends between the gate and the second electrode.

[0016] In some embodiments, the distance that the isolation portion extends from the gate in a direction from the gate toward the first electrode is less than one third of the distance between the gate and the second electrode.

[0017] According to a second aspect of the present application, an electronic device is provided, comprising any one of the above-mentioned semiconductor structures.

[0018] According to the above embodiments, the diode function in the reverse freewheeling is realized by the mutual electrical connection of the first electrode and the gate in the same first type region, so as to avoid the semiconductor structure being connected in parallel with other devices to produce parasitic effects and affect the high-frequency characteristics of the semiconductor structure. In addition, since the structures in the first type region and the second type region can be formed in the same layer, and the semiconductor-like structure of the part of the semiconductor structure located in the first type region is realized only by a simple wire connection method, the preparation cost of the semiconductor structure can be greatly reduced. Therefore, the above design can enable the semiconductor structure to realize the forward conduction and reverse freewheeling processes in the half-bridge circuit, while avoiding the influence of the high-frequency characteristics of the semiconductor structure by avoiding external devices of the semiconductor structure at a lower preparation cost.

[0019] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0021] Figure 1 It is a structural schematic diagram of a semiconductor structure according to an embodiment of the present application.

[0022] Figure 2 According to the embodiment of the present application Figure 1 The semiconductor structure is shown in a cross-sectional view along the section line AA.

[0023] Figure 3 According to the embodiment of the present application Figure 1 A cross-sectional view of a packaged semiconductor structure is shown.

[0024] Figure 4 It is an equivalent circuit diagram of a semiconductor structure located in a first type region and a second type region according to an embodiment of the present application.

[0025] Figure 5 According to the embodiment of the present application Figure 1 The semiconductor structure is shown in a cross-sectional view along the section line BB.

[0026] Figure 6 According to the embodiment of the present application Figure 1 The semiconductor structure is shown in a cross-sectional view along section line CC. DETAILED DESCRIPTION

[0027] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0028] In the prior art, the half-bridge circuit requires an alternately turned-on switch structure because it is used to achieve efficient high-power DC voltage to AC voltage conversion. The electron mobility transistor (HEMT) is often used in the half-bridge circuit due to its properties to play the role of an alternately turned-on switch structure. Since the half-bridge circuit is in the period between the steps of alternately turning on the switch structure, that is, one switch structure is closed and the other switch structure is not yet turned on, in order to prevent the instantaneous change of current from causing the inductor in the half-bridge circuit to generate a high induced electromotive force and damage other components in the half-bridge circuit, it is necessary to provide a low-impedance channel through a freewheeling device connected in parallel with the corresponding switch structure, so that the energy stored in the inductor can be gradually released through the freewheeling device to form a freewheeling current to prevent it from causing impact on the circuit.

[0029] When using the reverse conduction capability of the HEMT device itself to achieve the reverse freewheeling process, there will be large reverse conduction losses. Therefore, the solution of connecting a diode in parallel with the HEMT is a more feasible way. However, in this solution, parasitic effects are likely to occur between the parallel diode and the corresponding HEMT device, such as parasitic capacitance, which affects the high-frequency characteristics of the HEMT device. Therefore, how to reduce the loss of the HEMT device in the reverse freewheeling process is still a problem that needs to be solved urgently.

[0030] In order to solve the aforementioned problem, an embodiment of the present application provides a semiconductor structure 10 . Figure 1 FIG. 1 is a schematic diagram of the structure of the semiconductor structure 10. Figure 2 It is shown that Figure 1 The semiconductor structure 10 is shown in a cross-sectional view along the section line AA. Figure 1 and Figure 2As shown, the semiconductor structure 10 includes: first type regions Q1 and second type regions Q2 arranged adjacently and alternately. The semiconductor structure 10 may include one first type region Q1, or may include two first type regions Q1, or may include three first type regions Q1, but is not limited thereto, and the semiconductor structure 10 may also include a greater number of first type regions Q1. Similarly, the semiconductor structure 10 may also include one second type region Q2, or may include two second type regions Q2, or may include three second type regions Q2, but is not limited thereto, and the semiconductor structure 10 may also include a greater number of second type regions Q2.

[0031] The semiconductor structure 10 further includes a channel layer 11 , a barrier layer 12 , a first electrode 13 , a second electrode 14 and a gate 15 .

[0032] The barrier layer 12 is located on the channel layer 11. The gate 15 is located on the side of the barrier layer 12 facing away from the channel layer 11. The first electrode 13 and the second electrode 14 are located on opposite sides of the gate 15, and are in contact with the channel layer 11, and extend out of the barrier layer 12 along the direction from the channel layer 11 to the barrier layer 12. The first electrode 13 and the second electrode 14 can alternately serve as the source and the drain when the semiconductor structure 10 is in different working periods.

[0033] Specifically, the barrier layer 12 is in direct contact with the channel layer 11, and the band gap of the material forming the barrier layer 12 is higher than the band gap of the material forming the channel layer 11, so that when the barrier layer 12 and the channel layer 11 are subjected to an electric field, a two-dimensional electron gas (2DEG) is generated at the interface of the barrier layer 12 and the channel layer 11, facing the side of the channel layer 11, inside the heterojunction structure formed by the barrier layer 12 and the channel layer 11. By controlling the electric field applied to the barrier layer 12 and the channel layer 11, the semiconductor structure 10 can be turned on and off.

[0034] Furthermore, since the first electrode 13 and the second electrode 14 are in contact with the channel layer 11, if the two-dimensional electron gas exists, the first electrode 13 and the second electrode 14 can be connected through the two-dimensional electron gas. By controlling the formation of the two-dimensional electron gas (2DEG) on the side of the channel layer 11 at the interface between the barrier layer 12 and the channel layer 11 through the gate 15, the conduction and disconnection between the first electrode 13 and the second electrode 14 can be controlled.

[0035] The first electrode 13, the gate 15, the barrier layer 12 and the channel layer 11 are located between the first type region Q1 and the second type region Q2 and are separated from each other. The first electrode 13 and the gate 15 are located in the same first type region Q1 and are electrically connected to each other. The first electrode 13 and the gate 15 are located in the same first type region Q1 and are electrically connected to each other in a variety of ways. Figure 3 Shown Figure 1 In the cross-sectional view of the semiconductor structure 10 after packaging, the first electrode 13 and the gate 15 can be electrically connected to each other through the electrode 21 located on the surface of the packaging layer 20 .

[0036] It should be noted that the aforementioned electrical connection method of the first electrode 13 and the gate 15 located in the same first type region Q1 is only a feasible embodiment, but may not be limited thereto in other embodiments.

[0037] By electrically connecting the first electrode 13 and the gate 15 in the same first type region Q1, the semiconductor structure 10 in the first type region Q1 can function as a diode. Figure 4 The semiconductor structure 10 shown is an equivalent circuit diagram of a structure located in a first type region Q1 and a second type region Q2, wherein when current flows from the second electrode 14 to the first electrode 13, the portion of the gate 15 located in the second type region Q2 is turned on, and at the same time, current cannot flow from the second electrode 14 to the first electrode 13 through the first type region Q1, thereby realizing the conduction process of the semiconductor structure 10.

[0038] When the portion of the gate 15 located in the second type region Q2 is closed, the current generated by the inductor in the half-bridge circuit flows directly to the second electrode 14 via the first electrode 13. At this time, since the first electrode 13 and the portion of the gate 15 located in the same first type region Q1 are electrically connected to each other, the current flowing from the first electrode 13 to the second electrode 14 can simultaneously flow to the portion of the gate 15 located in the first type region Q1 to form a path between the first electrode 13 and the second electrode 14, thereby realizing the reverse freewheeling process.

[0039] The diode function in the reverse freewheeling is realized by the mutual electrical connection of the first electrode 13 and the gate 15 located in the same first type region Q1, so as to avoid the semiconductor structure 10 being connected in parallel with other devices to generate parasitic effects and affect the high frequency characteristics of the semiconductor structure 10. In addition, since the structures in the first type region Q1 and the second type region Q2 can be formed in the same layer, and the semiconductor-like structure of the part of the semiconductor structure 10 located in the first type region Q1 is realized only by a simple wire connection method, the preparation cost of the semiconductor structure 10 can be greatly reduced. Therefore, the above-mentioned design can enable the semiconductor structure 10 to realize the forward conduction and reverse freewheeling processes in the half-bridge circuit, and avoid affecting the high frequency characteristics of the semiconductor structure 10 by avoiding external devices of the semiconductor structure 10 at a lower preparation cost.

[0040] In some embodiments, Figure 5 It is shown that Figure 1 The semiconductor structure 10 is shown in a cross-sectional view along the section line BB. Figure 1 , Figure 2 and Figure 5 As shown, the distance between the side of the gate 15 facing the barrier layer 12 and the side of the channel layer 11 facing the barrier layer 12 is the control performance distance H.

[0041] The semiconductor structure 10 is configured to be turned on when a voltage lower than a threshold voltage is applied to the gate 15 , and the control performance distance H in the first type region Q1 is greater than the control performance distance H in the second type region Q2 .

[0042] Specifically, refer to Figure 2 and Figure 5 As shown, the control performance distance H in the first type area Q1 can be the first distance H1, and the control performance distance H in the second type area Q2 can be the second distance H2. Therefore, the control performance distance H in the first type area Q1 is greater than the control performance distance H in the second type area Q2, that is, the first distance H1 is greater than the second distance H2.

[0043] The semiconductor structure 10 is configured to be turned on when a voltage lower than the threshold voltage is applied to the gate 15, and the first distance H1 is greater than the second distance H2. At this time, since the gate 15 in the first type region Q1 is farther away from the channel layer 11, and the gate 15 in the second type region Q2 is closer to the channel layer 11, the portion of the semiconductor structure 10 located in the first type region Q1 can obtain a lower turn-on voltage, and the portion of the semiconductor structure 10 located in the first type region Q1 can obtain a higher threshold voltage, thereby further improving the high frequency characteristics of the semiconductor structure 10.

[0044] In some embodiments, Figure 5 As shown, the portion of the barrier layer 12 located in the first type region Q1 includes a control groove 121 . At least a portion of the gate 15 located in the first type region Q1 is located in the control groove 121 .

[0045] Such an arrangement can ensure a controllable performance distance H between the gate 15 and the channel layer 11 in the first type region Q1, thereby ensuring that the first distance H1 is greater than the second distance H2, to ensure that the gate 15 in the first type region Q1 is farther away from the channel layer 11, while the gate 15 in the second type region Q2 is closer to the channel layer 11, thereby enabling the portion of the semiconductor structure 10 located in the first type region Q1 to obtain a lower turn-on voltage, while enabling the portion of the semiconductor structure 10 located in the first type region Q1 to obtain a higher threshold voltage, thereby further improving the high frequency characteristics of the semiconductor structure 10.

[0046] In some embodiments, Figure 1 , Figure 2 , Figure 3 and Figure 5As shown, the barrier layer 12 includes a first sub-barrier layer 122 and a second sub-barrier layer 123. The first sub-barrier layer 122 is located on the side of the second sub-barrier layer 123 facing away from the channel layer 11, and the second sub-barrier layer 123 is located between the first sub-barrier layer 122 and the channel layer 11. The gate 15 includes a contact portion 150 in contact with the first sub-barrier layer 122, and the first sub-barrier layer 122 is at least formed by synchronous epitaxial growth with the contact portion 150.

[0047] It should be noted that the first sub-barrier layer 122 is epitaxially grown synchronously with the contact portion 150, which does not mean that the first sub-barrier layer 122 is epitaxially grown simultaneously with the contact portion 150. Instead, they are epitaxially grown successively in the same epitaxial growth stage.

[0048] In the aforementioned embodiment, the control groove 121 is provided to ensure the control performance distance H between the gate 15 and the channel layer 11 in the first type region Q1. In the etching process of forming the control groove 121 on the barrier layer 12, etching scars will inevitably be left at the control groove 121. As a result, the lattice coefficients of the control groove 121 and the materials of the gate 15 are mismatched, so that the gate 15 and the barrier layer 12 may have poor contact, or even the gate 15 may fall off.

[0049] Therefore, the barrier layer 12 is divided into a first sub-barrier layer 122 and a second sub-barrier layer 123. After the second sub-barrier layer 123 is etched with a groove to generate an etching scar, the first sub-barrier layer 122 is formed by synchronous epitaxial growth with at least the contact portion 150, so that there is a first sub-barrier layer 122 between the contact portion 150 and the second sub-barrier layer 123. Since the first sub-barrier layer 122 can be directly deposited on the second sub-barrier layer 123, and the groove naturally appears due to the surface morphology of the second sub-barrier layer 123 without etching, there is no etching scar in the first sub-barrier layer 122. The lattice coefficient of the first sub-barrier layer 122 will be more matched with the lattice coefficient of the contact portion 150, so that the bonding strength between the first sub-barrier layer 122 and the gate 15 can be enhanced, and further, the problem of poor contact between the gate 15 and the barrier layer 12 or even the gate 15 falling off can be avoided.

[0050] In some embodiments, Figure 1 , Figure 2 , Figure 3 and Figure 5As shown, the gate 15 includes a first sub-gate 151 and a second sub-gate 152. The first sub-gate 151 is located on the side of the second sub-gate 152 facing away from the barrier layer 12, and the portion of the first sub-gate 151 located in the first type region Q1 is used to be electrically connected to the first electrode 13 located in the same first type region Q1. The second sub-gate 152 is located between the first sub-gate 151 and the barrier layer 12, and is made of a different material from the first sub-gate 151. The contact portion 150 includes the second sub-gate 152.

[0051] Specifically, the first sub-gate 151 is mainly used to withstand the voltage applied to the gate and generate an electric field that can affect the heterojunction interface formed by the barrier layer 12 and the channel layer 11. Its material can specifically include a metal nitride material, such as titanium nitride (TiN), but is not limited thereto. The second sub-gate 152 is mainly used to induce an electric field with the film layer structure located on the side of the channel layer 11 facing away from the gate 15 in the semiconductor structure 10, so as to form a two-dimensional electron gas between the first electrode 13 and the second electrode 14 when the gate 15 is voltaged. Its material can include P-type doped gallium nitride (p-GaN). Moreover, in the case where the material of the second sub-gate can include P-type doped gallium nitride, the aforementioned film layer structure that induces an internal electric field with the second sub-gate 152 can be an N-type doped substrate 16, but is not limited thereto.

[0052] The contact portion 150 includes a second sub-gate 152, that is, the second sub-gate 152 is formed by synchronous epitaxial growth with the first sub-barrier layer 122, because the first sub-gate 151 itself needs to be formed successively with the second sub-gate 152. Therefore, by making the contact portion 150 include the second sub-gate 152, it is possible to enhance the bonding strength between the first sub-barrier layer 122 and the gate 15 while being more compatible with the existing preparation process, thereby avoiding the problem of poor contact between the gate 15 and the barrier layer 12, or even the gate 15 falling off, with lower technical difficulty and cost.

[0053] In some embodiments, the first sub-barrier layer 122 and the second sub-barrier layer 123 are made of the same material, wherein the material of the first sub-barrier layer 122 and the second sub-barrier layer 123 may specifically include aluminum gallium nitride (AlGaN), but is not limited thereto.

[0054] Such an arrangement is actually achieved by forming the parts of the barrier layer 12 in sequence, so that the surface where the barrier layer 12 contacts the gate 15 has both a control groove 121 and a good match with the lattice coefficient of the gate 15, thereby specifically avoiding the possible poor contact between the gate 15 and the barrier layer 12 or even the detachment of the gate 15.

[0055] In some embodiments, the control performance distance H in the first type region Q1 is at least twice the control performance distance H in the second type region Q2.

[0056] The inventors have confirmed through experiments that such a configuration can achieve the most appropriate effect of making the portion of the semiconductor structure 10 located in the first type region Q1 obtain a lower turn-on voltage and the portion of the semiconductor structure 10 located in the first type region Q1 obtain a higher threshold voltage, thereby further improving the high-frequency characteristics of the semiconductor structure 10.

[0057] In some embodiments, Figure 6 It is shown that Figure 1 The semiconductor structure 10 is shown in a cross-sectional view along the section line CC. Figure 1 and Figure 6 As shown, the semiconductor structure 10 further includes an isolation portion 17 .

[0058] The isolation portion 17 extends from a surface of the barrier layer 12 facing away from the channel layer 11 and into the channel layer 11 , and the length of the isolation portion 17 extending into the channel layer 11 is at least half of the thickness of the channel layer 11 .

[0059] The isolation portion 17 is located at the boundary between the first type region Q1 and the second type region Q2 . The isolation portion 17 extends from the first electrode Q1 to the side of the gate 15 facing away from the first electrode 13 , and extends between the gate and the second electrode 14 .

[0060] It should be noted that due to Figure 6 The cross-sectional view is shown, so the gate 15 and part of the first electrode 13 located next to the isolation portion 17 can be seen through perspective. Figure 1 It can be seen that there is no gate 15 disposed above the isolation portion 17 , and the first electrode 13 does not extend into the isolation portion 17 .

[0061] By providing the isolation portion 17, the main part of the semiconductor structure 10 located in the first type region Q1 and the second type region Q2 can be effectively separated, that is, the first electrode 13, the gate 15, the barrier layer 12 and the channel layer 11 located in the first type region Q1 and the second type region Q2 can be separated. The part located between the gate 15 and the second electrode 14 and the second electrode 14 are the parts that can be shared. Therefore, by extending the isolation portion 17 from the first electrode Q1 to the side of the gate 15 facing away from the first electrode 13, and extending to between the gate and the second electrode 14, the part located between the gate 15 and the second electrode 14 can be shared, thereby further improving the high-frequency characteristics of the semiconductor structure 10.

[0062] In some embodiments, Figure 1 and Figure 6As shown, the isolation portion 17 extends from the gate 15 in a direction away from the first electrode 13 , and the distance is less than one third of the distance between the gate 15 and the second electrode 14 .

[0063] The distance of the isolation portion 17 extending from the gate 15 in the direction away from the first electrode 13 is Figure 6 The distance between the gate 15 and the second electrode 14 is Figure 6 The length L2 is shown in FIG.

[0064] By making the length L1 less than one third of the length L2, it can be ensured that the isolation portion 17 effectively separates the first electrode 13, the gate 15, the barrier layer 12 and the channel layer 11 located in the first type area Q1 and the second type area Q2, while maximizing the sharing of the portion located between the gate 15 and the second electrode 14. Therefore, the isolation effect of the isolation portion 17 can be ensured while improving the high-frequency characteristics of the semiconductor structure 10.

[0065] In some embodiments, the semiconductor structure 10 may be at least one of two switch structures included in a half-bridge circuit.

[0066] In some embodiments, Figure 2 , Figure 3 , Figure 5 and Figure 6 As shown, the semiconductor structure 10 further includes a buffer layer 18 . The buffer layer 18 is located between the channel layer 11 and the substrate 16 , and is used to better epitaxially grow the channel layer 11 on the substrate 16 .

[0067] The present application also provides an electronic device, comprising any one of the semiconductor structures 10 described above.

[0068] The above embodiments of the present application may complement each other if no conflict occurs.

[0069] It should be noted that in the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. It is also understood that when an element or layer is referred to as being "on" another element or layer, it may be directly on the other element, or there may be an intermediate layer. In addition, it is understood that when an element or layer is referred to as being "under" another element or layer, it may be directly under the other element, or there may be more than one intermediate layer or element. In addition, it is also understood that when a layer or element is referred to as being "between" two layers or two elements, it may be the only layer between the two layers or two elements, or there may also be more than one intermediate layer or element. Similar reference numerals throughout the text indicate similar elements.

[0070] The term "plurality" means two or more than two, unless expressly limited otherwise.

[0071] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practice. The present application is intended to cover any variations, uses or adaptations of the present application, which follow the general principles of the present application and include common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0072] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A semiconductor structure, characterized in that: The semiconductor structure comprises first-type regions and second-type regions which are arranged adjacently and alternately in sequence; the semiconductor structure further comprises: a channel layer, a barrier layer, a first electrode, a second electrode and a gate; The barrier layer is located on the channel layer; the gates are located on a side of the barrier layer facing away from the channel layer; the first electrode and the second electrode are located on opposite sides of the gate and in contact with the channel layer, and extend out of the barrier layer in a direction from the channel layer to the barrier layer; The first electrode, the gate, the barrier layer and the channel layer are located between the first type region and the second type region and are separated from each other; the first electrode and the gate are located in the same first type region and are electrically connected to each other.

2. The semiconductor structure according to claim 1, characterized in that: The distance between the side of the gate facing the barrier layer and the side of the channel layer facing the barrier layer is the control performance distance; The semiconductor structure is configured to be turned on when a voltage lower than a threshold voltage of the gate is applied to the gate, and the control performance distance located in the first type region is greater than the control performance distance located in the second type region.

3. The semiconductor structure according to claim 2, characterized in that: The portion of the barrier layer located in the first type region includes a control groove; at least a portion of the gate located in the first type region is located in the control groove.

4. The semiconductor structure according to claim 3, characterized in that: The barrier layer includes a first sub-barrier layer and a second sub-barrier layer; the first sub-barrier layer is located on the side of the second sub-barrier layer facing away from the channel layer, and the second sub-barrier layer is located between the first sub-barrier layer and the channel layer; the gate includes a contact portion in contact with the first sub-barrier layer, and the first sub-barrier layer is formed by epitaxial growth at least synchronously with the contact portion.

5. The semiconductor structure according to claim 4, characterized in that: The gate includes a first sub-gate and a second sub-gate; the first sub-gate is located on the side of the second sub-gate facing away from the barrier layer, and the part of the first sub-gate located in the first type area is used to be electrically connected to the first electrode located in the same first type area; the second sub-gate is located between the first sub-gate and the barrier layer, and is made of a different material from that of the first sub-gate; the contact part includes the second sub-gate.

6. The semiconductor structure according to claim 4, characterized in that: The first sub-barrier layer and the second sub-barrier layer are made of the same material.

7. The semiconductor structure according to claim 2, characterized in that: The control performance distance within the first type of area is at least twice the control performance distance within the second type of area.

8. The semiconductor structure according to claim 1, characterized in that: Also includes: Isolation Department; The isolation portion starts from a surface of the barrier layer facing away from the channel layer and extends into the channel layer, and the length of the isolation portion extending into the channel layer is at least half of the thickness of the channel layer; The isolation portion is located at the junction of the first type region and the second type region; the isolation portion extends from the first electrode to a side of the gate facing away from the first electrode, and extends between the gate and the second electrode.

9. The semiconductor structure according to claim 8, characterized in that: The distance that the isolation portion extends out of the gate along a direction in which the gate faces away from the first electrode is less than one third of the distance between the gate and the second electrode.

10. An electronic device, characterized in that: A semiconductor structure comprising any one of claims 1 to 9.

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