Test signal generating circuit for measuring time delay of logic unit of integrated circuit
Through the test signal generation circuit combined with the ring oscillator and the frequency divider, the accuracy of the delay of the logic unit in the high-frequency circuit is solved by cascaded logic units and measuring the oscillation period of the frequency divider signal, and a high-precision and efficient measurement effect is achieved.
Patent Information
- Application Number
- CN202422157315.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-02
- Publication Date
- 2025-07-04
- Estimated Expiration
- 2034-09-02
AI Technical Summary
The prior art is difficult to accurately measure the delay of logic units in high-frequency, low-power, and high-integration integrated circuits, affecting the stability and reliability of the circuit.
The test signal generation circuit using a combination of a ring oscillator and a frequency divider is used to cascade the logic unit and amplify the signal, and the oscillation period is measured by using the frequency divider signal to obtain the delay of the logic unit.
It improves the measurement accuracy and efficiency of logic unit delay, and is suitable for the measurement needs of high-frequency, low-power, and high-integration circuits. It has a simple circuit structure and a small area occupancy.
Smart Images
Figure CN223067079U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the field of integrated circuits, in particular to a test signal generation circuit for measuring the delay of logic units in integrated circuits. Background Art
[0002] With the development of modern integrated circuits, the demand for circuit speed and performance is increasing day by day. Especially in high-frequency and high-speed circuits, accurate measurement of signal delay becomes crucial. Delay measurement has important applications in fields such as timing analysis, delay chain calibration, and pulse width modulation.
[0003] The delay of logic units is one of the key parameters, which affects the overall performance and timing of the circuit. Especially in high-frequency, low-power, and high-integration circuit designs, accurate measurement of the delay of logic units is crucial for ensuring the stability and reliability of the circuit.
[0004] However, with the reduction of process dimensions, conventional measurement methods for measuring the delay of logic units are difficult to meet the accurate measurement requirements in complex circuit structures. In large-scale circuits, logic units are widely used, so a small deviation in accuracy will have a great impact on the overall timing and performance of integrated circuits.
[0005] How to accurately measure the delay of a single logic unit (such as a logic gate circuit) has become a key technical issue in integrated circuit design. Summary of the Utility Model
[0006] The purpose of the utility model is to provide a test signal generation circuit for measuring the delay of logic units in integrated circuits, which can solve the problems of accuracy and efficiency in measuring the delay of logic units in integrated circuits. Through this circuit, a test signal for measuring the delay of logic units can be quickly generated to obtain an accurate delay of logic units.
[0007] An embodiment of the utility model provides a test signal generation circuit for measuring the delay of logic units in integrated circuits, including:
[0008] A first ring oscillator and a first frequency divider;
[0009] The first ring oscillator includes: 2M cascaded logic units and a reverse unit; the output terminal of the last logic unit among the 2M cascaded logic units is connected to the first input terminal of the reverse unit, the second input terminal of the reverse unit is connected to an enable input signal; the output terminal of the reverse unit is connected to the input terminal of the first logic unit among the 2M cascaded logic units; M≥50;
[0010] The input end of the first frequency divider is connected to the output end of the inversion unit to receive the first oscillation signal output by the first ring oscillator. The output end of the first frequency divider outputs a frequency-divided signal of the first oscillation signal, which is a test signal for measuring the delay of a logic unit in an integrated circuit.
[0011] Preferably, the inversion unit is a NAND gate.
[0012] Preferably, the logic unit includes: basic logic gates.
[0013] Preferably, the logic unit specifically includes: one of an AND gate, an OR gate, a NOT gate, a NAND gate, a NOR gate, an XOR gate, or an XNOR gate.
[0014] Preferably, the logic unit in the test signal generation circuit and the integrated circuit logic unit are fabricated through the same process.
[0015] Preferably, the test signal generation circuit further includes: an inversion unit delay measurement circuit;
[0016] The inversion unit delay measurement circuit includes: a second ring oscillator and a second frequency divider;
[0017] The second ring oscillator includes: 2M + 1 cascaded inversion units; wherein, the output end of each stage of the inversion unit is connected to the first input end of the next stage of the inversion unit, the second input end of each stage of the inversion unit is connected to an enable input signal; the output end of the last stage of the inversion unit is connected to the input end of the first stage of the inversion unit;
[0018] The input end of the second frequency divider is connected to the output end of the last stage of the inversion unit to receive the second oscillation signal output by the second ring oscillator. The output end of the second frequency divider outputs a frequency-divided signal of the second oscillation signal, which is a test signal for measuring the delay of the inversion unit.
[0019] The test signal generation circuit for measuring the delay of a logic unit in an integrated circuit provided by an embodiment of the present invention cascades logic units and combines a ring oscillator structure and a frequency divider. The signal amplification of the logic unit delay is achieved through cascading, and the delay of a single logic unit can be accurately obtained by measuring the oscillation period after frequency division. The proposed test signal generation circuit significantly improves the measurement accuracy and efficiency of the logic unit delay. The circuit structure is simple and easy to implement, occupies a small area in the integrated circuit, is applicable to scenarios such as integrated circuit design verification and fault diagnosis, and can effectively meet the measurement requirements of high-frequency, low-power, and high-integration integrated circuits. Description of the Drawings
[0020] Figure 1It is the logic schematic diagram of the test signal generation circuit for measuring the delay of the logic unit of the integrated circuit provided by the embodiment of the present invention;
[0021] Figure 2 It is the circuit diagram of a specific implementation of the test signal generation circuit for measuring the delay of the logic unit of the integrated circuit provided by the embodiment of the present invention;
[0022] Figure 3 For Figure 2 It is the waveform schematic diagram corresponding to the provided circuit. Specific embodiments
[0023] Next, through the drawings and embodiments, the technical solutions of the present invention will be further described in detail.
[0024] The test signal generation circuit for measuring the delay of the logic unit of the integrated circuit provided by the embodiment of the present invention, Figure 1 It is the logic schematic diagram of the test signal generation circuit for measuring the delay of the logic unit of the integrated circuit provided by the embodiment of the present invention.
[0025] As Figure 1 shown, the test signal generation circuit proposed in this embodiment includes: a first ring oscillator 10 and a first frequency divider 20.
[0026] The first ring oscillator 10 includes: 2M cascaded logic units and a reverse unit; the output end of the last logic unit in the 2M cascaded logic units is connected to the first input end of the reverse unit, and if there is a second input end in the reverse unit, it is connected to the enable input signal; the output end of the reverse unit is connected to the input end of the first logic unit in the 2M cascaded logic units.
[0027] In this application, the purpose of cascading the logic units in the circuit design is to accumulate the signal delays of the logic units through cascading, so as to achieve the purpose of amplifying the delay of the logic units. Considering that the signal delay of each logic unit is very small, it is preferably set that the cascading is not less than 100 levels, and to ensure that the signals at the output end and the input end of the cascading have the same phase, so the signal fed back to the input end of the cascading after passing through the reverse unit is a reverse signal, so it is set to an even number of cascades, so M≥50 is set.
[0028] The input end of the first frequency divider 20 is connected to the output end of the reverse unit, receives the first oscillation signal output by the first ring oscillator 10, and the output end of the first frequency divider 20 outputs a frequency-divided signal of the first oscillation signal, which is the test signal for measuring the delay of the logic unit in the integrated circuit.
[0029] In a specific implementation, the reverse unit is preferably a NAND gate.
[0030] In the field of digital circuit technology, a logic unit is a circuit component in a digital circuit that performs basic logic operations. According to classification, it can include basic logic gates, combinational logic units, sequential logic units, and composite logic units, etc. All kinds of devices in combinational logic units, sequential logic units, and composite logic units are composed of basic logic gates. Therefore, the accurate measurement of the delay of basic logic gates is very important.
[0031] In this embodiment, the logic unit specifically includes basic logic gates. Further, specifically, it includes one of an AND gate, an OR gate, a NOT gate, a NAND gate, a NOR gate, an XOR gate, or an XNOR gate.
[0032] The test signal generation circuit for measuring the delay of an integrated circuit logic unit in this solution is fabricated on the integrated circuit. In the design and fabrication of an integrated circuit, there will be a separate area on the layout design for placing the test circuit, that is, a corresponding test circuit is formed on the fabricated chip. The logic unit in the test signal generation circuit proposed in this solution and the logic unit in the integrated circuit applying this test signal generation circuit are fabricated through the same process. Therefore, the test signal generated by the test signal generation circuit can truly reflect the delay of the integrated circuit logic unit.
[0033] To better understand the technical solution of the present invention, the following will be described with a specific example.
[0034] Figure 2 This is a circuit diagram of a specific implementation of the test signal generation circuit for measuring the delay of an integrated circuit logic unit provided in the embodiment of the present invention. In this embodiment, the logic unit is a NOT gate, the inversion unit is a NAND gate, and the cascading level of the logic unit is 100. Figure 2 The ×100 between the two NOT gates in the figure indicates that there are a total of 100 cascaded NOT gates including the two drawn NOT gates.
[0035] One hundred cascaded NOT gates are connected to a NAND gate to form the first ring oscillator; due to the existence of a feedback path, the signal will circulate in the ring oscillator. To make the circuit oscillate, the total delay should be long enough, and it is ensured that when the signal returns to the input terminal of the first NOT gate, it is inverted with the previous signal, thereby triggering the next oscillation. For example, when the feedback signal output from the first ring oscillator for the first time returns to the input terminal of the first NOT gate, the signal is in the opposite state to the initial signal (phase difference of 180 degrees); when the feedback signal output from the first ring oscillator for the second time returns to the input terminal of the first NOT gate, the signal is in the same state as the initial signal. For a complete oscillation period, the signal needs to go through two state flips (such as: high to low, low to high), that is, two laps through the first ring oscillator. That is, two complete cycles of propagation form an oscillation period.
[0036] In this way, the delay of the 100 NOT gates cascaded in the first ring oscillator is accumulated to cell_delay × 100, where cell_delay refers to the delay of a logic cell. Without considering the delay of the inverter cell, cell_delay × 100 becomes half of the oscillation period.
[0037] The oscillation signal (OUT in the figure) output by the first ring oscillator is divided by a frequency divider and then the divided signal osc_div_out is output.
[0038] The output terminal of the frequency divider can be connected to an external measurement device, which can measure the oscillation period after division by monitoring this signal, and thus obtain the cell_delay value of a single logic cell (such as Figure 2 the NOT gate in
[0039] The external measurement device can be a device specifically including the following types, which is used to measure the oscillation period after division.
[0040] 1. Oscilloscope: An oscilloscope can capture and display the waveform of the oscillation signal and accurately measure the period and frequency of the signal.
[0041] 2. Frequency meter: A frequency meter can directly measure the frequency of the signal and calculate the period through the reciprocal of the frequency.
[0042] 3. Logic analyzer: A logic analyzer can capture and analyze the timing of digital signals and can accurately measure the signal period.
[0043] 4. Time-to-Digital Converter (TDC): A TDC can measure the time interval of the signal with high precision and calculate the period.
[0044] Figure 2 The waveform diagram corresponding to the provided circuit is as Figure 3 shown. It can be seen that after the enable signal en turns into a high-valid signal, the OUT signal is set low, and the divided signal osc_div_out is also set low. The first input of the first ring oscillator is a low-level signal. After the delay of 100 NOT gates cascaded, the output signal A of the last NOT gate also becomes low. In actual situations, due to the delay of the NAND gate, after passing through Figure 3After the delay corresponding to the NAND cell delay marked in the figure, the OUT signal will invert and become a high-level signal. At this time, the OUT signal is set high, and the frequency-divided signal osc_div_out is also set high, completing half an oscillation period, as represented by T / 2 in the figure. At this time, the second input of the first ring oscillator is a high-level signal, and the second half of the oscillation period is completed according to the circuit logic.
[0045] The frequency-divided signal osc_div_out is the test signal used to measure the delay of the integrated circuit logic unit. Based on this signal, the delay cell_delay of the logic unit can be easily obtained.
[0046] In practical applications, the oscillation period T of the frequency-divided signal osc_div_out can be measured by an external measuring device connected to the test signal generation circuit.
[0047] Then, the cell_delay value is calculated by the calculation unit and obtained according to the following formula:
[0048] cell_delay = [ T / (2×N) - t0 ] / 100 (Formula 1);
[0049] Among them, T is the oscillation period measured by the external measuring device, N is the frequency division multiple of the frequency divider, and t0 represents the delay of the NAND gate, that is, the NAND cell delay.
[0050] The above is the calculation formula for 100 cascaded logic units. For 2M cascaded logic units, cell_delay = [ T / (2×N) - t0 ] / 2M (Formula 2).
[0051] The delay of the NAND gate can be directly substituted with the delay data of the NAND gate obtained by simulation during the integrated circuit design stage. Because even if there is a certain error in the delay data of the NAND gate, it is very small compared to the delay of 100 cascaded NAND gates and can be ignored for the calculation result.
[0052] Of course, in order to obtain more accurate results, a reverse unit delay measurement circuit can also be designed separately in the test circuit. The circuit logic of the reverse unit delay measurement circuit is the same as that of the test signal generation circuit.
[0053] The reverse unit delay measurement circuit includes: a second ring oscillator and a second frequency divider;
[0054] The second ring oscillator includes: 2M + 1 cascaded inverter units; wherein, the output terminal of each stage of inverter unit is connected to the first input terminal of the next stage of inverter unit, the second input terminal of each stage of inverter unit is connected to an enable input signal; the output terminal of the last stage of inverter unit is connected to the input terminal of the first stage of inverter unit; that is, all logic units are set as inverter units.
[0055] The input terminal of the second frequency divider is connected to the output terminal of the last stage of inverter unit to receive the second oscillation signal output by the second ring oscillator, and the output terminal of the second frequency divider outputs a frequency-divided signal of the second oscillation signal, which is a test signal for measuring the delay of the inverter unit.
[0056] For example, in the Figure 2 same circuit, replacing all inverter units with NAND gates realizes a circuit for measuring the delay of inverter units. At this time, the obtained cell_delay is the delay of the NAND gate, that is, t0 in Formulas 1 and 2.
[0057] According to the same logic, it can be measured that cell_delay = t0 = T / (2×N) / 101.
[0058] The test signal generation circuit provided in this embodiment can be applied to specific application scenarios such as integrated circuit design and verification, delay chain calibration, pulse width modulation, etc.
[0059] The embodiment of the present utility model provides a test signal generation circuit for measuring the delay of logic units in an integrated circuit. By cascading logic units and combining a ring oscillator structure and a frequency divider, signal amplification of the delay of logic units is achieved through cascading, and the delay of a single logic unit can be accurately obtained by measuring the divided oscillation period. The proposed test signal generation circuit of the present invention greatly improves the measurement accuracy and efficiency of the delay of logic units. The circuit structure is simple and easy to implement, occupies a small area in the integrated circuit, is applicable to scenarios such as integrated circuit design verification and fault diagnosis, and can effectively meet the measurement requirements of high-frequency, low-power, and high-integration integrated circuits.
[0060] The above specific implementation manners further elaborate on the purpose, technical solutions, and beneficial effects of the present utility model. It should be understood that the above are only specific implementation manners of the present utility model and are not used to limit the protection scope of the present utility model. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present utility model shall be included in the protection scope of the present utility model.
Claims
1. A test signal generation circuit for measuring the delay of an integrated circuit logic unit, characterized in that, The test signal generation circuit includes: a first ring oscillator and a first frequency divider; The first ring oscillator includes: 2M cascaded logic units and an inverter; the output terminal of the last logic unit among the 2M cascaded logic units is connected to the first input terminal of the inverter, the second input terminal of the inverter is connected to an enable input signal; the output terminal of the inverter is connected to the input terminal of the first logic unit among the 2M cascaded logic units; M≥50; The input terminal of the first frequency divider is connected to the output terminal of the inverter, receives the first oscillation signal output by the first ring oscillator, and the output terminal of the first frequency divider outputs a frequency-divided signal of the first oscillation signal, which is the test signal for measuring the delay of the logic unit in the integrated circuit.
2. The test signal generating circuit according to claim 1, wherein The inverter is a NAND gate.
3. The test signal generating circuit according to claim 1, wherein The logic unit includes: basic logic gates.
4. The test signal generating circuit according to claim 1 or 3, characterized in that, Specifically, the logic unit includes one of an AND gate, an OR gate, a NOT gate, a NAND gate, a NOR gate, an XOR gate, or an XNOR gate.
5. The test signal generating circuit according to claim 1, wherein The logic units in the test signal generation circuit and the integrated circuit logic units are fabricated through the same process.
6. The test signal generating circuit according to claim 1, wherein The test signal generation circuit further includes: an inverter delay measurement circuit; The inverter delay measurement circuit includes: a second ring oscillator and a second frequency divider; The second ring oscillator includes: 2M + 1 cascaded inverters; wherein, the output terminal of each inverter is connected to the first input terminal of the next inverter, the second input terminal of each inverter is connected to an enable input signal; the output terminal of the last inverter is connected to the input terminal of the first inverter; The input terminal of the second frequency divider is connected to the output terminal of the last inverter, receives the second oscillation signal output by the second ring oscillator, and the output terminal of the second frequency divider outputs a frequency-divided signal of the second oscillation signal, which is the test signal for measuring the delay of the inverter.