Middle-high voltage shielding grid power MOSFET layout

Abstract

The embodiment of the utility model provides a middle-high voltage shielding grid power MOSFET layout, which is mainly characterized in that on the basis of the prior art, a mask region of a second injection region is added in a part of a first injection region, so that two different threshold voltages exist in the whole MOSFET, the current mainly flows out from a groove with low threshold voltage, and the current can flow out from a groove with low threshold voltage under the condition that other processes are not changed. According to the invention, the MOSFET can be in a safe working area, and the overcurrent capability of the safe working area of the MOSFET is optimized.

Description

Technical Field

[0001] Embodiments of the present application belong to the field of semiconductor technology, and in particular, relate to a layout of a medium-voltage shielded gate power MOSFET. Background Art

[0002] In the layout design of a shielded gate power MOSFET, it is necessary to separately connect out the source polysilicon electrode, the gate electrode, and the source electrode, and isolate the source polysilicon electrode from the gate electrode. As Figure 1 shown, generally, in a chip, there will be a first implantation region 03 and a second implantation region (not shown) from bottom to top between two adjacent trenches 01. As Figure 3 shown, however, the junction depth of the PN junction between two such trenches 01 is the same, and this structure will cause the shielded gate power MOSFET to be unable to optimize the overcurrent capacity of the safe operating area. Summary of the Invention

[0003] To solve or alleviate the problems in the prior art, embodiments of the present application provide a layout of a medium-voltage shielded gate power MOSFET, including: an isolation ring region, a plurality of trench regions, a first implantation region, and a second implantation region;

[0004] The isolation ring regions are arranged at intervals outside the trench regions;

[0005] The plurality of trench regions are arranged at intervals, and the first implantation region and the second implantation region are arranged between two adjacent trench regions, and a mask region of the second implantation region is arranged above a part of the first implantation regions.

[0006] As a preferred embodiment of the present application, a preset number of trench regions are arranged at intervals between two adjacent mask regions.

[0007] As a preferred embodiment of the present application, the preset number is 3.

[0008] Compared with the prior art, the layout of a medium-voltage shielded gate power MOSFET provided by the embodiments of the present application mainly adds a mask region of the second implantation region to a part of the first implantation regions on the basis of the prior art. Therefore, there are two different threshold voltages in the entire MOSFET, and the current mainly flows out from the trench with a lower threshold voltage. Without changing other processes, the present application can make the MOSFET in the safe operating area and optimize the overcurrent capacity of the safe operating area of the MOSFET. Description of the Drawings

[0009] The accompanying drawings described herein are used to provide a further understanding of the present application and form a part of the present application. The schematic embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation of the present application. Some specific embodiments of the present application will be described in detail hereinafter with reference to the accompanying drawings in an exemplary rather than restrictive manner. The same reference numerals in the drawings denote the same or similar components or parts. Those skilled in the art should understand that these drawings are not necessarily drawn to scale. In the drawings:

[0010] Figure 1 is a layout of a medium-voltage shielded-gate power MOSFET provided by the prior art;

[0011] Figure 2 is a layout of a medium-voltage shielded-gate power MOSFET provided by the present application;

[0012] Figure 3 is a simulation diagram of a MOSFET prepared from a layout of a medium-voltage shielded-gate power MOSFET provided by the prior art;

[0013] Figure 4 is a simulation diagram of a MOSFET prepared from a layout of a medium-voltage shielded-gate power MOSFET provided by the present application; Detailed Embodiments

[0014] In order to enable those skilled in the art to better understand the solution of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the scope of protection of the present application.

[0015] As Figure 2 shown, the embodiments of the present application provide a layout of a medium-voltage shielded-gate power MOSFET, including: an isolation ring region 02, a plurality of trench regions 01, a first implantation region 03, and a second implantation region (not shown);

[0016] The isolation ring region 02 is disposed at intervals around the trench regions 01;

[0017] The plurality of trench regions 01 are disposed at intervals, and the first implantation region 03 and the second implantation region (not shown) are disposed between two adjacent trench regions 01. A mask region 04 of the second implantation region is disposed above a part of the first implantation regions 03.

[0018] As a preferred embodiment of the present application, a preset number of trench regions 01 are spaced between two adjacent mask regions 04.

[0019] As a preferred embodiment of the present application, the preset quantity is 3.

[0020] As Figure 4 shown, from the MOSFET simulation diagram prepared from the layout of a medium and high voltage shielded gate power MOSFET provided by the present application, it can be obtained that by adding the mask region 04 of the second implantation region to a part of the first implantation region 03, the junction depths of the PN junctions between two trenches 01 in the MOSFET obtained by the present application are different. Therefore, there are two different threshold voltages in the entire MOSFET, and the current mainly flows out from the trench with a lower threshold voltage. Without changing other processes, the present application can make the MOSFET in the safe operating area and optimize the overcurrent capacity of the safe operating area of the MOSFET.

[0021] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A layout of a medium- and high-voltage shield-gate power MOSFET, characterized in that, Including: An isolation ring region, a plurality of trench regions, a first implantation region, and a second implantation region; The isolation ring regions are arranged at intervals around the trench regions; The plurality of trench regions are arranged at intervals, and the first implantation region and the second implantation region are arranged between two adjacent trench regions, and a mask region of the second implantation region is arranged above a part of the first implantation region.

2. The layout of a medium-high voltage shield gate power MOSFET as described in claim 1, wherein A preset number of trench regions are spaced between two adjacent mask regions.

3. The layout of a medium- and high-voltage shielded-gate power MOSFET according to claim 2, wherein, The preset number is 3.

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