Photoelectric test structure and system

Abstract

The utility model provides a photoelectric test structure and system, and the structure comprises a substrate which is provided with a first type of well region, and the first type of well region and the substrate have the same doping ion type; the charge storage doped region is arranged in the first type of well region, and a PN junction is formed at the interface of the charge storage doped region and the first type of well region; a transfer gate structure disposed on the substrate; the source electrode region and the drain electrode region of the test transistor are arranged in the first type of well region, the grid electrode structure of the test transistor is arranged on the substrate, the grid electrode structure of the test transistor is adjacent to the transmission grid electrode structure, and the grid electrode structure of the test transistor is kept at a high potential; and an output port connected to the drain region of the test transistor and outputting a first current when the transfer gate structure is in a floating state and outputting a second current when the transfer gate structure is in a low potential. According to the utility model, the white point condition of the image can be rapidly measured.

Description

TECHNICAL FIELD

[0001] The utility model relates to image sensing technical field, especially relate to a photoelectric test structure and system. BACKGROUND

[0002] Image sensor is a kind of semiconductor element that converts optical image into electronic signal, its working principle is that light signal is converted into photo-generated charge by photosensitive device, photo-generated charge is collected and handled to convert into voltage or current signal, and photoelectric signal is finally output in the form of digital signal.Dark performance is an important performance index of image sensor, is directly related to the imaging effect of image.

[0003] In the actual operation of image sensor, not all the signal conversion electronics come from photoelectric conversion. Among them, the source of non-photoelectric conversion electron is many, with the continuous reduction of transistor size, for example, gate-induced drain leakage (GIDL) will generate interference signal non-photoelectric conversion electron. This part of electron is difficult to be measured by conventional test equipment, and image white point can be seen after image output test, and image white point is detected by relying on image output, and the test cycle is longer, which greatly reduces the research and development efficiency. UTILITY MODEL CONTENT

[0004] The utility model aims at providing a photoelectric test structure and system, can test the white point condition of image in time and fast, to improve research and development efficiency.

[0005] To solve the above technical problems, the utility model is realized by the following technical schemes:

[0006] The utility model provides a photoelectric test structure, it includes:

[0007] Substrate, first type well area is arranged in the substrate, the first type well area and the doping ion type of the substrate are same;

[0008] Charge storage doped region is arranged in the first type well area, wherein PN junction is formed at the boundary of the charge storage doped region and the first type well area;

[0009] Transmission gate structure is arranged on the substrate, and the first end of the transmission gate structure is located on the first type well area and is located on the side of the charge storage doped region;

[0010] a test transistor having a source region and a drain region disposed in the first type of well region, and a gate structure disposed on the substrate, wherein the gate structure of the test transistor is adjacent to the transfer gate structure and is held at a high potential; and

[0011] an output port connected to the drain region of the test transistor and outputting a first current when the transfer gate structure is floating and outputting a second current when the transfer gate structure is at a low potential.

[0012] In an embodiment of the present application, the optoelectronic test structure includes a deep well region, the deep well region is disposed in the substrate, and the deep well region is located below the first type of well region and connected to the first type of well region, wherein a PN junction is formed at the interface between the deep well region and the first type of well region.

[0013] In an embodiment of the present application, the optoelectronic test structure includes a second type of well region, the second type of well region is disposed in the substrate, and the second type of well region is located above the deep well region and connected to the deep well region, wherein the second type of well region is adjacent to the first type of well region, and when the transfer gate structure is floating or at a low potential, the second type of well region is in communication with the deep well region, and isolates the first type of well region and the undoped region of the substrate, so that the first type of well region is in a floating state.

[0014] In an embodiment of the present application, the optoelectronic test structure includes a potential holding doped region, the potential holding doped region is disposed in the second type of well region, and the potential holding doped region is held at a high potential.

[0015] In an embodiment of the present application, the optoelectronic test structure includes a plurality of shallow trench isolation structures, and a portion of the shallow trench isolation structures are located in the first type of well region or the second type of well region, and another portion of the shallow trench isolation structures are located at the connecting interface of the first type of well region and the second type of well region and separate the doped region of the test transistor and the potential holding doped region.

[0016] In an embodiment of the present application, the depth of the shallow trench isolation structure in the substrate is less than the depth of the first type of well region in the substrate.

[0017] In an embodiment of the present application, the optoelectronic test structure includes a power supply end, the charge storage doped region is connected to the power supply end and held at a high potential.

[0018] In an embodiment of the utility model, the photoelectric test structure includes a photoelectric reaction area, the photoelectric reaction area is arranged in the first type trap area, and a PN junction is formed at the boundary of the photoelectric reaction area and the first type trap area, wherein the photoelectric reaction area is arranged on the deep trap area and is connected with the deep trap area.

[0019] In an embodiment of the utility model, the photoelectric test structure includes a test device, the test device is electrically connected to the output port, and the test device receives the first current and the second current and outputs the comparison result of the first current and the second current.

[0020] The utility model provides a kind of photoelectric test system, comprising:

[0021] wafer, the wafer includes test channel;And

[0022] A plurality of photoelectric test structures as described above, the photoelectric test structure is arranged on the wafer, and the photoelectric test structure is located in the test channel.

[0023] As described above, the utility model provides a kind of photoelectric test structure and system, without increasing new mask, based on the test machine platform of conventional wafer acceptable test can complete test, can obtain the functional test result of current chip before drawing test, quickly judge whether pixel unit exists GIDL white point problem, and test efficiency is high, to greatly reduce the time cost of research and development.

[0024] Of course, it is not necessary to achieve all the advantages described above while implementing any product of the utility model. BRIEF DESCRIPTION OF DRAWINGS

[0025] In order to more clearly illustrate the technical scheme of the embodiments of the utility model, the following will briefly introduce the drawings needed to be used in the embodiment description, and obviously, the drawings in the following description are only some embodiments of the utility model, and for those skilled in the art, other drawings can also be obtained according to these drawings without creative labor.

[0026] Figure 1 It is the structure schematic view of photoelectric test structure when transmission transistor is floated in an embodiment of the utility model.

[0027] Figure 2 It is the electronic distribution schematic view when transmission transistor is floated in an embodiment of the utility model.

[0028] Figure 3 It is the structure schematic view of photoelectric test structure when transmission transistor is cut off in an embodiment of the utility model.

[0029] Figure 4 It is the electronic and hole distribution schematic view when the transmission transistor is off in the embodiment of the utility model.

[0030] Figure 5 It is the structure schematic view of the photoelectric test system in the embodiment of the utility model.

[0031] In the figure: 100, substrate; 101, deep well region; 102, shallow trench isolation structure; 103, first type well region; 104, photoelectric reaction region; 105, charge storage doped region; 106, source region; 107, drain region; 108, second type well region; 109, potential holding doped region; 110, lightly doped region; 200, transmission gate structure; 300, test transistor; 301, gate oxide layer; 400, wafer; 401, test channel; 402, chip particle. DETAILED DESCRIPTION

[0032] The technical scheme in the embodiments of the utility model will be clearly and completely described in combination with the drawings in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by the person skilled in the art without creative labor belong to the protection scope of the utility model.

[0033] Please refer to Figure 1 As shown in the figure, the utility model provides a photoelectric test structure, photoelectric test structure includes substrate 100, charge storage doped region 105, transmission gate structure 200, test transistor 300 and output port. In this embodiment, the first type well region 103 is arranged in the substrate 100, and the doping ion type of the first type well region 103 and the substrate 100 is same. Charge storage doped region 105 is arranged in the first type well region 103, and PN junction is formed at the interface of charge storage doped region 105 and the first type well region 103. Transmission gate structure 200 is arranged on the substrate 100. Test transistor 300 includes source region 106, drain region 107 and test gate structure AT, wherein the source region 106 and the drain region 107 of test transistor 300 are arranged in the first type well region 103, and the test gate structure AT is arranged on the substrate 100. In this embodiment, the test gate structure AT is adjacent to the transmission gate structure 200, and the gate structure of test transistor 300 is kept at high potential. The output port is connected to the drain region 107 of test transistor 300, and the output port outputs the first current when the transmission gate structure 200 is in the floating state, and the output port outputs the second current when the transmission gate structure 200 is in the low potential.

[0034] Please refer to Figure 1As shown in the embodiment of the present application, the substrate 100 is, for example, a silicon base material for forming a semiconductor structure. The substrate 100 can include a base material, for example, a semiconductor substrate material such as silicon (Si), silicon carbide (SiC), sapphire (Al2O3), gallium arsenide (GaAs), lithium aluminate (LiAlO2), etc., and a silicon layer disposed above the base material. The silicon layer is formed above the base material. The present application does not limit the material and thickness of the substrate 100. When used for forming a semiconductor device, the substrate 100 can be an intrinsic semiconductor, or ions can be injected into the substrate 100 to form an N-type semiconductor or a P-type semiconductor. In the embodiment, the substrate 100 is a P-type semiconductor (P-sub). In the embodiment, the doping ions of the substrate 100 and the first-type well region 103 are trivalent ions, for example, boron ions. The present application does not limit the ion doping concentration of the substrate 100 and the first-type well region 103.

[0035] Referring to Figure 1 As shown in the embodiment of the present application, the optoelectronic test structure includes a deep well region 101. The deep well region 101 is disposed in the substrate 100, and the deep well region 101 is located below the first-type well region 103 and connected with the first-type well region 103, wherein a PN junction is formed at the interface between the deep well region 101 and the first-type well region 103. The doping ions of the deep well region 101 and the doping ions of the substrate 100 are mutually donor-acceptor, and the doping ions of the deep well region 101 and the doping ions of the first-type well region 103 are mutually donor-acceptor. In the embodiment, the doping ion type of the deep well region 101 is pentavalent ion, for example, phosphorus ion. When formed, ions can be first injected into the substrate 100 to form the deep well region 101, and then ions are injected into the substrate 100 to form the first-type well region 103.

[0036] Referring to Figure 1As shown in the embodiment of the present application, the optoelectronic test structure comprises a second type of well region 108, the second type of well region 108 is arranged in the substrate 100, and the second type of well region 108 is located above the deep well region 101 and connected with the deep well region 101. The second type of well region 108 is adjacent to the first type of well region 103. In the embodiment, the doping ions of the second type of well region 108 and the doping ions of the first type of well region 103 are in a donor-acceptor relationship. Specifically, the doping ions of the second type of well region 108 are pentavalent ions, such as phosphorus ions. In the embodiment, the second type of well region 108 is connected to the deep well region 101. After the holes are accumulated to a certain concentration, the holes will form a hole diffusion channel in the first type of well region 103. The second type of well region 108 can isolate the first type of well region 103 and the undoped substrate 100, wherein the undoped substrate 100 refers to the substrate region located below the deep well region 101. In the embodiment, the first type of well region 103 and the second type of well region 108 are adjacent and connected, and cover the substrate 100 region. When the ions are injected, the first type of well region 103 and the second type of well region 108 can be injected in sequence, and the present application does not limit the formation order of the first type of well region 103 and the second type of well region 108.

[0037] Referring to Figure 1 As shown in the embodiment of the present application, the optoelectronic test structure comprises a potential maintaining doping region, the potential maintaining doping region is arranged in the second type of well region 108, and the potential maintaining doping region is maintained at a high potential. In the embodiment, the potential maintaining doping region and the doping ion type of the second type of well region 108 are the same, and the potential maintaining doping region is located in the surface layer of the second type of well region 108. In the embodiment, the ions can be injected into the substrate 100 after the second type of well region 108 is formed to form the potential maintaining doping region.

[0038] Referring to Figure 1As shown in the embodiment of the present application, the photoelectric test structure comprises a photoelectric reaction region 104, which is arranged in the first type of well region 103, and a PN junction is formed at the interface between the photoelectric reaction region 104 and the first type of well region 103. The photoelectric reaction region 104 is arranged on the deep well region 101 and connected with the deep well region 101. In the embodiment, the photoelectric reaction region 104 can effectively respond to the light signal and convert it into an electrical signal under the exposure environment. In the embodiment, the surface of the photoelectric reaction region 104 is specially treated to enhance the absorption of light of a specific wavelength, for example, a lightly doped region 110 is arranged in the substrate 100, wherein the lightly doped region 110 partially or wholly overlaps with the photoelectric reaction region 104, and the doped ions of the lightly doped region 110 and the photoelectric reaction region 104 are in a donor-acceptor relationship. The lightly doped region 110 is connected with the transfer gate structure 200. In the embodiment, the doped ions of the photoelectric reaction region 104 are, for example, pentavalent ions such as phosphorus ions. The doped ions of the lightly doped region 110 are, for example, trivalent ions such as boron ions. The PN junction between the photoelectric reaction region 104 and the first type of well region 103 helps to separate the photo-generated carriers and reduce recombination, thereby further improving the photoelectric conversion efficiency. The performance of the photoelectric reaction region 104 can be finely adjusted to adapt to different test and light conversion requirements by precisely controlling the doping concentration and depth of the PN junction, and the present application does not limit this.

[0039] Please refer to Figure 1 As shown in the embodiment of the present application, the first end of the transfer gate structure 200 is arranged on the first type of well region 103, and the first end of the transfer gate structure 200 is located on one side of the charge storage doped region 105. The second end of the transfer gate structure 200 extends to the surface of the photoelectric reaction region 104, and the gate channel of the transfer gate structure 200 is arranged between the photoelectric reaction region 104 and the charge storage doped region 105, thereby forming a transfer transistor TG. In the exposure environment, the transfer gate structure 200 is at a low potential, so the transfer transistor TG is in a cut-off state. After the exposure is completed, the transfer gate structure 200 can be set to a high potential, so that the transfer transistor TG is turned on, the charges of the photoelectric reaction region 104 are moved into the charge storage doped region 105, and then the charges are output in the form of voltage through a 3T pixel structure or a 4T pixel structure formed by a source follower (SF) and a select transistor (SEL). The present application does not limit the pixel structure in which the photoelectric reaction region 104 is located. The test transistor 300 of the photoelectric test structure only works in a non-exposure environment. Specifically, when the photoelectric reaction region 104 is in a non-exposure state, the output port outputs the first current and the second current.

[0040] Please refer to Figure 1As shown in an embodiment of the present application, the optoelectronic test structure includes a plurality of shallow trench isolation structures 102, which are disposed in the substrate 100. In this embodiment, the plurality of shallow trench isolation structures 102 can be divided into first shallow trench isolation structures 102 and second shallow trench isolation structures 102 according to their positions. The first shallow trench isolation structures 102 are located in the first type well region 103 or the second type well region 108. The shallow trench isolation structures 102 located in the first type well region 103 separate the charge storage doped region 105 and the source region 106 of the test transistor 300. In this embodiment, the shallow trench isolation structures 102 can be formed after the deep well region 101, and the first type well region 103 and the second type well region 108 can be formed after the shallow trench isolation structures 102. Then, the charge storage doped region 105, the source region 106 and the drain region 107 of the test transistor 300, and the potential holding doped region 108, the optoelectronic reaction region 104 and the lightly doped region 110 are formed. The shallow trench isolation structures 102 located in the second type well region 108 are used to isolate the potential holding doped region 108 and another optoelectronic test structure. For example, the shallow trench isolation structures 102 separate the potential holding doped region 108 and the optoelectronic reaction region 104 of another optoelectronic test structure. In this embodiment, the second shallow trench isolation structure 102 is located at the connecting interface position of the first type well region 103 and the second type well region 108, and is used to separate the drain region 107 of the test transistor 300 and the potential holding doped region.

[0041] Please refer to Figure 1 As shown in an embodiment of the present application, Figure 1 As shown, only a single test transistor 300 and a transfer gate structure 200 are shown. In practice, a plurality of test transistors 300 and gate structures can be distributed on the substrate 100. The depth of the shallow trench isolation structure 102 in the substrate 100 is less than the depth of the first type well region 103 in the substrate 100. In this embodiment, the shallow trench isolation structure 102 is disposed in the substrate 100 and separates the substrate 100 into a plurality of active regions. In this embodiment, an optoelectronic test structure includes, for example, a first active region, a second active region and a third active region. The first active region is formed between two first shallow trench isolation structures 102, and is formed between two first shallow trench isolation structures 102 located in the first type well region. The optoelectronic reaction region 104, the charge storage doped region 105 and the lightly doped region 110 are disposed in the first active region. The source region 106 and the drain region 107 of the test transistor 300 are disposed in the second active region. The potential holding doped region 108 is disposed in the third active region.

[0042] Please refer to Figure 1As shown in the embodiment of the utility model, the photoelectric test structure includes an output port, a first input end and a second input end, a photoelectric output end and a source end, and a potential holding end N_ISO. The first input end is connected to the transmission gate structure 200. The second input end is connected to the test gate structure AT and inputs a constant high voltage, for example, 2V, to the test gate structure AT, so that the test transistor 300 is in a saturated working zone. In the embodiment, the photoelectric output end is connected to the charge storage doped region 105 for outputting the accumulated charge of the charge storage doped region 105. The photoelectric output end can be connected to the power supply end Vdd to maintain a high potential. In other embodiments of the utility model, the photoelectric output end can continue to be connected to a source follower transistor and a selection transistor, etc. The source end is connected to the source region 106, and the output port is connected to the drain region 107. The potential holding end N_ISO is maintained at a high potential, for example, 2V, so as to maintain the potential holding doped region 109 in a high potential state, so as to isolate the first type well region 103 and the undoped region of the substrate 100, and make the first type well region 103 in a floating state. It should be noted that the substrate 100 itself is a P-type semiconductor, and the undoped region of the substrate 100 refers to a region which is not additionally ion doped on the basis of the P-type semiconductor. In the embodiment, the undoped region of the substrate 100 can be a region of the substrate 100 which is connected to the deep well region 101 and located on the side opposite to the first type well region 103 with respect to the deep well region 101. The utility model does not show a port lead-out line. The port lead-out line can be embodied as a metal plug structure (CT) in the semiconductor structure.

[0043] Please refer to Figure 1 As shown in the embodiment of the utility model, when the first input end is connected to the power supply end Vdd, the transmission gate structure 200 is at a high potential, at this time, the photoelectric reaction region 104 and the charge storage doped region 105 are in communication, and the accumulated charge after exposure can be transported. As shown in the embodiment of the utility model, Figures 1 to 4 and Figure 1 As shown, when the first input end is floating, the transmission gate structure 200 is in a floating state, the photoelectric reaction region 104, the deep well region 101 and the second type well region 108 isolate the first type well region 103 from the undoped substrate 100, so that the first type well region 103 is in a floating state. The source region 106 and the drain region 107 of the test transistor 300 are connected to a higher voltage with respect to the first type well region 103, and the voltage difference between the gate voltage, the source voltage and the drain voltage of the test transistor 300 remains unchanged. At this time, the current output by the output port is the first current. As shown in the embodiment of the utility model, Figure 2 and Figure 3As shown, in order to simulate the exposure state of the image sensor, the gate voltage of the transfer transistor TG is, for example, -1V, at which the transfer transistor TG is closed. At this time, the photoelectric output end is kept at a high potential. The electrons and holes in the overlapping area of the transfer transistor TG and the photoelectric output end are separated due to the strong electric field, the electrons flow to the charge storage doped region 105, and at this time, the equivalent holes do not flow to the undoped substrate 100 because the first-type well region 103 is in a floating state, the holes gather in the first-type well region 103 on the side of the transfer transistor TG, and thus the hole concentration is increased, the holes diffuse to the first-type well region 103 on the side of the test transistor 300 due to the concentration gradient, the potential of the first-type well region 103 on the side of the test transistor 300 is increased, the potential difference between the test gate structure AT and the first-type well region 103 is reduced, the conductive channel is narrowed, and thus the drain current is reduced. Figure 4 and Figure 3 The gate oxide layer 301 of the test gate structure AT and part of the first-type well region 103 are shown in FIG. 3. At this time, the output port outputs the second current. It should be noted that the overlapping area of the transfer transistor TG and the photoelectric output end refers to the part of the PN junction depletion region formed by the charge storage doped region 105 and the first-type well region 103 extending to the area below the transfer gate structure 200. In the GIDL effect, the drain depletion region below the gate structure is called the gate-drain overlapping area, and the electron-hole pairs in the gate-drain overlapping area are separated by the strong electric field caused by the high voltage on the transfer gate transistor TG and the charge storage doped region 105.

[0044] Please refer to Figure 4 Figures 1 to 5 As shown in FIG. 4, in an embodiment of the present application, the present application further provides a photoelectric test system, which comprises a wafer 400 and a plurality of photoelectric test structures. The wafer 400 comprises a plurality of test channels 401, which are distributed in parallel on the surface of the wafer 400. In this embodiment, the substrate 100 can be a surface silicon layer of the wafer 400 or an epitaxial layer grown on the wafer 400. In this embodiment, the photoelectric test structure is arranged on the wafer 400, and the photoelectric test structure is arranged in the test channel. In this embodiment, a plurality of chip particles 402 are arranged on the wafer 400, and the chip particle 402 comprises the transfer gate structure 200, the charge storage doped region 105 and the photoelectric reaction region 104. In this embodiment, the photoelectric test system further comprises a test device. The test device is electrically connected to the output port and receives the first current and the second current. The test device can be a differential operational amplifier circuit to output the difference between the first current and the second current. The test device can also be a comparator to compare whether there is a change between the first current and the second current, and determine whether the current chip particle 402 has a leakage current and whether the white spot condition will occur later according to the current change.

[0045] The above disclosed embodiments of the utility model are only used for helping the utility model to be described. The embodiments do not describe all the details, and also do not limit the utility model to be the specific implementation mode. Apparently, according to the content of the specification, many modifications and changes can be made. The specification selects and specifically describes these embodiments, in order to better explain the principle and practical application of the utility model, so that the person skilled in the art can well understand and utilize the utility model. The utility model is limited by the claims and the whole range and equivalents.

Claims

1. An optoelectronic test structure, characterized by include: A substrate, wherein a first type of well region is provided in the substrate, and the first type of well region and the substrate are doped with the same type of ions; A charge storage doped region is disposed in the first type-well region, wherein a PN junction is formed at the interface between the charge storage doped region and the first type-well region; A transfer gate structure is disposed on the substrate, wherein a first end of the transfer gate structure is located on the first type well region and is located on one side of the charge storage doped region; A test transistor, wherein the source region and drain region of the test transistor are disposed in the first type of well region, and the gate structure of the test transistor is disposed on the substrate, wherein the gate structure of the test transistor is adjacent to the transmission gate structure, and the gate structure of the test transistor is maintained at a high potential. as well as The output port is connected to the drain region of the test transistor and outputs a first current when the transmission gate structure is in a floating state and a second current when the transmission gate structure is at a low potential.

2. The optoelectronic test structure of claim 1, wherein, The optoelectronic testing structure includes a deep well region disposed in the substrate. The deep well region is located below and connected to the first type of well region, wherein a PN junction is formed at the interface between the deep well region and the first type of well region.

3. The optoelectronic test structure of claim 2, wherein, The optoelectronic testing structure includes a second type of well region disposed in the substrate. The second type of well region is located on and connected to the deep well region. The second type of well region is adjacent to the first type of well region. When the transmission gate structure is floating or at a low potential, the second type of well region is connected to the deep well region and isolates the first type of well region from the undoped region of the substrate, so that the first type of well region is in a floating state.

4. The optoelectronic test structure of claim 3, wherein, The optoelectronic test junction structure includes a potential-maintaining doped region disposed in the second type of well region, wherein the potential-maintaining doped region is maintained at a high potential.

5. An optoelectronic test structure according to claim 4, wherein, The optoelectronic testing structure includes multiple shallow trench isolation structures disposed in the substrate. A portion of the shallow trench isolation structures are located in the first type of well region or the second type of well region, while another portion of the shallow trench isolation structures are located at the connection interface between the first type of well region and the second type of well region, separating the doped region of the test transistor from the potential-holding doped region.

6. The optoelectronic test structure of claim 5, wherein, The shallow trench isolation structure is less deep in the substrate than the first type of well region is in the substrate.

7. The optoelectronic test structure of claim 1, wherein, The photoelectric testing structure includes a power supply terminal, and the charge storage doped region is connected to the power supply terminal and maintained at a high potential.

8. The optoelectronic test structure of claim 2, wherein, The photoelectric testing structure includes a photoelectric reaction region disposed in the first type of well region, and a PN junction is formed at the interface between the photoelectric reaction region and the first type of well region. The photoelectric reaction region is disposed on the deep well region and connected to the deep well region.

9. The optoelectronic test structure of claim 1, wherein, The photoelectric testing structure includes a testing device electrically connected to the output port, which receives the first current and the second current and outputs a comparison result of the first current and the second current.

10. An optoelectronic test system, characterized by include: Wafer, the wafer including a test channel; as well as A plurality of optoelectronic test structures as claimed in any one of claims 1 to 9, said optoelectronic test structures being arranged on said wafer and said optoelectronic test structures being located in said test trenches.

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