Clamping circuit, module and integrated circuit

Abstract

The utility model discloses a clamping circuit, a module and an integrated circuit, the clamping circuit comprises a voltage delay unit, a reverse shaping unit and a voltage release unit, the voltage delay unit is connected with a power supply, the reverse shaping unit and a grounding end, the reverse shaping unit is connected with the power supply, the voltage release unit and the grounding end, and the voltage release unit is connected with the power supply. The voltage release unit is connected with the power supply and the grounding end; the voltage delay unit is used for delaying and caching an EOS voltage and converting the EOS voltage into a charging voltage when the power supply outputs the EOS voltage; the reverse shaping unit is used for starting the voltage release unit when the charging voltage reaches a preset value; and the voltage release unit is used for releasing the EOS voltage to the grounding end after being started. The breakdown voltage of the TVS tube in the integrated circuit provided with the clamping circuit can be smaller than that of the clamping circuit, so that the model selection difficulty of the TVS tube in the integrated circuit is reduced.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, specifically to a clamping circuit, module, and integrated circuit. Background Technology

[0002] Currently, in integrated circuits, the power supply is typically connected to a TVS diode and a clamping circuit. The TVS diode and the clamping circuit are connected in parallel. When the power supply generates an EOS voltage, the EOS voltage is first released through the TVS diode and the device with the lower breakdown voltage in the clamping circuit. Therefore, to ensure that the integrated circuit has a high EOS voltage withstand capability, the TVS diode needs to be able to release the EOS voltage first. This leads to the requirement that existing integrated circuits generally need to select TVS diodes with lower breakdown voltages, resulting in a difficulty in selecting the right TVS diode for current integrated circuits. Utility Model Content

[0003] In view of this, this application provides a clamping circuit, module, and integrated circuit, which enables the breakdown voltage of the TVS diode in the integrated circuit equipped with the clamping circuit of this application to be less than that of the clamping circuit, thereby reducing the difficulty of selecting the TVS diode in the integrated circuit. The technical solution of this application is as follows:

[0004] The first aspect of this application provides a clamping circuit, including a voltage delay unit, a reverse shaping unit, and a voltage release unit. The voltage delay unit is connected to a power supply, the reverse shaping unit, and a ground terminal. The reverse shaping unit is connected to the power supply, the voltage release unit, and the ground terminal. The voltage release unit is connected to the power supply and the ground terminal. The voltage delay unit is used to delay and buffer the EOS voltage when the power supply outputs an EOS voltage, and convert the EOS voltage into a charging voltage. The reverse shaping unit is used to activate the voltage release unit when the charging voltage reaches a preset value. The voltage release unit is used to release the EOS voltage to the ground terminal after activation.

[0005] In one embodiment of this application, the voltage release unit includes a first switch and a second switch; the control terminals of the first switch and the second switch are connected to the reverse shaping unit, the first terminal of the first switch is connected to the power supply, the second terminal of the first switch is connected to the first terminal of the second switch, and the second terminal of the second switch is connected to the ground terminal.

[0006] In one embodiment of this application, the voltage release unit includes a first switching transistor and n first diodes, where n is a positive integer greater than or equal to 1; the control terminal of the first switching transistor is connected to the reverse shaping unit, the first terminal of the first switching transistor is connected to the power supply, and the second terminal of the first switching transistor is connected in series with the forward direction of the n first diodes to the ground terminal.

[0007] In one embodiment of this application, the voltage release unit includes a first switching transistor and m thyristors, where m is a positive integer greater than or equal to 1; the control terminal of the first switching transistor is connected to the reverse shaping unit, the first terminal of the first switching transistor is connected to the power supply, and the second terminal of the first switching transistor is connected in series with the m thyristors to the ground terminal.

[0008] In one embodiment of this application, the voltage release unit further includes a first reverse diode, the negative terminal of which is connected to the first terminal of the first switching transistor, and the positive terminal of which is connected to the ground terminal.

[0009] In one embodiment of this application, the voltage delay unit includes a resistor and a capacitor. The first end of the resistor is connected to the power supply, and the second end of the resistor is connected to the first end of the capacitor and the reverse shaping unit. The second end of the capacitor is grounded.

[0010] In one embodiment of this application, the reverse shaping unit includes a third switch and a fourth switch; the control terminals of the third switch and the fourth switch are connected to the voltage delay unit, the first terminal of the third switch is connected to the power supply, the second terminal of the third switch is connected to the first terminal of the fourth switch and the voltage release unit, and the second terminal of the fourth switch is connected to the ground terminal.

[0011] In one embodiment of this application, the reverse shaping unit further includes a fifth switch and a sixth switch; the control terminals of the fifth switch and the sixth switch are connected to the second terminal of the third switch, the first terminal of the fifth switch is connected to the power supply, the second terminal of the fifth switch is connected to the first terminal of the sixth switch and the voltage release unit, and the second terminal of the sixth switch is connected to the ground terminal.

[0012] A second aspect of this application provides a clamping module, including i clamping circuits, where i is a positive integer greater than or equal to 1; the i clamping circuits are connected in series and then respectively connected to the power supply and the ground terminal.

[0013] In one embodiment of this application, the clamping module further includes a second reverse diode, the positive terminal of which is connected to a ground terminal, and the second reverse diode is connected in parallel with i clamping circuits.

[0014] A third aspect of this application provides an integrated circuit, including a power supply, a TVS diode, and a clamping module, wherein the power supply is connected to a ground terminal through the clamping module, and the TVS diode is connected in parallel with the clamping module.

[0015] It is understood that when the clamping circuit of this application generates an EOS voltage through the power supply it is connected to, it first delays and buffers the EOS voltage through a voltage delay unit and converts the EOS voltage into a charging voltage. When the reverse shaping unit detects that the charging voltage has reached a preset voltage, it then activates the voltage release unit to release the EOS voltage of the power supply to the ground terminal. This can improve the clamping circuit's ability to withstand EOS voltage and increase the clamping circuit's own breakdown voltage. This allows the breakdown voltage of the TVS diode in the integrated circuit equipped with the clamping circuit of this application to be less than that of the clamping circuit, thereby reducing the difficulty of selecting the TVS diode in the integrated circuit. Attached Figure Description

[0016] Figure 1 This is a schematic block diagram of a clamping circuit provided in an embodiment of this application.

[0017] Figure 2 This is a circuit diagram of a clamping circuit provided in an embodiment of this application.

[0018] Figure 3 This is a circuit diagram of the second clamping circuit provided in the embodiments of this application.

[0019] Figure 4 This is a circuit diagram of the third clamping circuit provided in the embodiments of this application.

[0020] Figure 5 This is a circuit diagram of the fourth clamping circuit provided in the embodiments of this application.

[0021] Figure 6 This is a circuit diagram of one of the clamping modules provided in the embodiments of this application.

[0022] Figure 7 This is a circuit diagram of another clamping module provided in an embodiment of this application.

[0023] Figure 8 This is a schematic block diagram of an integrated circuit provided in an embodiment of this application. Detailed Implementation

[0024] It should be noted that in the embodiments of this application, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone, where A and B can be singular or plural. The terms "first," "second," "third," "fourth," etc. (if present) in the specification, claims, and drawings of this application are used to distinguish similar objects, not to describe a specific order or sequence.

[0025] It should also be noted that the methods disclosed in the embodiments of this application or the methods shown in the flowcharts include one or more steps for implementing the method. Without departing from the scope of the claims, the execution order of multiple steps can be interchanged, and some steps can also be deleted.

[0026] Currently, in integrated circuits, the power supply is typically connected to a TVS diode and a clamping circuit. The TVS diode and the clamping circuit are connected in parallel. When the power supply generates an EOS voltage, the EOS voltage is first released through the TVS diode and the device with the lower breakdown voltage in the clamping circuit. Therefore, to ensure that the integrated circuit has a high EOS voltage withstand capability, the TVS diode needs to be able to release the EOS voltage first. This leads to the requirement that existing integrated circuits generally need to select TVS diodes with lower breakdown voltages, resulting in a difficulty in selecting the right TVS diode for current integrated circuits.

[0027] This application provides a clamping circuit, module, and integrated circuit, which enables the breakdown voltage of the TVS transistor in the integrated circuit equipped with the clamping circuit of this application to be less than that of the clamping circuit, thereby reducing the difficulty of selecting the TVS transistor in the integrated circuit.

[0028] Please refer to Figure 1 , Figure 1 This is a schematic block diagram of a clamping circuit provided in an embodiment of the present application. The clamping circuit 100 includes a voltage delay unit 110, a reverse shaping unit 120, and a voltage release unit 130.

[0029] In this embodiment, the voltage delay unit 110 is connected to the power supply, the reverse shaping unit 120 and the ground terminal GND, the reverse shaping unit 120 is connected to the power supply, the voltage release unit 130 and the ground terminal GND, and the voltage release unit 130 is connected to the power supply and the ground terminal GND.

[0030] The voltage delay unit 110 is used to delay and buffer the EOS (Electrical Over Stress) voltage when the power supply outputs it, and converts the EOS voltage into a charging voltage. The reverse shaping unit 120 is used to activate the voltage release unit 130 when the charging voltage reaches a preset value. The voltage release unit 130 is used to release the EOS voltage to the ground terminal GND after activation. In this embodiment, the clamping circuit 100 can be applied to an integrated circuit, and the power supply is the power supply in the integrated circuit. The EOS voltage is a transient voltage surge exceeding the design voltage experienced by the integrated circuit during use.

[0031] It is understood that when the clamping circuit 100 of this application generates an EOS voltage through its connected power supply, it first delays and buffers the EOS voltage through the voltage delay unit 110 and converts the EOS voltage into a charging voltage. When the reverse shaping unit 120 detects that the charging voltage has reached a preset voltage, it then activates the voltage release unit 130 to release the EOS voltage of the power supply to the ground terminal GND. This can improve the clamping circuit 100's ability to withstand EOS voltage and increase the clamping circuit 100's own breakdown voltage. This allows the breakdown voltage of the TVS transistor in the integrated circuit equipped with the clamping circuit 100 of this application to be less than that of the clamping circuit 100, thereby reducing the difficulty of selecting the TVS transistor (TVS, Transient Voltage Suppressor) in the integrated circuit.

[0032] Please refer to Figure 2 , Figure 2 The present application provides a circuit diagram of a clamping circuit 100, wherein the clamping circuit 100 includes a voltage delay unit 110, a reverse shaping unit 120, and a voltage release unit 130.

[0033] In this embodiment, the voltage release unit 130 includes a first switch Q1 and a second switch Q2. The control terminals of the first switch Q1 and the second switch Q2 are connected to the reverse shaping unit 120. The first terminal of the first switch Q1 is connected to the power supply 11, the second terminal of the first switch Q1 is connected to the first terminal of the second switch Q2, and the second terminal of the second switch Q2 is connected to the ground terminal GND.

[0034] It is understood that, by using the first switch Q1 and the second switch Q2 connected in series in the voltage release unit 130, the breakdown voltage of the clamping circuit 100 can be doubled compared to a structure with only one switch, thereby improving the EOS voltage withstand capability of the clamping circuit 100. In some embodiments, the voltage release unit 130 may also have multiple switches connected in series to further increase the breakdown voltage of the clamping circuit 100, thereby further improving the EOS voltage withstand capability of the clamping circuit 100.

[0035] The voltage delay unit 110 includes a resistor R1 and a capacitor C1. The first end of the resistor R1 is connected to the power supply 11, and the second end of the resistor R1 is connected to the first end of the capacitor C1 and the reverse shaping unit 120. The second end of the capacitor C1 is grounded.

[0036] In this embodiment, the voltage delay unit 110 sets up an RC circuit structure with resistor R1 and capacitor C1 connected in series. After receiving the EOS voltage from the power supply 11, it delays the EOS voltage through the RC circuit structure and receives the EOS voltage through capacitor C1 for charging and buffering, thereby preventing instantaneous voltage spikes from breaking down the clamping circuit 100 and improving the EOS voltage withstand capability of the clamping circuit 100.

[0037] The reverse shaping unit 120 includes a third switch Q3 and a fourth switch Q4. The control terminals of the third switch Q3 and the fourth switch Q4 are connected to the voltage delay unit 110. The first terminal of the third switch Q3 is connected to the power supply 11. The second terminal of the third switch Q3 is connected to the first terminal of the fourth switch Q4 and the voltage release unit 130. The second terminal of the fourth switch Q4 is connected to the ground terminal GND.

[0038] In this embodiment, when the power supply voltage increases, the gate voltages of the third switch Q3 and the fourth switch Q4 remain at a lower level for a period of time due to the delay unit 110 delaying the EOS voltage. The drains of the third switch Q3 and the fourth switch Q4 output a high level, while the gates of the first switch Q1 and the second switch Q2 of the voltage release unit 130 are at a high level. The voltage release unit 130 is in the ON state, and the duration of the ON state is determined by R1*C2 of the voltage delay unit 110. After the voltage release unit 130 is turned on, the power supply voltage decreases, thus clamping the power supply voltage. If the voltage release unit 130 consists only of the first switch Q1, the first switch Q1 will burn out before the voltage delay unit 110 and the reverse shaping unit 120 operate when the power supply voltage increases above its breakdown voltage. After the first switch Q1 and the second switch Q2 are connected in series, the breakdown voltage of the voltage release unit 130 doubles, and the EOS withstand voltage doubles.

[0039] In some embodiments, such as Figure 3 As shown, the aforementioned reverse shaping unit 120 also includes a fifth switch Q5 and a sixth switch Q6. The control terminals of the fifth switch Q5 and the sixth switch Q6 are connected to the second terminal of the third switch Q3. The first terminal of the fifth switch Q5 is connected to the power supply 11. The second terminal of the fifth switch Q5 is connected to the first terminal of the sixth switch Q6 and the voltage release unit 130. The second terminal of the sixth switch Q6 is connected to the ground terminal GND.

[0040] It can be understood that the third switch Q3 and the fourth switch Q4 of the reverse shaping unit 120 constitute the first-stage switching circuit, while the fifth switch Q5 and the sixth switch Q6 constitute the second-stage switching circuit. By receiving the EOS voltage from the power supply 11 through the second-stage switching circuit, the breakdown voltage of the clamping circuit 100 and the EOS voltage withstand capability of the clamping circuit 100 can be further improved.

[0041] In some embodiments, the reverse shaping unit 120 may also be provided with a multi-stage switching circuit, which is not limited here.

[0042] Please refer to Figure 4 , Figure 4 A circuit diagram of the third clamping circuit 100 provided in the embodiments of this application is shown below. Figure 2 Compared to the clamping circuit 100 shown, Figure 4 The voltage release unit 130 of the clamping circuit 100 shown includes a first switching transistor Q1 and n first diodes D1, where n is a positive integer greater than or equal to 1.

[0043] In this embodiment, the control terminal of the first switching transistor Q1 is connected to the reverse shaping unit 120, the first terminal of the first switching transistor Q1 is connected to the power supply 11, and the second terminal of the first switching transistor is connected in series with the forward direction of n first diodes D1 to the ground terminal GND.

[0044] It can be understood that the voltage release unit 130 improves the breakdown voltage of the clamping circuit 100 through n series-connected first diodes D1. The larger n is, the larger the breakdown voltage is. Compared with the structure with only one switching transistor, the breakdown voltage of the clamping circuit 100 can be increased by n*A volts, where A is the breakdown voltage value of the first diode D1, for example, it can be 0.7 volts.

[0045] In some embodiments, the voltage release unit 130 of the clamping circuit 100 may further include a first switching transistor Q1 and m thyristors, where m is a positive integer greater than or equal to 1.

[0046] In this embodiment, the control terminal of the first switching transistor Q1 is connected to the reverse shaping unit 120, the first terminal of the first switching transistor Q1 is connected to the power supply 11, and the second terminal of the first switching transistor is connected in series with m thyristors to the ground terminal GND.

[0047] It is understood that the voltage release unit 130 improves the breakdown voltage of the clamping circuit 100 by using m series-connected silicon controlled rectifiers (SCRs) 1. The larger m is, the larger the breakdown voltage is. Compared with the structure with only one switching transistor, the breakdown voltage of the clamping circuit 100 can be increased by m*B volts, where B is the breakdown voltage value of the silicon controlled rectifier (SCR) 1, for example, it can be 1.4 volts.

[0048] Please refer to Figure 5 , Figure 5 A circuit diagram of the fourth clamping circuit 100 provided in the embodiments of this application is shown below. Figure 2 Compared to the clamping circuit 100 shown, Figure 5 The voltage release unit 130 shown also includes a first reverse diode D2.

[0049] In this embodiment, the negative terminal of the first reverse diode D2 is connected to the first terminal of the first switching transistor Q1, and the positive terminal of the first reverse diode is connected to the ground terminal GND.

[0050] It is understandable that the aforementioned first reverse diode D2 can also be set in the same manner. Figure 3 , Figure 4 as well as Figure 5 The clamping circuit 100 shown is designed to enhance the reverse electrostatic discharge capability of the power supply 11 to the ground terminal GND.

[0051] In this embodiment, the first switch Q1 and the second switch Q2 are N-type MOSFETs, with their first terminals being drains and their second terminals being sources. The third switch Q3 and the fifth switch Q5 are P-type MOSFETs, with their first terminals being drains and their second terminals being sources. The fourth switch Q4 and the sixth switch Q6 are N-type MOSFETs, with their first terminals being drains and their second terminals being sources.

[0052] This application embodiment also provides a clamping module, wherein the clamping module 10 includes i units. Figures 1 to 5 The clamping circuit 100 shown is an example where i is a positive integer greater than or equal to 1. i clamping circuits 100 are connected in series and then connected to the power supply 11 and the ground terminal GND, respectively. Figure 2 The clamping circuit 100 shown is connected in series as an example; please refer to [reference needed]. Figure 6 The circuit diagram of one type of clamping module 10 is shown (example i in the figure is 2).

[0053] It is understandable that by setting i clamping circuits 100 in series and connecting them to the power supply 11 and the ground terminal GND respectively, the breakdown voltage of the clamping module 10 can be made to be the sum of the breakdown voltages of the i clamping circuits 100, thereby improving the clamping module 10's ability to withstand EOS voltage.

[0054] In some embodiments, the clamping module 10 further includes a second reverse diode D3, the positive terminal of which is connected to ground GND, and the second reverse diode D3 is connected in parallel with the clamping circuit 100. Figure 2 The clamping circuit 100 shown is connected in series as an example; please refer to [reference needed]. Figure 7 The circuit diagram of another clamping module 10 is shown (example i in the figure is 2).

[0055] It can be understood that the clamping module 10 is connected in parallel with the i clamping circuits 100 through the second reverse diode D3, so that the clamping module 10 can also enhance the reverse electrostatic discharge capability from the power supply 11 to the ground terminal GND.

[0056] Please refer to Figure 8 , Figure 8 This is a schematic block diagram of an integrated circuit provided in an embodiment of this application. The integrated circuit 1 includes a power supply 11, a TVS diode 12, and a clamping module 10 from any of the above embodiments.

[0057] In this embodiment, the power supply 11 is connected to the ground terminal GND through the clamping module 10, and the TVS diode 12 is connected in parallel with the clamping module 10. It is understood that the beneficial effects achieved by the integrated circuit 1 can be referenced from the beneficial effects of the clamping circuit 100 in the aforementioned embodiments, and will not be repeated here.

[0058] The embodiments described above are merely preferred embodiments of this application and are not intended to limit the scope of this application. Any modifications and improvements made by those skilled in the art to the technical solutions of this application without departing from the spirit of this application should fall within the protection scope defined by the claims of this application.

Claims

1. A clamping circuit, characterized in that, It includes a voltage delay unit, a reverse shaping unit, and a voltage release unit. The voltage delay unit is connected to a power supply, the reverse shaping unit, and a ground terminal. The reverse shaping unit is connected to the power supply, the voltage release unit, and the ground terminal. The voltage release unit is connected to the power supply and the ground terminal. The voltage delay unit is used to delay and buffer the EOS voltage when the power supply outputs the EOS voltage, and convert the EOS voltage into a charging voltage; The reverse shaping unit is used to activate the voltage release unit when the charging voltage reaches a preset value. The voltage release unit is used to release the EOS voltage to the ground terminal after startup.

2. The clamping circuit as described in claim 1, characterized in that, The voltage release unit includes a first switching transistor and a second switching transistor; The control terminals of the first and second switching transistors are connected to the reverse shaping unit. The first terminal of the first switching transistor is connected to the power supply. The second terminal of the first switching transistor is connected to the first terminal of the second switching transistor. The second terminal of the second switching transistor is connected to the ground terminal.

3. The clamping circuit as described in claim 1, characterized in that, The voltage release unit includes a first switching transistor and n first diodes, where n is a positive integer greater than or equal to 1; The control terminal of the first switching transistor is connected to the reverse shaping unit, the first terminal of the first switching transistor is connected to the power supply, and the second terminal of the first switching transistor is connected in series with the forward direction of n first diodes to the ground terminal.

4. The clamping circuit as described in claim 1, characterized in that, The voltage release unit includes a first switching transistor and m thyristors, where m is a positive integer greater than or equal to 1; The control terminal of the first switching transistor is connected to the reverse shaping unit, the first terminal of the first switching transistor is connected to the power supply, and the second terminal of the first switching transistor is connected in series with m of the thyristors to the ground terminal.

5. The clamping circuit as described in any one of claims 2 to 4, characterized in that, The voltage release unit further includes a first reverse diode, the negative terminal of which is connected to the first terminal of the first switching transistor, and the positive terminal of which is connected to the ground terminal.

6. The clamping circuit as described in claim 1, characterized in that, The voltage delay unit includes a resistor and a capacitor. The first end of the resistor is connected to the power supply, and the second end of the resistor is connected to the first end of the capacitor and the reverse shaping unit. The second end of the capacitor is grounded.

7. The clamping circuit as described in claim 1, characterized in that, The reverse shaping unit includes a third switch and a fourth switch; The control terminals of the third and fourth switching transistors are connected to the voltage delay unit. The first terminal of the third switching transistor is connected to the power supply. The second terminal of the third switching transistor is connected to the first terminal of the fourth switching transistor and the voltage release unit. The second terminal of the fourth switching transistor is connected to the ground terminal.

8. The clamping circuit as described in claim 7, characterized in that, The reverse shaping unit also includes a fifth switching transistor and a sixth switching transistor; The control terminals of the fifth and sixth switching transistors are connected to the second terminal of the third switching transistor. The first terminal of the fifth switching transistor is connected to the power supply. The second terminal of the fifth switching transistor is connected to the first terminal of the sixth switching transistor and the voltage release unit. The second terminal of the sixth switching transistor is connected to the ground terminal.

9. A clamping module, characterized in that, Includes i clamping circuits as described in any one of claims 1 to 8, where i is a positive integer greater than or equal to 1; The i clamping circuits are connected in series and then connected to the power supply and ground terminal respectively.

10. The clamping module as described in claim 9, characterized in that, The clamping module further includes a second reverse diode, the positive terminal of which is connected to the ground terminal, and the second reverse diode is connected in parallel with i clamping circuits.

11. An integrated circuit, characterized in that, It includes a power supply, a TVS diode, and a clamping module as described in claim 9 or 10, wherein the power supply is connected to a ground terminal through the clamping module, and the TVS diode is connected in parallel with the clamping module.

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