Gate drive circuit of array substrate, array substrate and display

Abstract

The utility model discloses a gate drive circuit of an array substrate, the array substrate and a display, the array substrate comprises a front plate wiring area, and the gate drive circuit comprises a main level unit, a redundancy unit and a compensation capacitor unit; the main stage unit is connected with a gate line of the front plate wiring area, the redundancy unit is connected with the main stage unit, a positive electrode end of the compensation capacitor unit is connected with an output node of the redundancy unit, and a negative electrode end of the compensation capacitor unit is connected with a grounding end of the gate drive circuit; the main stage unit is used for driving the gate lines; the redundancy unit is used for driving the gate line when the main level unit fails; the compensation capacitor unit is used for compensating the first load of the redundancy unit to a target load, and the target load is a second load of the output node of the main level unit. The performance of the gate drive circuit can be improved.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a gate driving circuit for an array substrate, an array substrate, and a display. Background Technology

[0002] The gate drive circuit of the display is a row scan drive circuit integrated on the array substrate, which can reduce the use of external integrated circuits in the display, thereby reducing the production cost of the display and facilitating the realization of a narrow bezel design for the display.

[0003] However, as the size of displays increases, the number of main and redundant units required in the gate drive circuit also increases. This leads to a greater difference between the output load of the main unit and the output load of the redundant unit in the gate drive circuit, which in turn affects the performance of the gate drive circuit. Utility Model Content

[0004] Therefore, this application provides a gate driving circuit for an array substrate, an array substrate, and a display, to improve the performance of the gate driving circuit. The technical solution of this application is as follows:

[0005] A first aspect of this application provides a gate driving circuit for an array substrate, the array substrate including a front panel wiring area, the gate driving circuit including a main stage unit, a redundant unit, and a compensation capacitor unit; the main stage unit is connected to the gate line of the front panel wiring area, the redundant unit is connected to the main stage unit, the positive terminal of the compensation capacitor unit is connected to the output node of the redundant unit, and the negative terminal of the compensation capacitor unit is connected to the ground terminal of the gate driving circuit; the main stage unit is used to drive the gate line; the redundant unit is used to drive the gate line when the main stage unit fails; the compensation capacitor unit is used to compensate the first load of the redundant unit to a target load, the target load being the second load of the output node of the main stage unit.

[0006] In one embodiment of this application, the load compensation value of the compensation capacitor unit is greater than or equal to 5% of the second load.

[0007] In one embodiment of this application, the compensation capacitor unit includes a compensation capacitor, which includes a first conductor at the positive terminal and a second conductor at the negative terminal. The first conductor is composed of a first type of metal encapsulating a second type of metal, and the second conductor is composed of a first type of metal encapsulating a third type of metal.

[0008] In one embodiment of this application, a semiconductor layer is disposed between the first conductor and the second conductor.

[0009] A second aspect of this application provides an array substrate, including a front panel wiring area, a first gate circuit area, and a second gate circuit area; the front panel wiring area is used to connect to a display front panel; the first gate circuit area and the second gate circuit area are respectively disposed on both sides of the front panel wiring area; the first gate circuit area and the second gate circuit area are respectively disposed with the gate driving circuit.

[0010] In one embodiment of this application, the first gate circuit region includes a first main stage region, a first redundancy region, and a second redundancy region. The first redundancy region and the second redundancy region are respectively disposed at the upper and lower ends of the first main stage region. The first main stage region is used to house the main stage unit, and the first redundancy region and the second redundancy region are used to house the redundancy unit. The second gate circuit region includes a second main stage region, a third redundancy region, and a fourth redundancy region. The third redundancy region and the fourth redundancy region are respectively disposed at the upper and lower ends of the second main stage region. The second main stage region is used to house the main stage unit, and the third redundancy region and the fourth redundancy region are used to house the redundancy unit.

[0011] In one embodiment of this application, the array substrate further includes a first fan-out region, a second fan-out region, a first driver chip, and a second driver chip; the first fan-out region and the second fan-out region are disposed below the front panel wiring area, the first driver chip is disposed below the first fan-out region, and the second driver chip is disposed below the second fan-out region; the first driver chip is connected to the front panel wiring area through the first fan-out region, and the second driver chip is connected to the front panel wiring area through the second fan-out region; the first gate circuit region further includes a first compensation region, which is disposed between the first fan-out region and the second redundancy region, and the first compensation region is used to house the compensation capacitor unit; the second gate circuit region further includes a second compensation region, which is disposed between the second fan-out region and the fourth redundancy region, and the second compensation region is used to house the compensation capacitor unit.

[0012] The first gate circuit region of the array substrate further includes a third compensation region, which is disposed between the first redundancy region and the front board wiring region, and is used to house the compensation capacitor unit.

[0013] The second gate circuit region of the array substrate further includes a fourth compensation region, which is disposed between the third redundancy region and the front board wiring region, and is used to house the compensation capacitor unit.

[0014] A third aspect of this application provides a display, including a display front panel and the array substrate.

[0015] It is understood that in the gate drive circuit of this application embodiment, by setting a compensation capacitor unit for the redundant unit, the positive terminal of the compensation capacitor unit is connected to the output node of the redundant unit, and the negative terminal is connected to the ground terminal of the gate drive circuit. Since the compensation capacitor unit compensates the first load of the output node of the redundant unit to the second load of the output node of the main unit, the load of the redundant unit and the main unit are made closer to the same, thereby improving the performance of the gate drive circuit. Attached Figure Description

[0016] Figure 1 This is a schematic block diagram of a gate driving circuit for an array substrate provided in an embodiment of this application.

[0017] Figure 2 This is a schematic block diagram of a compensation capacitor provided in an embodiment of this application.

[0018] Figure 3 This is a schematic diagram of the structure of an array substrate provided in an embodiment of this application.

[0019] Figure 4 This is a schematic diagram of the structure of the second array substrate provided in the embodiments of this application.

[0020] Figure 5 This is a schematic diagram of the structure of the third array substrate provided in the embodiments of this application.

[0021] Figure 6 This is a partial structural schematic diagram of an array substrate provided in an embodiment of this application. Detailed Implementation

[0022] It should be noted that in the embodiments of this application, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone, where A and B can be singular or plural. The terms "first," "second," "third," "fourth," etc. (if present) in the specification, claims, and drawings of this application are used to distinguish similar objects, not to describe a specific order or sequence.

[0023] It should also be noted that the methods disclosed in the embodiments of this application or the methods shown in the flowcharts include one or more steps for implementing the method. Without departing from the scope of the claims, the execution order of multiple steps can be interchanged, and some steps can also be deleted.

[0024] The gate drive circuit of the display is a row scan drive circuit integrated on the array substrate, which can reduce the use of external integrated circuits in the display, thereby reducing the production cost of the display and facilitating the realization of a narrow bezel design for the display.

[0025] However, as the size of displays increases, the number of main and redundant units required in the gate drive circuit also increases. This leads to a greater difference between the output load of the main unit and the output load of the redundant unit in the gate drive circuit, which in turn affects the performance of the gate drive circuit.

[0026] This application provides a gate driving circuit for an array substrate, an array substrate, and a display, for improving the performance of the gate driving circuit.

[0027] Please refer to Figure 1 , Figure 1 This is a schematic block diagram of a gate driving circuit for an array substrate provided in an embodiment of this application. The array substrate includes a front panel wiring area, and the gate driving circuit 100 includes a main stage unit 110, a redundancy unit 120, and a compensation capacitor unit 130.

[0028] In this embodiment, the main stage unit 110 is connected to the gate line of the front panel wiring area, the redundant unit 120 is connected to the main stage unit 110, the positive terminal of the compensation capacitor unit 130 is connected to the output node of the redundant unit 120, and the negative terminal of the compensation capacitor unit 130 is connected to the ground terminal of the gate drive circuit 100.

[0029] The main stage unit 110 is used to drive the gate lines. The redundancy unit 120 is used to drive the gate lines in the event of a failure of the main stage unit 110. The compensation capacitor unit 130 is used to compensate the first load of the redundancy unit 120 to a target load, where the target load is the second load of the output node of the main stage unit 110.

[0030] It is understood that in the gate drive circuit 100 of this application embodiment, by providing a compensation capacitor unit 130 for the redundant unit 120, the positive terminal of the compensation capacitor unit 130 is connected to the output node of the redundant unit 120, and the negative terminal is connected to the ground terminal of the gate drive circuit 100. Since the compensation capacitor unit 130 compensates the first load of the output node of the redundant unit 120 to the second load of the output node of the main unit 110, the loads of the redundant unit 120 and the main unit 110 are made closer to the same, thereby improving the performance of the gate drive circuit 100.

[0031] In some embodiments, the load compensation value of the compensation capacitor unit 130 is greater than or equal to 5% of the second load.

[0032] In this embodiment, the compensation capacitor unit 130 includes a compensation capacitor 131. Please refer to... Figure 2 , Figure 2 This is a schematic block diagram of a compensation capacitor 131 provided in an embodiment of the present application. The compensation capacitor 131 includes a first conductor 1311 at the positive terminal and a second conductor 1312 at the negative terminal. The first conductor 1311 is composed of a first type of metal encapsulating a second type of metal, and the second conductor 1312 is composed of a first type of metal encapsulating a third type of metal.

[0033] In some embodiments, a semiconductor layer 1313 is disposed between the first conductor 1311 and the second conductor 1312. It can be understood that the compensation capacitor 131, in which the first conductor 1311 is formed by encapsulating a second metal with a first metal, and the second conductor 1312 is formed by encapsulating a third metal with a first metal, and the semiconductor layer 1313 is disposed between the first conductor 1311 and the second conductor 1312, can further improve the performance of the compensation capacitor 131, thereby improving the stability of the gate drive circuit 100.

[0034] Please refer to Figure 3 , Figure 3 This is a schematic diagram of the structure of an array substrate 10 provided in an embodiment of this application. The array substrate 10 includes a front panel wiring area 101, a first gate circuit area 102, and a second gate circuit area 103.

[0035] In this embodiment, the front panel wiring area 101 is used to connect to the display front panel. A first gate circuit area 102 and a second gate circuit area 103 are respectively disposed on both sides of the front panel wiring area 101. The first gate circuit area 102 and the second gate circuit area 103 are respectively provided with the gate driving circuit 100 of any of the above embodiments.

[0036] In some embodiments, such as Figure 4 As shown, the first gate circuit region 102 includes a first main stage region 1021, a first redundancy region 1022 and a second redundancy region 1023. The first redundancy region 1022 and the second redundancy region 1023 are respectively disposed at the upper and lower ends of the first main stage region 1021. The first main stage region 1021 is used to house the main stage unit 110, and the first redundancy region 1022 and the second redundancy region 1023 are used to house the redundancy unit 120.

[0037] The second gate circuit region 103 includes a second main stage region 1031, a third redundancy region 1032 and a fourth redundancy region 1033. The third redundancy region 1032 and the fourth redundancy region 1033 are respectively disposed at the upper and lower ends of the second main stage region 1031. The second main stage region 1031 is used to house the main stage unit 110, and the third redundancy region 1032 and the fourth redundancy region 1033 are used to house the redundancy unit 120.

[0038] In some embodiments, such as Figure 5As shown, the array substrate 10 also includes a first fan-out area 104, a second fan-out area 105, a first driver chip 106, and a second driver chip 107. The first fan-out area 104 and the second fan-out area 105 are located below the front panel wiring area 101. The first driver chip 106 is located below the first fan-out area 104, and the second driver chip 107 is located below the second fan-out area 105. The first driver chip 106 is connected to the front panel wiring area 101 through the first fan-out area 104, and the second driver chip 107 is connected to the front panel wiring area 101 through the second fan-out area 105.

[0039] The first gate circuit region 102 further includes a first compensation region 1024, which is disposed between the first fan-out region 104 and the second redundancy region 1023. The first compensation region 1024 is used to house the compensation capacitor unit 130. The second gate circuit region 103 further includes a second compensation region 1034, which is disposed between the second fan-out region 105 and the fourth redundancy region 1033. The second compensation region 1034 is used to house the compensation capacitor unit 130.

[0040] In some embodiments, such as Figure 6 As shown, a redundancy unit 120 is provided in the second redundancy area 1023. The redundancy unit 120 includes n redundancy sub-units 121, where n is a positive integer greater than or equal to 1. Figure 6 (Example 3) Each redundant sub-unit 121 can be used to drive one of the gate lines. n compensation capacitors 131 can be provided in the first compensation region 1024, each compensation capacitor 131 connected to one of the redundant sub-units 121, used to compensate for the load of the output node of the corresponding redundant sub-unit 121. It can be understood that setting the compensation region where the compensation capacitors 131 are provided in the diagonal space between the first fan-out region 104 and the second redundant region 1023 can fully utilize the space of the array substrate 10 to provide more compensation capacitors 131, thereby improving the performance and stability of the gate drive circuit 100.

[0041] The first gate circuit region 102 further includes a third compensation region 1025, which is located between the first redundancy region 1022 and the front panel wiring region 101. The third compensation region 1025 is used to house the compensation capacitor unit 130. The second gate circuit region 103 further includes a fourth compensation region 1035, which is located between the third redundancy region 1032 and the front panel wiring region 101. The fourth compensation region 1035 is used to house the compensation capacitor unit 130.

[0042] This application also provides a display, including a front display panel and an array substrate 10 of any of the above embodiments. It is understood that the beneficial effects achieved by the display can be referenced to the beneficial effects of the array substrate 10 in the foregoing embodiments, and will not be repeated here.

[0043] The embodiments described above are merely preferred embodiments of this application and are not intended to limit the scope of this application. Any modifications and improvements made by those skilled in the art to the technical solutions of this application without departing from the spirit of this application should fall within the protection scope defined by the claims of this application.

Claims

1. A gate driving circuit for an array substrate, the array substrate including a front panel wiring area, characterized in that, The gate drive circuit includes a main stage unit, a redundancy unit, and a compensation capacitor unit. The main stage unit is connected to the gate line of the front board wiring area, the redundant unit is connected to the main stage unit, the positive terminal of the compensation capacitor unit is connected to the output node of the redundant unit, and the negative terminal of the compensation capacitor unit is connected to the ground terminal of the gate drive circuit. The main stage unit is used to drive the gate line; The redundant unit is used to drive the gate line when the main stage unit fails; The compensation capacitor unit is used to compensate the first load of the redundant unit to the target load, and the target load is the second load of the output node of the master unit.

2. The gate driving circuit as described in claim 1, characterized in that, The load compensation value of the compensation capacitor unit is greater than or equal to 5% of the second load.

3. The gate driving circuit as described in claim 1, characterized in that, The compensation capacitor unit includes a compensation capacitor, which includes a first conductor at the positive terminal and a second conductor at the negative terminal. The first conductor is composed of a first type of metal encapsulating a second type of metal, and the second conductor is composed of a first type of metal encapsulating a third type of metal.

4. The gate driving circuit as described in claim 3, characterized in that, A semiconductor layer is disposed between the first conductor and the second conductor.

5. An array substrate, characterized in that, It includes the front panel wiring area, the first gate circuit area, and the second gate circuit area; The front panel wiring area is used to connect to the display front panel; The first gate circuit region and the second gate circuit region are respectively disposed on both sides of the front panel wiring area; The first gate circuit region and the second gate circuit region are respectively provided with gate driving circuits as described in any one of claims 1 to 4.

6. The array substrate as described in claim 5, characterized in that, The first gate circuit region includes a first main stage region, a first redundancy region, and a second redundancy region. The first redundancy region and the second redundancy region are respectively disposed at the upper and lower ends of the first main stage region. The first main stage region is used to house the main stage unit, and the first redundancy region and the second redundancy region are used to house the redundancy unit. The second gate circuit region includes a second main stage region, a third redundancy region, and a fourth redundancy region. The third redundancy region and the fourth redundancy region are respectively disposed at the upper and lower ends of the second main stage region. The second main stage region is used to house the main stage unit, and the third redundancy region and the fourth redundancy region are used to house the redundancy unit.

7. The array substrate as described in claim 6, characterized in that, It also includes a first fan-out area, a second fan-out area, a first driver chip, and a second driver chip; The first fan-out area and the second fan-out area are located below the front panel wiring area. The first driver chip is located below the first fan-out area, and the second driver chip is located below the second fan-out area. The first driver chip is connected to the front panel wiring area through the first fan-out area, and the second driver chip is connected to the front panel wiring area through the second fan-out area. The first gate circuit region further includes a first compensation region, which is disposed between the first fan-out region and the second redundancy region, and is used to house the compensation capacitor unit. The second gate circuit region further includes a second compensation region, which is disposed between the second fan-out region and the fourth redundancy region. The second compensation region is used to house the compensation capacitor unit.

8. The array substrate as described in claim 6, characterized in that, The first gate circuit region further includes a third compensation region, which is disposed between the first redundancy region and the front board wiring region, and is used to house the compensation capacitor unit.

9. The array substrate as described in claim 6, characterized in that, The second gate circuit region further includes a fourth compensation region, which is disposed between the third redundancy region and the front board wiring region, and is used to house the compensation capacitor unit.

10. A display, characterized in that, It includes a display front panel and an array substrate as described in any one of claims 5 to 9.

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