A circuit package structure supporting stack-up soldering

Abstract

This utility model relates to the field of circuit structure design technology, and discloses a circuit packaging structure that supports stacked soldering. It includes a substrate with an upper and lower surface, stamp-hole pads located at the edge of the substrate for basic electrical connection to the motherboard, and a padless empty area in the central region of the upper surface of the substrate. The surface of the padless empty area has an exposed metal layer, on which a functional circuit board is vertically soldered. By centrally arranging the stamp-hole pads at the edge and retaining the padless empty area in the center, the top of the stamp-hole package module is solderable. This design breaks through the limitation of traditional full-pad structures on vertical space occupation, allowing the upper PCB to be directly stacked and soldered onto the empty area surface. Without increasing the planar size, it achieves system function expansion and space utilization optimization, effectively improving the system expansion capability of small-sized modules in complex functional scenarios, and is particularly suitable for applications such as drone navigation, smart terminals, and high-precision positioning.

Description

Technical Field

[0001] This utility model relates to the field of circuit structure design technology, and in particular to a circuit packaging structure that supports stacked soldering. Background Technology

[0002] Stamp holes are mechanical structures in PCB panelization that connect smaller boards to process edges. They are achieved by creating an array of non-metallic semi-circular holes (resembling the edge of a stamp) on the connecting ribs, thus separating the panel. Current electronic modules commonly use a fully enclosed stamp hole packaging method. While this approach is beneficial for mass production and surface mount technology, the top packaging area cannot support other PCB structures, limiting functional expansion and device integration within a limited space. Forcibly stacking upper PCBs can obstruct edge pads and disrupt electrical connections; this problem is particularly pronounced in space-sensitive scenarios such as industrial IoT devices, navigation terminals, and embedded microsystems. Therefore, there is an urgent need for a space-saving stacking structure compatible with standard packaging processes to improve PCB utilization and system integration. Utility Model Content

[0003] This application discloses a circuit package structure that supports stacked soldering, in order to solve the technical problem that the top package area of ​​the existing electronic modules using the fully enclosed stamp hole package form cannot support other PCB structures.

[0004] To solve the above problems, the present invention adopts the following technical solution: This utility model provides a circuit package structure that supports stacked soldering, including a substrate having an upper surface and a lower surface opposite to each other; a stamp hole pad disposed on the edge region of the substrate; a padless empty area disposed in the central region of the upper surface of the substrate, the surface of the padless empty area having an exposed metal layer; and a functional circuit board vertically soldered to the padless empty area.

[0005] Preferably, the area of ​​the padless void area accounts for 40%-70% of the total area of ​​the upper surface of the substrate.

[0006] Preferably, the pads of the functional circuit board are fixed to the padless area of ​​the substrate by solder paste reflow soldering.

[0007] Preferably, the surface of the padless area is provided with an anti-oxidation metal coating.

[0008] Preferably, the hole wall of the stamp hole pad is metallized.

[0009] Preferably, a thermally conductive insulating layer is provided between the substrate and the functional circuit board.

[0010] Preferably, the stamp hole pad adopts a standard 1216 stamp hole layout.

[0011] The technical solution adopted in this utility model can achieve the following beneficial effects: 1. This utility model provides a circuit packaging structure supporting stacked soldering, comprising a substrate having opposing upper and lower surfaces; stamp hole pads disposed at the edge region of the substrate, providing basic electrical connection with the motherboard; a padless empty area disposed at the center region of the upper surface of the substrate, the surface of the padless empty area having an exposed metal layer; and a functional circuit board vertically soldered onto the padless empty area. By centrally distributing stamp hole pads at the edge region and retaining the padless empty area in the center, the top of the stamp hole packaging module is made solderable. This design breaks through the limitation of traditional full-pad structures on vertical space occupation, allowing the upper PCB to be directly stacked and soldered onto the empty area surface. Without increasing the planar size, it achieves system function expansion and space utilization optimization, effectively improving the system expansion capability of small-sized modules in complex functional scenarios, and is particularly suitable for applications such as drone navigation, smart terminals, and high-precision positioning.

[0012] 2. Set the area of ​​the padless empty area to 40%-70% of the total area of ​​the upper surface. This ensures that the upper PCB has sufficient soldering area to avoid cold solder joints, while also preserving the mechanical strength of the edge pads to prevent board breakage. This ratio balances solderability and structural reliability. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 This is a schematic diagram of a circuit package structure supporting stacked soldering disclosed in some embodiments of this application; Figure 2 This is a schematic diagram of a circuit package structure that supports stacked soldering and removes a functional circuit board, as disclosed in some embodiments of this application. Figure 3 This is a side view of a circuit package structure supporting stacked soldering disclosed in some embodiments of this application.

[0015] In the picture: 1. A circuit packaging structure that supports stacked soldering; 10. Substrate; 11. Stamp hole pad; 12. Padless area; 13. Functional circuit board; 100. Thermally conductive insulating layer; 101. Electronic device. Detailed Implementation

[0016] To make the objectives, technical solutions, and advantages of this utility model clearer, the technical solutions of this utility model will be described in detail below. Obviously, the described embodiments are only a part of the embodiments of this utility model, and not all of them. Based on the embodiments of this utility model, all other implementation methods obtained by those skilled in the art without creative effort are within the scope of protection of this utility model.

[0017] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0018] Traditional stamp hole designs require pads to be laid out along the entire edge of the board for mechanical connection, resulting in the top area being occupied by pads and unusable as a soldering surface. If upper PCB layers are forcibly stacked, the edge pads will be blocked, damaging the electrical connection. Burrs after board separation can easily damage the circuit. Existing improvements (such as the three-hole offset design) only optimize the board separation accuracy and do not solve the space reuse problem. Furthermore, existing stamp hole templates require a dedicated test base plate, and the flying wire connections are complex and prone to poor contact. Repair requires disassembling the entire board, resulting in high rework costs.

[0019] The following is in conjunction with the appendix Figures 1 to 3 The present application provides a detailed description of a circuit packaging structure 1 that supports stacked soldering through specific embodiments and application scenarios.

[0020] Please refer to Figure 1 and Figure 2 The first embodiment of this utility model provides a circuit package structure 1 that supports stacked soldering, including a substrate 10 having an upper surface and a lower surface, a stamp hole pad 11 disposed in the edge region of the substrate 10 for basic electrical connection with the motherboard, and a padless empty area 12 disposed in the central region of the upper surface of the substrate 10, the surface of the padless empty area 12 having an exposed metal layer, on which a functional circuit board 13 is vertically soldered.

[0021] Understandably, when electronic components 101 can be placed in the regular area, the stamp hole pads 11 are concentrated in the edge area while retaining the padless empty area 12 in the middle, thus achieving the top solderability of the stamp hole package module. This design breaks through the limitation of the traditional full pad structure on the vertical space, allowing the upper PCB to be directly stacked and soldered on the surface of the padless empty area 12. Without increasing the planar size, it achieves the optimization of system function expansion and space utilization, effectively improving the system expansion capability of small-sized modules in complex functional scenarios. It is particularly suitable for applications such as drone navigation, smart terminals, and high-precision positioning.

[0022] Furthermore, the stamp hole pad 11 adopts a standard 1216 stamp hole layout; specifically, it adopts a standard 1216 package size stamp hole layout, and the number and spacing of the edge pads comply with industry standards, ensuring the compatibility of the module with the existing main PCB. Users can directly replace the traditional module without modifying the motherboard design or SMT production line parameters, significantly reducing upgrade costs and supply chain risks.

[0023] Specifically, in the first embodiment, the substrate 10 has dimensions of 14.38 mm × 31.29 mm.

[0024] As an optional implementation, other standard stamp hole layouts and substrate sizes can also be used in actual production.

[0025] Furthermore, the area of ​​the padless empty area 12 accounts for 40%-70% of the total area of ​​the upper surface of the substrate 10.

[0026] Understandably, setting the area of ​​the padless empty area 12 to 40%-70% of the total area of ​​the upper surface ensures that the upper PCB has sufficient soldering area to avoid cold solder joints, while also preserving the mechanical strength of the edge pads to prevent board breakage. This ratio balances solderability and structural reliability.

[0027] Furthermore, the pads of the functional circuit board 13 are fixed to the padless empty area 12 of the substrate 10 by solder paste reflow soldering.

[0028] Specifically, the connection between the upper PCB and the padless empty area 12 is achieved through solder paste reflow soldering. The motherboard soldering and stacking soldering are completed simultaneously using a standard SMT production line, avoiding secondary high temperature impact. This saves time per reflow soldering, improves production efficiency, and avoids the risk of misalignment or cold soldering caused by manual soldering.

[0029] Furthermore, the surface of the padless empty area 12 is provided with an anti-oxidation metal coating.

[0030] Specifically, the anti-oxidation metal coating in this embodiment is an electroless nickel-gold (ENIG) anti-oxidation coating, which can effectively improve the oxidation resistance of the solder pads, reduce the surface tension of reflow soldering, and help improve the solder paste spreading rate; avoid the risk of migration short circuit caused by copper layer exposure, and improve the long-term stability of stacked circuits.

[0031] Furthermore, the hole wall of the stamp hole pad 11 is metallized; specifically, the hole wall of the stamp hole pad 11 is metallized by copper plating and gold plating to increase the thickness of the conductive layer on the inner wall of the pad. This design helps to enhance the pad's resistance to mechanical stress and improve the integrity of high-frequency signals.

[0032] Further, please refer to Figure 3 A thermally conductive insulating layer 100 is provided between the substrate 10 and the functional circuit board 13.

[0033] Specifically, in the first embodiment, the thermally conductive insulating layer 100 is a ceramic-filled epoxy resin thermally conductive layer, which is beneficial to the thermal conduction and cooling of the functional circuit board 13; and improves the overall insulation and withstand voltage performance, prevents high-frequency interference coupling; and can fill the welding gaps and enhance the overall mechanical shock resistance of the circuit board.

[0034] The circuit packaging structure supporting stacked soldering provided by this embodiment of the invention has the following advantages over the prior art: 1. This utility model provides a circuit packaging structure supporting stacked soldering, comprising a substrate having opposing upper and lower surfaces; stamp hole pads disposed at the edge region of the substrate, providing basic electrical connection with the motherboard; a padless empty area disposed at the center region of the upper surface of the substrate, the surface of the padless empty area having an exposed metal layer; and a functional circuit board vertically soldered onto the padless empty area. By centrally distributing stamp hole pads at the edge region and retaining the padless empty area in the center, the top of the stamp hole packaging module is made solderable. This design breaks through the limitation of traditional full-pad structures on vertical space occupation, allowing the upper PCB to be directly stacked and soldered onto the empty area surface. Without increasing the planar size, it achieves the optimization of system function expansion and space utilization, effectively improving the system expansion capability of small-sized modules in complex functional scenarios, and is particularly suitable for applications such as UAV navigation, smart terminals, and high-precision positioning.

[0035] 2. Set the area of ​​the padless empty area to 40%-70% of the total area of ​​the upper surface. This ensures that the upper PCB has sufficient soldering area to avoid cold solder joints, while also preserving the mechanical strength of the edge pads to prevent board breakage. This ratio balances solderability and structural reliability.

[0036] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0037] Furthermore, it should be noted that the scope of the methods and apparatus in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. In addition, features described with reference to certain examples may be combined in other examples.

[0038] The above description is only a specific embodiment of this utility model, but the protection scope of this utility model is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this utility model should be included within the protection scope of this utility model.

Claims

1. A circuit package structure supporting stacked soldering, characterized in that, include: The substrate has opposing upper and lower surfaces; Stamp hole pads are provided in the edge region of the substrate; A padless empty area is provided in the central region of the upper surface of the substrate, and the surface of the padless empty area has an exposed metal layer. The functional circuit board is vertically soldered onto the padless empty area.

2. The circuit package structure supporting stacked soldering according to claim 1, characterized in that, The area of ​​the padless void area accounts for 40%-70% of the total area of ​​the upper surface of the substrate.

3. The circuit package structure supporting stacked soldering according to claim 1, characterized in that, The pads of the functional circuit board are fixed to the padless empty area of ​​the substrate by solder paste reflow soldering.

4. The circuit package structure supporting stacked soldering according to claim 1, characterized in that, The surface of the padless area is coated with an anti-oxidation metal coating.

5. A circuit package structure supporting stacked soldering according to claim 1, characterized in that, The hole walls of the stamp hole pads are metallized.

6. A circuit package structure supporting stacked soldering according to claim 1, characterized in that, A thermally conductive insulating layer is provided between the substrate and the functional circuit board.

7. A circuit package structure supporting stacked soldering according to claim 1, characterized in that, The stamp hole pads adopt a standard 1216 stamp hole layout.

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