Semiconductor memory device

Abstract

To provide a semiconductor memory device that operates favorably.SOLUTION: A semiconductor memory device includes: a semiconductor layer (120); a gate electrode (110) facing the semiconductor layer; a first insulating film (131) provided between the semiconductor layer and the gate electrode, and including oxygen (O) and hafnium (Hf); and a second insulating film (133) provided between the first insulating film and the gate electrode. The first insulating film includes a first additive region (134), a second additive region (135), and a memory region (136). The first additive region and the second additive region each include at least one additive element selected from the group consisting of ruthenium (Ru), titanium (Ti), molybdenum (Mo), tantalum (Ta), tungsten (W), and platinum (Pt). The memory region includes no additive element, or a concentration of an additive element in the memory region is lower than a concentration of a second additive element in the first additive region.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present embodiment relates to a semiconductor memory device. [Background technology]

[0002] A semiconductor memory device including a plurality of memory transistors is known. The gate insulating film of the plurality of memory transistors is provided with a memory section capable of storing data, such as an insulating charge storage layer made of silicon nitride (Si3N4) or the like, a conductive charge storage layer such as a floating gate, a ferroelectric film, or the like. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP2021-48214 Public Relations [Patent Document 2] JP2022-145049 Public Relations Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor memory device that operates favorably is provided. [Means for solving the problem]

[0005] A semiconductor memory device according to one embodiment includes a semiconductor layer, a gate electrode facing the semiconductor layer, a first insulating film provided between the semiconductor layer and the gate electrode, containing oxygen (O), hafnium (Hf) and a first additive element, and having a rectangular crystal structure, and a second insulating film provided between the first insulating film and the gate electrode. The first insulating film includes a first additive region, a second additive region provided between the first additive region and the gate electrode, and a memory region provided between the first additive region and the second additive region. The first additive region includes at least one second additive element selected from the group consisting of ruthenium (Ru), titanium (Ti), molybdenum (Mo), tantalum (Ta), tungsten (W), and platinum (Pt). The second additive region includes at least one third additive element selected from the group consisting of ruthenium (Ru), titanium (Ti), molybdenum (Mo), tantalum (Ta), tungsten (W), and platinum (Pt). The memory region does not include the second additive element, or the concentration of the second additive element in the memory region is lower than the concentration of the second additive element in the first additive region. The memory region does not include the third additive element, or the concentration of the third additive element in the memory region is lower than the concentration of the third additive element in the second additive region. [Brief description of the drawings]

[0006] [Figure 1] 2 is a schematic circuit diagram showing a configuration of a portion of a memory die MD according to the first embodiment. FIG. [Diagram 2] FIG. 2 is a schematic plan view of a memory die MD. [Diagram 3] 2 is a schematic perspective view showing a configuration of a portion of a memory die MD. FIG. [Figure 4] FIG. 4 is a schematic cross-sectional view showing an enlarged portion of FIG. [Diagram 5] 1 is a schematic histogram for explaining the threshold voltage of a memory cell MC. [Figure 6] 1 is a schematic graph for explaining the polarizability of a memory cell MC. [Figure 7]10 is a schematic cross-sectional view for explaining the state of a memory cell MC. FIG. [Figure 8] 3 is a schematic energy band diagram for explaining the state of a memory cell MC. FIG. [Figure 9] 10 is a schematic cross-sectional view for explaining the state of a memory cell MC. FIG. [Figure 10] 3 is a schematic energy band diagram for explaining the state of a memory cell MC. FIG. [Figure 11] FIG. 2 is a schematic energy band diagram for explaining the effect of the first embodiment. [Figure 12] FIG. 2 is a schematic energy band diagram for explaining the effect of the first embodiment. [Figure 13] 5A to 5C are schematic cross-sectional views for explaining a manufacturing method of the memory die MD according to the first embodiment. [Figure 14] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 15] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 16] 11 is a schematic cross-sectional view showing a configuration of a portion of a semiconductor memory device according to a second embodiment. FIG. [Figure 17] 5A to 5C are schematic cross-sectional views for explaining a manufacturing method of the semiconductor memory device. [Figure 18] FIG. 11 is a schematic cross-sectional view showing a configuration of a portion of a semiconductor memory device according to a third embodiment. [Figure 19] 13A to 13C are schematic cross-sectional views for illustrating a method for manufacturing a semiconductor memory device according to a third embodiment. [Figure 20] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 21] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 22] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 23] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 24] FIG. 11 is a schematic cross-sectional view showing a configuration of a portion of a semiconductor memory device according to a fourth embodiment. [Diagram 25] 13A to 13C are schematic cross-sectional views for illustrating a method for manufacturing a semiconductor memory device according to a fourth embodiment. [Figure 26] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 27] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 28] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 29] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 30] FIG. 13 is a schematic cross-sectional view showing a configuration of a portion of a semiconductor memory device according to a fifth embodiment. [Diagram 31] 13A to 13C are schematic cross-sectional views illustrating a method for manufacturing a semiconductor memory device according to a fifth embodiment. [Diagram 32] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 33] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 34] 13 is a schematic cross-sectional view showing a configuration of a portion of a semiconductor memory device according to a sixth embodiment. FIG. [Diagram 35] 13A to 13C are schematic cross-sectional views for illustrating a method for manufacturing a semiconductor memory device according to a sixth embodiment. [Diagram 36] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 37] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 38] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 39] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 40] FIG. 13 is a schematic cross-sectional view showing a configuration of a portion of a semiconductor memory device according to a seventh embodiment. [Diagram 41]13A to 13C are schematic cross-sectional views illustrating a method for manufacturing a semiconductor memory device according to a seventh embodiment. [Diagram 42] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 43] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Next, a semiconductor memory device according to an embodiment will be described in detail with reference to the drawings. Note that the following embodiment is merely an example, and is not intended to limit the present invention. Also, the following drawings are schematic, and for the sake of explanation, some configurations may be omitted. Also, parts common to multiple embodiments may be given the same reference numerals, and explanations may be omitted.

[0008] In addition, in this specification, the term "semiconductor memory device" may refer to a memory die, or may refer to a memory system including a controller die, such as a memory chip, a memory card, or an SSD (Solid State Drive). Furthermore, it may refer to a configuration including a host computer, such as a smartphone, a tablet terminal, or a personal computer.

[0009] In addition, in this specification, the term "control circuit" may refer to a peripheral circuit such as a sequencer provided on a memory die, or may refer to a controller die or controller chip connected to a memory die, or may refer to a configuration that includes both of these.

[0010] In addition, in this specification, when it is said that a first configuration is "electrically connected" to a second configuration, the first configuration may be directly connected to the second configuration, or the first configuration may be connected to the second configuration via wiring, a semiconductor member, a transistor, etc. For example, when three transistors are connected in series, the first transistor is "electrically connected" to the third transistor even if the second transistor is in an OFF state.

[0011] In addition, in this specification, when it is said that a first configuration is "connected between" a second configuration and a third configuration, it may mean that the first configuration, the second configuration, and the third configuration are connected in series, and that the second configuration is connected to the third configuration via the first configuration.

[0012] In addition, in this specification, when it is said that a circuit or the like "conducts" two wirings or the like, it may mean, for example, that the circuit or the like includes a transistor or the like, that the transistor or the like is provided in a current path between the two wirings, and that the transistor or the like is in an ON state.

[0013] In this specification, a predetermined direction parallel to the upper surface of the substrate is called the X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is called the Y direction, and a direction perpendicular to the upper surface of the substrate is called the Z direction.

[0014] In addition, in this specification, the direction intersecting with the upper surface of the substrate may be referred to as the stacking direction. The stacking direction may or may not coincide with the Z direction. In addition, in this specification, the direction along a predetermined plane intersecting with the stacking direction may be referred to as the first direction, and the direction intersecting with the first direction along this predetermined plane may be referred to as the second direction. These first and second directions may or may not correspond to either the X direction or the Y direction.

[0015] In this specification, expressions such as "upper" and "lower" are based on the substrate. For example, the direction away from the substrate along the Z direction is called "up," and the direction toward the substrate along the Z direction is called "down." Furthermore, when referring to a certain configuration, the lower surface or lower end refers to the surface or end of the configuration facing the substrate, and when referring to the upper surface or upper end, refers to the surface or end of the configuration facing away from the substrate. Furthermore, surfaces that intersect with the X or Y direction are called side surfaces, etc.

[0016] In addition, in this specification, when referring to a configuration, member, etc., "width," "length," or "thickness" in a specific direction, this may mean the width, length, or thickness in a cross section observed by SEM (Scanning electron microscopy), TEM (Transmission electron microscopy), or the like.

[0017] [First embodiment] [Circuit configuration of memory die MD] Fig. 1 is a schematic circuit diagram showing a configuration of a part of a memory die MD according to the first embodiment. As shown in Fig. 1, the memory die MD includes a memory cell array MCA for storing data and a peripheral circuit PC connected to the memory cell array MCA.

[0018] As shown in Fig. 1, the memory cell array MCA includes a plurality of memory blocks BLK. Each of the memory blocks BLK includes a plurality of string units SU. Each of the string units SU includes a plurality of memory strings MS. One end of each of the memory strings MS is connected to the peripheral circuit PC via a plurality of electrically independent bit lines BL. The other ends of each of the memory strings MS are connected to the peripheral circuit PC via one electrically common source line SL.

[0019] The memory string MS includes a drain-side select transistor STD, a plurality of memory cells MC (memory transistors), and a source-side select transistor STS, which are connected in series between a bit line BL and a source line SL. Hereinafter, the drain-side select transistor STD and the source-side select transistor STS may be simply referred to as select transistors (STD, STS).

[0020] The memory cells MC are field-effect transistors including a semiconductor layer functioning as a channel region, a gate insulating film including a memory section, and a gate electrode. The threshold voltage of the memory cells MC changes depending on the state of the memory section. The memory cells MC store one or more bits of data. A word line WL is connected to each of the gate electrodes of the memory cells MC corresponding to one memory string MS. Each of these word lines WL is commonly connected to all the memory strings MS in one memory block BLK.

[0021] The selection transistors (STD, STS) are field-effect transistors having a semiconductor layer functioning as a channel region, a gate insulating film, and a gate electrode. The gate electrodes of the selection transistors (STD, STS) are connected to selection gate lines (SGD, SGS), respectively. The drain side selection gate line SGD is provided corresponding to the string unit SU, and is commonly connected to all memory strings MS in one string unit SU. The source side selection gate line SGS is commonly connected to all memory strings MS in a memory block BLK.

[0022] The peripheral circuit PC includes, for example, a voltage generation circuit that generates an operating voltage and outputs it to a voltage supply line, a decode circuit that connects the desired voltage supply line to the bit line BL, the source line SL, the word line WL, and the select gate line (SGD, SGS), a sense amplifier circuit that detects the current or voltage of the bit line BL, and a sequencer that controls these circuits.

[0023] [Memory die MD structure] 2 is a schematic plan view of the memory die MD. As shown in FIG. 2, the memory die MD includes a semiconductor substrate 100. In the illustrated example, the semiconductor substrate 100 includes two memory cell array regions R aligned in the X direction. MCA In addition, the memory cell array region R MCA A plurality of memory blocks BLK arranged in the Y direction are provided in the semiconductor substrate 100. A peripheral circuit region R PC is provided.

[0024] Fig. 3 is a schematic perspective view showing a configuration of a portion of the memory die MD, and Fig. 4 is a schematic cross-sectional view showing an enlarged view of a portion of Fig. 3.

[0025] As shown in Fig. 3, the memory block BLK includes a plurality of conductive layers 110 arranged in the Z direction above the semiconductor substrate 100, a conductive layer 111 provided below the conductive layers 110 (between the conductive layers 110 and the semiconductor substrate 100), and a plurality of semiconductor layers 120 extending in the Z direction. As shown in Fig. 4, the memory block BLK includes a plurality of gate insulating films 130 provided between the conductive layers 110 and the semiconductor layers 120. As shown in Fig. 3, the memory block BLK includes an electrode 140 connected to the conductive layer 111. Above these configurations, the bit line BL described with reference to Fig. 1 is provided.

[0026] The semiconductor substrate 100 is made of P-type silicon (Si) containing P-type impurities such as boron (B). An N-type well region containing N-type impurities such as phosphorus (P), a P-type well region containing P-type impurities such as boron (B), and a semiconductor substrate region in which neither the N-type well region nor the P-type well region is provided are provided on the surface of the semiconductor substrate 100. The N-type well region, the P-type well region, and the semiconductor substrate region each function as a part of a plurality of transistors and a plurality of capacitors that constitute the peripheral circuit PC.

[0027] The conductive layer 110 is a substantially plate-shaped conductive layer extending in the X direction. The conductive layer 110 may include a laminated film of a barrier conductive film 112 such as titanium nitride (TiN) and a metal film 113 such as tungsten (W), as illustrated in Fig. 4. The conductive layer 110 may also include polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). An insulating layer 101 such as silicon oxide (SiO2) is provided between the conductive layers 110 arranged in the Z direction.

[0028] The multiple conductive layers 110 function as the word lines WL described with reference to FIG. 1 and the gate electrodes of the multiple memory cells MC connected thereto. In the following description, such a conductive layer 110 may be referred to as a conductive layer 110(WL). These multiple conductive layers 110(WL) are electrically independent for each memory block BLK. When focusing on two memory blocks BLK adjacent to each other in the Y direction, the multiple conductive layers 110(WL) arranged in the Z direction and the multiple insulating layers 101 provided on the upper and lower surfaces of these layers in these two memory blocks BLK are divided in the Y direction.

[0029] One or more conductive layers 110 located below the multiple conductive layers 110(WL) function as the gate electrodes of the source side select gate line SGS and the multiple source side select transistors STS connected thereto, as described with reference to Fig. 1. In the following description, such a conductive layer 110 may be referred to as a conductive layer 110(SGS). When focusing on two memory blocks BLK adjacent to each other in the Y direction, the one or more conductive layers 110(SGS) and the multiple insulating layers 101 provided on the upper and lower surfaces of these conductive layers 110(SGS) in these two memory blocks BLK are divided in the Y direction.

[0030] One or more conductive layers 110 located above the multiple conductive layers 110(WL) function as the drain side select gate line SGD and the gate electrodes of the multiple drain side select transistors STD connected thereto, as described with reference to Fig. 1. In the following description, such a conductive layer 110 may be referred to as a conductive layer 110(SGD).

[0031] As shown in FIG. 3, the width in the Y direction of the multiple conductive layers 110 (SGD) is smaller than the width in the Y direction of the conductive layer 110 (WL).

[0032] The multiple conductive layers 110 (SGD) are electrically independent for each string unit SU. In each memory block BLK, when focusing on two string units SU adjacent to each other in the Y direction, one or more conductive layers 110 (SGD) in these two string units SU are divided in the Y direction via an inter-string unit insulating member SHE. When focusing on the string unit SU closest to the other string unit among the multiple string units SU included in one of two memory blocks BLK adjacent to each other in the Y direction, and the string unit SU closest to the one string unit among the multiple string units SU included in the other memory block, one or more conductive layers 110 (SGD) in these two string units SU are divided in the Y direction.

[0033] The conductive layer 111 may include, for example, polycrystalline silicon containing an N-type impurity such as phosphorus (P). A metal such as tungsten (W), a conductive member such as tungsten silicide, or other conductive members may be provided on the lower surface of the conductive layer 111. The conductive layer 111 functions as a part of the source line SL described with reference to FIG.

[0034] The semiconductor layers 120 are arranged in a predetermined pattern in the X and Y directions. The semiconductor layers 120 function as channel regions of a plurality of memory cells MC and select transistors STD, STS included in one memory string MS (FIG. 1). The semiconductor layers 120 are, for example, semiconductor layers made of polycrystalline silicon (Si) or the like. The semiconductor layers 120 have a substantially cylindrical shape. The outer periphery of the semiconductor layers 120 are surrounded by the conductive layers 110 and face the conductive layers 110.

[0035] An impurity region (not shown) containing N-type impurities such as phosphorus (P) is provided at the upper end of the semiconductor layer 120. This impurity region is electrically connected to a bit line BL through a via contact electrode (not shown).

[0036] An impurity region (not shown) containing N-type impurities such as phosphorus (P) is provided at the lower end of the semiconductor layer 120. This impurity region is connected to the conductive layer 111.

[0037] The gate insulating film 130 (FIG. 4) has a substantially cylindrical shape extending in the Z direction along the outer circumferential surface of the semiconductor layer 120 over a range in the Z direction corresponding to the multiple conductive layers 110. The gate insulating film 130 includes a substantially cylindrical ferroelectric film 131 extending in the Z direction along the outer circumferential surface of the semiconductor layer 120 over a range in the Z direction corresponding to the multiple conductive layers 110, a substantially cylindrical insulating film 132 (interface layer) extending in the Z direction along the inner circumferential surface of the ferroelectric film 131 over a range in the Z direction corresponding to the multiple conductive layers 110, and a substantially cylindrical insulating film 133 (interface layer) extending in the Z direction along the outer circumferential surface of the ferroelectric film 131 over a range in the Z direction corresponding to the multiple conductive layers 110.

[0038] The ferroelectric film 131 may be, for example, an insulating film containing orthorhombic hafnium oxide. The hafnium oxide contained in the ferroelectric film 131 may be mainly orthorhombic. More specifically, the hafnium oxide contained in the ferroelectric film 131 may be mainly orthorhombic (orthorhombic III, space group Pbc21, space group number 29). The proportion of orthorhombic crystals among the hafnium oxide crystals contained in the ferroelectric film 131 may be the largest. The orthorhombic crystal is also called an orthorhombic crystal. The crystal structure in the ferroelectric film 131 can be observed by a method such as ACOM-TEM (Automated Crystal Orientation Mapping Transmission Electron Microscopy).

[0039] The ferroelectric film 131 may contain at least one additive element selected from the group consisting of silicon (Si), zirconium (Zr), aluminum (Al), yttrium (Y), strontium (Sr), lanthanum (La), samarium (Sm), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), ytterbium (Yb), lutetium (Lu), and barium (Ba). Hereinafter, such an additive element may be referred to as a "first additive element." The presence and concentration of the additive element may be confirmed by, for example, a method such as EDX (Energy Dispersive X-ray Spectroscopy).

[0040] From the viewpoint of making hafnium oxide exhibit ferroelectricity, the concentration of the first additive element is preferably 0.1 atomic % or more and 80 atomic % or less. The appropriate range of the concentration of the first additive element for making hafnium oxide exhibit ferroelectricity varies depending on the type of the first additive element. For example, when the first additive element is silicon (Si), the appropriate range of the concentration of the first additive element for making hafnium oxide exhibit ferroelectricity is 3 atomic % or more and 7 atomic % or less. For example, when the first additive element is barium (Ba), the appropriate range of the concentration of the first additive element for making hafnium oxide exhibit ferroelectricity is 0.1 atomic % or more and 3 atomic % or less. For example, when the first additive element is zirconium (Zr), the appropriate range of the concentration of the first additive element for making hafnium oxide exhibit ferroelectricity is 10 atomic % or more and 80 atomic % or less.

[0041] The ferroelectric film 131 also has an additive region 134 including an inner surface (surface on the semiconductor layer 120 side) of the ferroelectric film 131, an additive region 135 including an outer surface (surface on the conductive layer 110 side) of the ferroelectric film 131, and a memory region 136 provided between the additive region 134 and the additive region 135.

[0042] The additive region 134 contains at least one additive element selected from the group consisting of ruthenium (Ru), titanium (Ti), molybdenum (Mo), tantalum (Ta), tungsten (W), and platinum (Pt) in addition to the first additive element described above. Hereinafter, such an additive element may be referred to as a "second additive element." The concentration of the second additive element in the additive region 134 is, for example, 6.2×10 21 / cm 3 It may be the following.

[0043] The additive region 135 contains at least one additive element selected from the group consisting of ruthenium (Ru), titanium (Ti), molybdenum (Mo), tantalum (Ta), tungsten (W), and platinum (Pt) in addition to the first additive element described above. Hereinafter, such an additive element may be referred to as a "third additive element." The concentration of the third additive element in the additive region 135 is, for example, 6.2×10 21 / cm 3 The type and concentration of the third additive element in the additive region 135 may be the same as or different from the type and concentration of the second additive element in the additive region .

[0044] The memory region 136 may or may not contain a second additive element in addition to the first additive element described above. When the memory region 136 contains the second additive element, the concentration of the second additive element in the memory region 136 is lower than the concentration of the second additive element in the additive region 134. When the memory region 136 contains the second additive element, the boundary between the memory region 136 and the additive region 134 may be, for example, a position where the concentration of the second additive element is half of the peak value. When the memory region 136 does not contain the second additive element, the boundary between the memory region 136 and the additive region 134 may be, for example, a boundary between a region containing the second additive element and a region not containing the second additive element, or a boundary between a region where the second additive element can be detected and a region where the second additive element cannot be detected.

[0045] Furthermore, the memory region 136 may or may not contain a third additive element in addition to the first additive element described above. When the memory region 136 contains the third additive element, the concentration of the third additive element in the memory region 136 is lower than the concentration of the third additive element in the additive region 135. When the memory region 136 contains the third additive element, the boundary between the memory region 136 and the additive region 135 may be, for example, a position where the concentration of the third additive element is half of the peak value. When the memory region 136 does not contain the third additive element, the boundary between the memory region 136 and the additive region 135 may be, for example, a boundary between a region containing the third additive element and a region not containing the third additive element, or a boundary between a region where the third additive element can be detected and a region where the third additive element cannot be detected.

[0046] The thickness (radial length) of the memory region 136 is greater than the thickness (radial length) of the additive region 134 and the thickness (radial length) of the additive region 135. The thickness of the memory region 136 may be, for example, 8 nm or more. Here, when the thickness of the memory region 136 is 8 nm or more, the memory region 136 tends to exhibit ferroelectricity, and when the thickness is less than 8 nm, the memory region 136 tends to exhibit less ferroelectricity. In particular, when the thickness of the memory region 136 is 5 nm or less, the memory region 136 tends to exhibit less ferroelectricity.

[0047] The thickness (radial length) of the memory region 136 can be determined by various methods. For example, in this embodiment, the distance between the additive region 134 and the additive region 135 may be set as the thickness of the memory region 136.

[0048] The insulating film 132 is provided between the ferroelectric film 131 and the semiconductor layer 120 extending in the Z direction. In the example shown, the insulating film 132 contacts the ferroelectric film 131 and the semiconductor layer 120. The insulating film 132 includes, for example, silicon oxynitride (SiON) or the like.

[0049] The insulating film 133 is provided between the ferroelectric film 131 and the multiple conductive layers 110 aligned in the Z direction. In the example shown, the insulating film 133 contacts the ferroelectric film 131 and the multiple conductive layers 110 aligned in the Z direction. The insulating film 133 includes, for example, silicon oxide (SiO2), silicon oxynitride (SiON), or the like.

[0050] The electrode 140 extends in the X direction and the Z direction, as shown in FIG. 3, for example. An insulating film 141 such as silicon oxide (SiO2) is provided on both side surfaces of the electrode 140 in the Y direction. The electrode 140 is separated in the Y direction from the multiple conductive layers 110 arranged in the Z direction and the multiple insulating layers 101 provided between them, via the insulating film 141. The lower ends of the electrode 140 and the insulating film 141 are connected to the conductive layer 111. The electrode 140 may be a conductive member including, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). The electrode 140 may also be a semiconductor member such as polycrystalline silicon including impurities such as phosphorus (P) or boron (B). The electrode 140 functions as a part of the source line SL described with reference to FIG. 1.

[0051] [Threshold voltage of memory cell MC] Next, the threshold voltage of the memory cell MC will be described with reference to Fig. 5. Fig. 5 is a schematic histogram for explaining the threshold voltage of the memory cell MC. The horizontal axis indicates the voltage of the word line WL, and the vertical axis indicates the number of memory cells MC. Note that the threshold voltage referred to here is the threshold voltage when the memory cell MC is operated as an NMOS transistor.

[0052] In the example of Fig. 5, the threshold voltage of the memory cell MC is controlled to two states. For example, the threshold voltage of the memory cell MC controlled to the lower state is negative, and the absolute value of this threshold voltage is greater than the absolute value of the negative voltage V1 in Fig. 5. Also, the threshold voltage of the memory cell MC controlled to the higher state is positive, and the absolute value of this threshold voltage is greater than the absolute value of the positive voltage V2 in Fig. 5.

[0053] In a read operation, for example, a read voltage V between a negative voltage V1 and a positive voltage V2 is applied to the selected word line WL. CGR In the example of FIG. 5, the read voltage V CGR is the ground voltage V SS As a result, an electron channel is formed in the channel region of the selected memory cell MC controlled to a lower state, and no channel is formed in the channel region of the selected memory cell MC controlled to a higher state.

[0054] In a read operation, for example, a read pass voltage V , which is higher than the threshold voltage of the memory cell MC controlled to the higher state, is applied to the unselected word line WL. READ is supplied. As a result, the unselected memory cells MC are turned ON regardless of the data to be recorded. As a result, the selected memory cell MC is conductive to the bit line BL (FIG. 1) and source line SL (FIG. 1). Therefore, in this state, a voltage is supplied between the bit line BL and the source line SL, and by detecting whether or not a current flows through the bit line BL, the data recorded in the selected memory cell MC can be read.

[0055] Next, a method for controlling the threshold voltage of the memory cell MC will be described with reference to FIGS. 6 to 10. FIG. 6 is a schematic graph for explaining the polarizability of the memory cell MC. The horizontal axis of the graph shown in FIG. 6 indicates the voltage of the word line WL. The vertical axis of the graph shown in FIG. 6 indicates the polarizability P of the ferroelectric film 131. FIG. 7 is a schematic cross-sectional view for explaining the state of the memory cell MC. FIG. 8 is a schematic energy band diagram for explaining the state of the memory cell MC. FIG. 9 is a schematic cross-sectional view for explaining the state of the memory cell MC. FIG. 10 is a schematic energy band diagram for explaining the state of the memory cell MC. Note that FIGS. 8 and 10 respectively show the potential energy of electrons in the conduction bands of the configurations shown in FIGS. 7 and 9.

[0056] As described with reference to Fig. 4, the gate insulating film 130 of the memory cell MC according to this embodiment includes a ferroelectric film 131. When a positive voltage and a negative voltage of a predetermined magnitude or more are alternately supplied to the word line WL connected to such a memory cell MC, a hysteresis curve as shown in Fig. 6 is observed. In Fig. 6, states S1 and S2 are shown on this hysteresis curve.

[0057] State S1 is the state of the memory cell MC controlled to the higher state. In state S1, the polarization P is a negative polarization P1, and the voltage of the word line WL is the ground voltage V SS 7 and 8, negative charges are induced on the surface of the ferroelectric film 131 facing the semiconductor layer 120, and the potential energy of electrons in the vicinity of this surface is high. In this state, positive charges are induced on the surface of the semiconductor layer 120 facing the ferroelectric film 131, and the potential energy of electrons in the vicinity of this surface is high, making it difficult for an electron channel to be formed in the semiconductor layer 120. Therefore, the threshold voltage of the memory cell MC becomes a positive value.

[0058] When a voltage of approximately the magnitude of the read pass voltage is supplied to the gate electrode of the memory cell MC in state S1, there is no change in the polarization state of the ferroelectric film 131. When the supply of voltage to the gate electrode is interrupted in this state, the memory cell MC returns to state S1.

[0059] When a positive voltage of a predetermined magnitude or more is supplied to the gate electrode of the memory cell MC in state S1, the direction of polarization in the ferroelectric film 131 is reversed by the electric field between the conductive layer 110 and the semiconductor layer 120, and the polarizability P in the ferroelectric film 131 increases as shown in FIG. PGM When the voltage supply to the gate electrode is stopped in this state, the memory cell MC transitions to state S2.

[0060] State S2 is a state of the memory cell MC controlled to a lower state. In state S2, the polarization P is a positive polarization P2, and the voltage of the word line WL is the ground voltage V SS 9 and 10, positive charges are induced on the surface of the ferroelectric film 131 facing the semiconductor layer 120, and the potential energy of electrons in the vicinity of this surface is low. In this state, negative charges are induced on the surface of the semiconductor layer 120 facing the ferroelectric film 131, and the potential energy of electrons in the vicinity of this surface is low, so that an electron channel is formed in the semiconductor layer 120. Therefore, the threshold voltage of the memory cell MC becomes a negative value.

[0061] When a negative voltage of a predetermined magnitude or more is supplied to the gate electrode of the memory cell MC in state S2, the direction of polarization in the ferroelectric film 131 is reversed by the electric field between the conductive layer 110 and the semiconductor layer 120, and the polarizability P in the ferroelectric film 131 decreases as shown in FIG. era When the voltage supply to the gate electrode is stopped in this state, the memory cell MC transitions to state S1.

[0062] [effect] 11 and 12 are schematic energy band diagrams for explaining the effects of the first embodiment.

[0063] 4, the ferroelectric film 131 according to this embodiment includes an additive region 134 including an inner peripheral surface of the ferroelectric film 131 and including a second additive element such as titanium (Ti). With this configuration, the crystal structure of the ferroelectric film 131 can be controlled to be an orthorhombic crystal to favorably exhibit ferroelectric properties.

[0064] Here, in the additive region 134, a trap level due to the second additive element such as titanium (Ti) is formed. In FIG. 11, the state before electrons are accumulated in the trap level in the additive region 134 is shown by a solid line, and the state after electrons are accumulated is shown by a two-dot chain line. When electrons are trapped in the additive region 134, in state S1 described with reference to FIGS. 7 and 8, the energy gradient in the ferroelectric film 131 becomes steep as shown in FIG. 11. In such a case, the transition from state S1 to state S2 occurs at a low voltage. For example, when the read pass voltage V READ If a transition from state S1 to state S2 occurs in the read operation, a write error occurs when a read operation is executed.

[0065] Therefore, the ferroelectric film 131 according to this embodiment includes an outer circumferential surface of the ferroelectric film 131 and is provided with an additive region 135 that contains a third additive element such as titanium (Ti).

[0066] 12, the state before electrons are accumulated in the trap levels in the additive regions 134 and 135 is shown by a solid line, and the state after electrons are accumulated is shown by a two-dot chain line. In this embodiment, electrons are trapped not only on the inner peripheral surface of the ferroelectric film 131 but also on the outer peripheral surface. As a result, it is possible to make the energy gradient in the ferroelectric film 131 gentle, for example, as shown in FIG. 12. This makes it possible to suppress the occurrence of erroneous writing accompanying the execution of a read operation.

[0067] [Manufacturing method] Next, a method for manufacturing the memory die MD will be described with reference to Figures 13 to 15. Figures 13 to 15 are schematic cross-sectional views for explaining the manufacturing method.

[0068] In manufacturing the memory die MD according to this embodiment, as shown in Fig. 13, a plurality of sacrificial layers 110A and a plurality of insulating layers 101 are formed above the semiconductor substrate 100 described with reference to Fig. 3. The sacrificial layer 110A includes, for example, polycrystalline silicon (Si), silicon nitride (Si3N4), etc. This process is performed by, for example, a method such as CVD (Chemical Vapor Deposition).

[0069] 14, a memory hole MH is formed at a position corresponding to the semiconductor layer 120. The memory hole MH is a through hole that extends in the Z direction and penetrates the insulating layer 101 and the sacrificial layer 110A. This step is performed by a method such as RIE (Reactive Ion Etching).

[0070] 15, an insulating film 133, a ferroelectric film 131, an insulating film 132, and a semiconductor layer 120 are formed on the inner circumferential surface of the memory hole MH. This process is performed by a method such as CVD or ALD (Atomic Layer Deposition).

[0071] Thereafter, a groove is formed by RIE or the like at a position corresponding to the electrode 140 described with reference to Fig. 3, the sacrificial layer 110A is removed by wet etching or the like through the groove, and the conductive layer 110 is formed by CVD or the like, thereby manufacturing the structure as described with reference to Fig. 4. Furthermore, the insulating film 141, the electrode 140, the bit line BL, etc. are formed, thereby manufacturing the structure as described with reference to Fig. 3.

[0072] [Second embodiment] As described above, the ferroelectric film 131 according to the first embodiment has the additive region 135 including the outer circumferential surface of the ferroelectric film 131, which makes the energy gradient in the ferroelectric film 131 gentle. However, this configuration is merely an example, and the specific configuration can be adjusted as appropriate. For example, the additive region 135 only needs to be provided in the vicinity of the outer circumferential surface of the ferroelectric film 131, and does not need to include the outer circumferential surface. Hereinafter, such a configuration will be exemplified as a semiconductor memory device according to the second embodiment.

[0073] [composition] FIG. 16 is a schematic cross-sectional view showing a configuration of a portion of the semiconductor memory device according to the second embodiment.

[0074] The semiconductor memory device according to the second embodiment is basically configured in the same manner as the semiconductor memory device according to the first embodiment. However, the semiconductor memory device according to the second embodiment includes a gate insulating film 230 instead of the gate insulating film 130. The gate insulating film 230 is basically configured in the same manner as the gate insulating film 130. However, the gate insulating film 230 includes a ferroelectric film 231 instead of the ferroelectric film 131.

[0075] The ferroelectric film 231 is basically configured in the same manner as the ferroelectric film 131. However, the ferroelectric film 231 includes an additive region 134 including the inner peripheral surface of the ferroelectric film 231, a region 235 including the outer peripheral surface of the ferroelectric film 231, an additive region 236 provided between the additive region 134 and the region 235, and a memory region 237 provided between the additive region 134 and the additive region 236.

[0076] The additive region 236 is configured similarly to the additive region 135 described with reference to FIG.

[0077] The region 235 may or may not contain a third additive element in addition to the first additive element described above. When the region 235 contains the third additive element, the concentration of the third additive element in the region 235 is lower than the concentration of the third additive element in the additive region 236. When the region 235 contains the third additive element, the boundary between the region 235 and the additive region 236 may be, for example, a position where the concentration of the third additive element is half of the peak value. When the region 235 does not contain the third additive element, the boundary between the region 235 and the additive region 236 may be, for example, a boundary between a region containing the third additive element and a region not containing the third additive element, or a boundary between a region where the third additive element can be detected and a region where the third additive element cannot be detected.

[0078] Memory area 237 is configured similarly to memory area 136 described with reference to FIG.

[0079] [Manufacturing method] A method for manufacturing the semiconductor memory device according to the second embodiment will now be described with reference to Figure 17. Figure 17 is a schematic cross-sectional view for explaining the manufacturing method.

[0080] The semiconductor memory device according to the second embodiment is basically manufactured in the same manner as the semiconductor memory device according to the first embodiment. However, in manufacturing the semiconductor memory device according to the second embodiment, a gate insulating film 230 is formed instead of the gate insulating film 130 in the process described with reference to FIG. 15, as shown in FIG.

[0081] [Third embodiment] [composition] Next, a semiconductor memory device according to a third embodiment will be described with reference to Fig. 18. Fig. 18 is a schematic cross-sectional view showing the configuration of a portion of the semiconductor memory device according to the third embodiment.

[0082] The semiconductor memory device according to the third embodiment is basically configured similarly to the semiconductor memory device according to the first embodiment. However, the semiconductor memory device according to the third embodiment includes a gate insulating film 330 instead of the gate insulating film 130.

[0083] The gate insulating film 330 is basically configured in the same manner as the gate insulating film 130 .

[0084] However, the inner and outer diameters of the portion of the gate insulating film 330 provided at a height position corresponding to the insulating layer 101 are larger than the inner and outer diameters of the portion provided at a height position corresponding to the conductive layer 110, respectively.

[0085] The gate insulating film 330 also includes a plurality of insulating members 331 arranged in the Z direction corresponding to the plurality of insulating layers 101, a ferroelectric film 332 extending in the Z direction along the outer peripheral surfaces of the plurality of insulating members 331 and the semiconductor layer 120 over a Z direction range corresponding to the plurality of conductive layers 110, an insulating film 333 (interface layer) extending in the Z direction along the inner peripheral surface of the ferroelectric film 332 over a Z direction range corresponding to the plurality of conductive layers 110, and an insulating film 334 (interface layer) extending in the Z direction along the outer peripheral surface of the ferroelectric film 332 over a Z direction range corresponding to the plurality of conductive layers 110.

[0086] The insulating member 331 includes, for example, silicon oxide (SiO 2 ). The insulating member 331 has a substantially annular shape. An inner peripheral surface of the insulating member 331 is connected to an outer peripheral surface of the semiconductor layer 120.

[0087] The ferroelectric film 332 is basically configured in the same manner as the ferroelectric film 131. However, the inner and outer diameters of a portion 332b of the ferroelectric film 332 provided at a height position corresponding to the insulating layer 101 are larger than the inner and outer diameters of a portion 332a of the ferroelectric film 332 provided at a height position corresponding to the conductive layer 110, respectively.

[0088] That is, the ferroelectric film 332 includes a plurality of portions 332a provided at a plurality of height positions corresponding to a plurality of conductive layers 110, and a plurality of portions 332b provided at a plurality of height positions corresponding to a plurality of insulating layers 101. The inner diameter of the plurality of portions 332b is larger than the inner diameter of the plurality of portions 332a. That is, the distance D2 from the inner peripheral surface (surface on the semiconductor layer 120 side) of the plurality of portions 332b to the semiconductor layer 120 is larger than the distance D1 from the inner peripheral surface (surface on the semiconductor layer 120 side) of the plurality of portions 332a to the semiconductor layer 120. The difference between the distance D2 and the distance D1 may be, for example, 2 nm or more. Also, the outer diameter of the plurality of portions 332b is larger than the outer diameter of the plurality of portions 332a.

[0089] The ferroelectric film 332 also includes an additive region 335 including the inner circumferential surface of the ferroelectric film 332, and a memory region 336 provided between the additive region 335 and the conductive layer 110. The additive region 335 and the memory region 336 are formed in substantially the same manner as the additive region 134 and the memory region 136, respectively. However, the inner and outer diameters of the portion of the additive region 335 provided at a height position corresponding to the insulating layer 101 are larger than the inner and outer diameters of the portion of the memory region 336 provided at a height position corresponding to the conductive layer 110, respectively. The inner and outer diameters of the portion of the memory region 336 provided at a height position corresponding to the insulating layer 101 are larger than the inner and outer diameters of the portion of the memory region 336 provided at a height position corresponding to the conductive layer 110, respectively.

[0090] The insulating film 333 is basically configured in a manner similar to that of the insulating film 132. However, the inner and outer diameters of a portion 333b of the insulating film 333 provided at a height position corresponding to the insulating layer 101 are larger than the inner and outer diameters of a portion 333a of the insulating film 333 provided at a height position corresponding to the conductive layer 110, respectively.

[0091] That is, the insulating film 333 includes a plurality of portions 333a provided at a plurality of height positions corresponding to the plurality of conductive layers 110, and a plurality of portions 333b provided at a plurality of height positions corresponding to the plurality of insulating layers 101. The inner diameter of the plurality of portions 333b is larger than the inner diameter of the plurality of portions 333a. The outer diameter of the plurality of portions 333b is larger than the outer diameter of the plurality of portions 333a.

[0092] Note that the distance D3 from the inner circumferential surfaces (surfaces on the semiconductor layer 120 side) of the multiple portions 333b to the semiconductor layer 120 is greater than the distance from the inner circumferential surfaces (surfaces on the semiconductor layer 120 side) of the multiple portions 333a to the semiconductor layer 120. For example, in the illustrated example, the multiple portions 333a are each connected to the outer circumferential surface of the semiconductor layer 120, and the distance from the inner circumferential surfaces of the multiple portions 333a to the semiconductor layer 120 is zero. On the other hand, the multiple portions 333b are each separated from the semiconductor layer 120 via the insulating member 331, and therefore the distance D3 is not zero.

[0093] The insulating film 334 is basically configured in a manner similar to that of the insulating film 133. However, the inner and outer diameters of the portion of the insulating film 334 provided at a height position corresponding to the insulating layer 101 are larger than the inner and outer diameters of the portion of the insulating film 334 provided at a height position corresponding to the conductive layer 110, respectively.

[0094] [effect] As described with reference to FIG. 4, in the first embodiment, the additive region 134 of the ferroelectric film 131 is formed in a substantially cylindrical shape. Here, as described above, an electron trap level is formed in the additive region 134. Furthermore, when the insulating film 132 contains silicon oxynitride (SiON), an electron trap level is also formed in the insulating film 132. In such a configuration, a tunnel current is generated every time a write operation and an erase operation are repeated, and electrons are accumulated in the additive region 134 and the insulating film 132 at a height position corresponding to the insulating layer 101. This may make it impossible to suitably control the threshold voltage of the memory cell MC. Furthermore, the current flowing through the semiconductor layer 120 decreases.

[0095] Therefore, in the third embodiment, a portion of the additive region 335 provided at a height position corresponding to the insulating layer 101 and a portion 333b of the insulating film 333 are separated from the semiconductor layer 120. This makes it possible to suppress tunneling of electrons from the semiconductor layer 120 and suppress deterioration of the threshold voltage characteristics caused by an increase in the number of write / erase operations. Also, it is possible to suppress a decrease in the current flowing through the semiconductor layer 120.

[0096] [Manufacturing method] A method for manufacturing the semiconductor memory device according to the third embodiment will now be described with reference to Figures 19 to 23. Figures 19 to 23 are schematic cross-sectional views for explaining the manufacturing method.

[0097] In manufacturing the semiconductor memory device according to the third embodiment, for example, the steps up to the step described with reference to FIG. 14 out of the manufacturing steps of the semiconductor memory device according to the first embodiment are performed.

[0098] 19, a part of the insulating layer 101 is removed through the memory hole MH. This step is performed by, for example, a method such as wet etching.

[0099] 20, an insulating film 334, a ferroelectric film 332, and an insulating film 333 are formed on the inner circumferential surface of the memory hole MH. This step is performed by a method such as CVD or ALD.

[0100] Next, the memory holes MH are filled with an insulating member 331A as shown in Fig. 21. This process is performed by a method such as CVD.

[0101] 22, a part of the insulating member 331A is removed. In this step, the part 333a of the insulating film 333 is exposed to the inside of the memory hole MH. Also, the insulating member 331A is divided into a plurality of insulating members 331 arranged in the Z direction. This step is performed by a method such as RIE.

[0102] Next, a semiconductor layer 120 is formed inside the memory hole MH as shown in Fig. 23. This process is performed by a method such as CVD.

[0103] Thereafter, a groove is formed by RIE or the like at a position corresponding to the electrode 140 described with reference to FIG. 3, the sacrificial layer 110A is removed by wet etching or the like through this groove, and the conductive layer 110 is formed by CVD or the like, thereby manufacturing a structure such as that described with reference to FIG. 18.

[0104] [Fourth embodiment] [composition] Next, a semiconductor memory device according to a fourth embodiment will be described with reference to Fig. 24. Fig. 24 is a schematic cross-sectional view showing a configuration of a portion of the semiconductor memory device according to the fourth embodiment.

[0105] The semiconductor memory device according to the fourth embodiment is basically configured in the same manner as the semiconductor memory device according to the third embodiment. However, the semiconductor memory device according to the fourth embodiment includes a gate insulating film 430 instead of the gate insulating film 330. The gate insulating film 430 is basically configured in the same manner as the gate insulating film 130. However, the gate insulating film 430 includes a ferroelectric film 432 instead of the ferroelectric film 332.

[0106] The ferroelectric film 432 is basically configured in the same manner as the ferroelectric film 332. However, the ferroelectric film 432 includes a plurality of additive regions 435 provided at a height position corresponding to the conductive layer 110 and including the inner circumferential surface of the ferroelectric film 432, and a memory region 436 provided between the plurality of additive regions 435 and the conductive layer 110.

[0107] The multiple additive regions 435 are basically configured in the same manner as the additive region 335. However, the multiple additive regions 435 are spaced apart from each other in the Z direction and aligned in the Z direction corresponding to the conductive layer 110. Each of the additive regions 435 has a substantially annular shape.

[0108] The memory region 436 is basically configured in the same manner as the memory region 336. However, the inner and outer diameters of a portion 436b of the memory region 436 provided at a height position corresponding to the insulating layer 101 are larger than the inner and outer diameters of a portion 436a of the memory region 436 provided at a height position corresponding to the conductive layer 110, respectively.

[0109] That is, the memory region 436 includes a plurality of portions 436a provided at a plurality of height positions corresponding to a plurality of conductive layers 110, and a plurality of portions 436b provided at a plurality of height positions corresponding to a plurality of insulating layers 101. The inner diameter of the plurality of portions 436b is larger than the inner diameter of the plurality of portions 436a. The outer diameter of the plurality of portions 436b is larger than the outer diameter of the plurality of portions 436a.

[0110] Here, the portion 436a is in contact with the additive region 435. Therefore, the crystal structure in the portion 436a is controlled by the additive region 435 and mainly includes a rectangular crystal. This allows the portion 436a to exhibit ferroelectric properties. On the other hand, the portion 436b is not in contact with the additive region 435. Therefore, the crystal structure in the portion 436b mainly includes a crystal structure other than a rectangular crystal. Therefore, the portion 436b does not exhibit ferroelectric properties.

[0111] [effect] The semiconductor memory device according to the fourth embodiment can achieve the same effects as the semiconductor memory device according to the third embodiment.

[0112] Moreover, with this configuration, it is possible to divide the region exhibiting ferroelectricity in the Z direction for each memory cell MC, thereby making it possible to suppress polarization inversion in the portion of the ferroelectric film 432 provided at a height position corresponding to the insulating layer 101.

[0113] [Manufacturing method] A method for manufacturing the semiconductor memory device according to the fourth embodiment will now be described with reference to Figures 25 to 29. Figures 25 to 29 are schematic cross-sectional views for explaining the manufacturing method.

[0114] In manufacturing the semiconductor memory device according to the fourth embodiment, for example, the steps up to the step described with reference to FIG. 19 out of the manufacturing steps of the semiconductor memory device according to the third embodiment are performed.

[0115] 25, for example, on the inner circumferential surface of the memory hole MH, an insulating film 334, a ferroelectric film 432A, and an insulating film 333 are formed. This step is performed by a method such as CVD or ALD.

[0116] 26, the memory holes MH are filled with an insulating member 331A. This process is performed by a method such as CVD.

[0117] 27, a part of the insulating member 331A is removed. In this process, the part 333a of the insulating film 333 is exposed to the inside of the memory hole MH. Also, the insulating member 331A is divided into a plurality of insulating members 331 arranged in the Z direction.

[0118] 28, a second additive element is added to the ferroelectric film 432A through the insulating film 333. As a result, a plurality of additive regions 435 are formed.

[0119] In the example of FIG. 28, an insulating member 331 containing silicon oxide (SiO2) and an insulating film 333 containing silicon oxynitride (SiON) are exposed inside the memory hole MH. Here, a second additive element such as titanium (Ti) is difficult to adhere to silicon oxide (SiO2) and easily adheres to silicon oxynitride (SiON). Therefore, an additive region 435 is formed in a portion of the ferroelectric film 432A that is not covered by the insulating member 331 (a portion provided at a height position corresponding to the sacrificial layer 110A). On the other hand, an additive region is not formed in a portion of the ferroelectric film 432A that is covered by the insulating member 331 (a portion provided at a height position corresponding to the insulating layer 101).

[0120] Next, the semiconductor layer 120 is formed inside the memory hole MH as shown in Fig. 29. This process is performed by a method such as CVD.

[0121] Thereafter, a groove is formed by RIE or the like at a position corresponding to the electrode 140 described with reference to FIG. 3, the sacrificial layer 110A is removed by wet etching or the like through this groove, and a conductive layer 110 is formed by CVD or the like, thereby manufacturing a structure such as that described with reference to FIG. 24.

[0122] [Fifth embodiment] [composition] Next, a semiconductor memory device according to a fifth embodiment will be described with reference to Fig. 30. Fig. 30 is a schematic cross-sectional view showing a configuration of a portion of the semiconductor memory device according to the fifth embodiment.

[0123] The semiconductor memory device according to the fifth embodiment is basically configured in the same manner as the semiconductor memory device according to the fourth embodiment. However, the semiconductor memory device according to the fifth embodiment includes a gate insulating film 530 instead of the gate insulating film 430. The gate insulating film 530 is basically configured in the same manner as the gate insulating film 430. However, the gate insulating film 530 includes an insulating film 533 instead of the insulating film 333.

[0124] The insulating film 533 is basically configured in the same manner as the insulating film 333. However, the insulating film 533 includes a plurality of portions 533a and a plurality of portions 533b instead of the plurality of portions 333a and a plurality of portions 333b. The plurality of portions 533a and a plurality of portions 533b are basically configured in the same manner as the plurality of portions 333a and a plurality of portions 333b, respectively. However, the portion 533a includes, for example, silicon oxynitride (SiON) or the like. The portion 533b includes, for example, silicon nitride (SiN) or the like.

[0125] [effect] The semiconductor memory device according to the fifth embodiment can achieve the same effects as the semiconductor memory device according to the fourth embodiment.

[0126] [Manufacturing method] A method for manufacturing the semiconductor memory device according to the fifth embodiment will now be described with reference to Figures 31 to 33. Figures 31 to 33 are schematic cross-sectional views for explaining the manufacturing method.

[0127] In manufacturing the semiconductor memory device according to the fifth embodiment, for example, the steps up to the step described with reference to FIG. 19 out of the manufacturing steps of the semiconductor memory device according to the fourth embodiment are performed.

[0128] 31, an insulating film 334, a ferroelectric film 432A, and an insulating film 533A are formed on the inner circumferential surface of the memory hole MH. The insulating film 533A includes, for example, silicon nitride (SiN) or the like. This step is performed by, for example, a method such as CVD.

[0129] Next, for example, among the manufacturing steps of the semiconductor memory device according to the fourth embodiment, the steps described with reference to Figures 21 and 22 are carried out. As a result, a structure as shown in Figure 32 is formed.

[0130] 33, the insulating film 533 is formed. In this step, the surface of the insulating film 533A exposed to the memory holes MH is oxidized by, for example, thermal oxidation or other method, thereby forming a plurality of portions 533a. In this way, the insulating film 533 is formed.

[0131] Thereafter, for example, by performing the steps subsequent to the step described with reference to FIG. 28 among the manufacturing steps of the semiconductor memory device according to the fourth embodiment, a structure such as that described with reference to FIG. 30 is manufactured.

[0132] [Sixth embodiment] [composition] Next, a semiconductor memory device according to a sixth embodiment will be described with reference to Fig. 34. Fig. 34 is a schematic cross-sectional view showing a configuration of a portion of the semiconductor memory device according to the sixth embodiment.

[0133] The semiconductor memory device according to the sixth embodiment is basically configured similarly to the semiconductor memory device according to the first embodiment. However, the semiconductor memory device according to the sixth embodiment includes a gate insulating film 630 instead of the gate insulating film 130.

[0134] The gate insulating film 630 is basically configured in the same manner as the gate insulating film 130 .

[0135] However, the outer diameter of the portion of gate insulating film 630 provided at a height position corresponding to insulating layer 101 is larger than the outer diameter of the portion provided at a height position corresponding to conductive layer 110 .

[0136] The gate insulating film 630 also includes a plurality of insulating members 631 arranged in the Z direction corresponding to the plurality of insulating layers 101, a ferroelectric film 632 extending in the Z direction along the plurality of insulating members 631 and the semiconductor layer 120 over a Z-direction range corresponding to the plurality of conductive layers 110, a substantially cylindrical insulating film 132 extending in the Z direction along the inner surface of the ferroelectric film 632 over a Z-direction range corresponding to the plurality of conductive layers 110, and an insulating film 334 extending in the Z direction along the outer surface of the ferroelectric film 632 over a Z-direction range corresponding to the plurality of conductive layers 110.

[0137] The insulating member 631 includes a material, such as silicon oxide (SiO2), having a larger EOT (Equivalent Oxide Thickness) than the ferroelectric film 632 and a lower dielectric constant than the ferroelectric film 632. The insulating member 631 has a substantially annular shape. The film thickness (radial length) of the insulating member 631 may be, for example, 1 nm or more. The film thickness of the insulating member 631 may be defined as the distance between the surface of the insulating member 631 on the semiconductor layer 120 side and the surface of the insulating member 631 on the conductive layer 110 side.

[0138] The ferroelectric film 632 is basically configured in the same manner as the ferroelectric film 131. However, the outer diameter of a portion 632b of the ferroelectric film 632 provided at a height position corresponding to the insulating layer 101 is larger than the outer diameter of a portion 632a of the ferroelectric film 632 provided at a height position corresponding to the conductive layer 110.

[0139] That is, the ferroelectric film 632 includes a plurality of portions 632a provided at a plurality of height positions corresponding to the plurality of conductive layers 110, and a plurality of portions 632b provided at a plurality of height positions corresponding to the plurality of insulating layers 101. The inner diameter of the plurality of portions 632b is approximately the same as the inner diameter of the plurality of portions 632a. The outer diameter of the plurality of portions 632b is larger than the outer diameter of the plurality of portions 632a.

[0140] The portion 632a mainly contains orthorhombic crystals and exhibits ferroelectric properties. On the other hand, the portion 632b mainly contains a crystal structure other than orthorhombic crystals and does not exhibit ferroelectric properties. Each of the multiple portions 632b is divided by the insulating member 631 into two portions aligned in the radial direction.

[0141] Moreover, the ferroelectric film 632 includes a region 633 provided on the inner circumferential surface side of the ferroelectric film 632, and a region 634 provided on the outer circumferential surface side of the ferroelectric film 632. The region 634 is a region of the ferroelectric film 632 that is formed in a process to be described later with reference to Fig. 35. The region 633 is a region of the ferroelectric film 632 that is formed in a process to be described later with reference to Fig. 39.

[0142] The region 633 has a generally cylindrical shape extending in the Z direction along the outer circumferential surface of the semiconductor layer 120 over a range in the Z direction corresponding to the plurality of conductive layers 110 .

[0143] Region 634 extends in the Z direction along the outer circumferential surfaces of region 633 and insulating member 631 over a range in the Z direction corresponding to the plurality of conductive layers 110. Furthermore, the inner and outer diameters of a portion of region 634 provided at a height position corresponding to insulating layer 101 are larger than the inner and outer diameters of a portion provided at a height position corresponding to conductive layer 110, respectively.

[0144] In addition, the distance from the inner circumferential surface (surface on the semiconductor layer 120 side) of the multiple portions of the region 634 corresponding to the multiple insulating layers 101 to the region 633 is greater than the distance from the inner circumferential surface (surface on the semiconductor layer 120 side) of the multiple portions corresponding to the multiple conductive layers 110 to the region 633. For example, in the illustrated example, the multiple portions corresponding to the multiple conductive layers 110 are each connected to the outer circumferential surface of the region 633, and the distance from the inner circumferential surface of the multiple portions corresponding to the multiple conductive layers 110 to the region 633 is zero. On the other hand, the multiple portions corresponding to the multiple insulating layers 101 are each spaced apart from the region 633, and therefore the distance is not zero.

[0145] Furthermore, the thickness (radial length) of each of the regions 633 and 634 may be less than 8 nm. Furthermore, the total thickness of the regions 633 and 634 may be 8 nm or more. In this case, the thickness of the portion 632a of the ferroelectric film 632 is 8 nm or more. On the other hand, the portion 632b of the ferroelectric film 632 is divided into two portions each having a thickness of less than 8 nm.

[0146] The thickness (radial length) of the region 633 and the region 634 can be defined by various methods. For example, in this embodiment, the distance between the insulating member 631 and the surface of the ferroelectric film 632 on the semiconductor layer 120 side may be defined as the thickness of the region 633. Also, the distance between the insulating member 631 and the surface of the ferroelectric film 632 on the conductive layer 110 side may be defined as the thickness of the region 634.

[0147] [effect] 4, in the first embodiment, the ferroelectric film 131 is formed in a substantially cylindrical shape. In such a configuration, for example, during a write operation or an erase operation, due to a fringe electric field of the conductive layer 110, polarization inversion may occur in a portion of the ferroelectric film 131 provided at a height position corresponding to the insulating layer 101 or an adjacent word line WL (a word line WL adjacent to the selected word line WL in the Z direction).

[0148] Therefore, in the sixth embodiment, an insulating member 631 having an EOT larger than that of the ferroelectric film 632 is provided at a height position of the gate insulating film 630 corresponding to the insulating layer 101. With this configuration, the electric field lines from the conductive layer 110 reach the semiconductor layer 120 while avoiding the insulating layer 101, so that it is possible to suppress polarization inversion in the portion of the ferroelectric film 632 provided at a height position corresponding to the insulating layer 101 and the adjacent word line WL.

[0149] In the sixth embodiment, the thickness of the portion of the ferroelectric film 632 provided at a height position corresponding to the conductive layer 110 may be 8 nm or more. The portion of the ferroelectric film 632 provided at a height position corresponding to the insulating layer 101 may be divided into two portions having a thickness of less than 8 nm (for example, 5 nm or less). As described above, the ferroelectric film is likely to exhibit ferroelectricity when it has a thickness of 8 nm or more, and is unlikely to exhibit ferroelectricity when it has a thickness of less than 8 nm. In particular, when the thickness of the ferroelectric film is 5 nm or less, the ferroelectric film is likely to exhibit ferroelectricity. Therefore, with this configuration, it is possible to divide the region exhibiting ferroelectricity in the Z direction for each memory cell MC. This makes it possible to suppress polarization inversion in the portion of the ferroelectric film 632 provided at a height position corresponding to the insulating layer 101.

[0150] [Manufacturing method] A method for manufacturing the semiconductor memory device according to the sixth embodiment will now be described with reference to Figures 35 to 39. Figures 35 to 39 are schematic cross-sectional views for explaining the manufacturing method.

[0151] In manufacturing the semiconductor memory device according to the sixth embodiment, for example, the steps up to the step described with reference to FIG. 19 out of the manufacturing steps of the semiconductor memory device according to the third embodiment are performed.

[0152] 35, an insulating film 334 and a region 634 of a ferroelectric film 632 are formed on the inner circumferential surface of the memory hole MH. This step is performed by a method such as CVD or ALD.

[0153] Next, an insulating member 632A is formed on the inner circumferential surface of the memory hole MH as shown in Fig. 36. This step is performed by a method such as CVD.

[0154] 37, a part of the insulating member 631A is removed. In this step, a part of the region 634 that is provided at a height position corresponding to the sacrificial layer 110A is exposed inside the memory hole MH. Also, the insulating member 631A is divided into a plurality of insulating members 631 arranged in the Z direction. This step is performed by, for example, a method such as wet etching.

[0155] 38, a region 633 of a ferroelectric film 632 is formed inside the memory hole MH. This step is performed by a method such as CVD.

[0156] Next, for example, as shown in Fig. 39, an insulating film 132 and a semiconductor layer 120 are formed inside the memory hole MH. This process is performed by, for example, a method such as CVD.

[0157] Thereafter, a groove is formed by RIE or the like at a position corresponding to the electrode 140 described with reference to FIG. 3, the sacrificial layer 110A is removed by wet etching or the like through this groove, and a conductive layer 110 is formed by CVD or the like, thereby manufacturing a structure such as that described with reference to FIG. 34.

[0158] [Seventh embodiment] As described with reference to FIG. 34, in the sixth embodiment, the regions 633 and 634 in the ferroelectric film 632 are connected to each other at a plurality of height positions corresponding to the plurality of conductive layers 110. However, this configuration is merely an example, and the specific configuration can be appropriately adjusted. For example, the regions 633 and 634 may be spaced apart from each other. Hereinafter, such a configuration will be exemplified as a semiconductor memory device according to the seventh embodiment.

[0159] [composition] FIG. 40 is a schematic cross-sectional view showing a configuration of a portion of the semiconductor memory device according to the seventh embodiment.

[0160] The semiconductor memory device according to the seventh embodiment is basically configured in the same manner as the semiconductor memory device according to the sixth embodiment. However, the semiconductor memory device according to the seventh embodiment includes a gate insulating film 730 instead of the gate insulating film 630. The gate insulating film 730 is basically configured in the same manner as the gate insulating film 630. However, the gate insulating film 630 includes a ferroelectric film 732 instead of the ferroelectric film 632.

[0161] The ferroelectric film 732 is basically configured in the same manner as the ferroelectric film 632. However, the outer diameter of a portion 732b of the ferroelectric film 732 provided at a height position corresponding to the insulating layer 101 is larger than the outer diameter of a portion 732a of the ferroelectric film 732 provided at a height position corresponding to the conductive layer 110.

[0162] That is, the ferroelectric film 732 includes a plurality of portions 732a provided at a plurality of height positions corresponding to the plurality of conductive layers 110, and a plurality of portions 732b provided at a plurality of height positions corresponding to the plurality of insulating layers 101. The inner diameter of the plurality of portions 732b is approximately the same as the inner diameter of the plurality of portions 732a. The outer diameter of the plurality of portions 732b is larger than the outer diameter of the plurality of portions 732a.

[0163] The portion 732a mainly contains orthogonal crystals and exhibits ferroelectric properties, whereas the portion 732b mainly contains a crystal structure other than orthogonal crystals and does not exhibit ferroelectric properties.

[0164] The ferroelectric film 732 also includes a plurality of additive regions 731 arranged in the Z direction corresponding to the plurality of conductive layers 110 and provided between the regions 633 and 634 .

[0165] The additive region 731 includes at least one additive element selected from the group consisting of titanium (Ti) and silicon (Si) in addition to the first additive element described above. Hereinafter, such an additive element may be referred to as a "fourth additive element."

[0166] In this embodiment, the regions 633, 634 may or may not contain a fourth additive element in addition to the first additive element described above. When the regions 633, 634 contain the fourth additive element, the concentration of the fourth additive element in the regions 633, 634 is lower than the concentration of the fourth additive element in the additive region 731. When the regions 633, 634 contain the fourth additive element, the boundary between the regions 633, 634 and the additive region 731 may be, for example, a position where the concentration of the fourth additive element is half of the peak value. When the regions 633, 634 do not contain the fourth additive element, the boundary between the regions 633, 634 and the additive region 731 may be, for example, a boundary between a region containing the fourth additive element and a region not containing the fourth additive element, or a boundary between a region where the fourth additive element can be detected and a region where the fourth additive element cannot be detected.

[0167] Also in the seventh embodiment, the distance from the inner circumferential surface (surface on the semiconductor layer 120 side) of the multiple portions of region 634 corresponding to the multiple insulating layers 101 to region 633 is greater than the distance from the inner circumferential surface (surface on the semiconductor layer 120 side) of the multiple portions corresponding to the multiple conductive layers 110 to region 633. However, the multiple portions corresponding to the multiple conductive layers 110 are separated from region 633 via additive region 731. Therefore, the distance from the inner circumferential surface of the multiple portions corresponding to the multiple conductive layers 110 to region 633 is not zero.

[0168] [Wake-up operation] In the seventh embodiment, the regions 633 and 634 of the ferroelectric film 732 are divided in the radial direction of the semiconductor layer 120 via the additive region 731. Here, for example, when the thicknesses of the regions 633 and 634 are less than 8 nm, the ferroelectric film 732 tends not to exhibit ferroelectricity. In such a case, for example, it is considered to perform a wake-up operation before shipping the semiconductor memory device.

[0169] The wake-up operation is an operation in which a positive voltage and a negative voltage are alternately supplied multiple times between the semiconductor layer 120 and the conductive layer 110, thereby causing the ferroelectric film 732 to exhibit ferroelectricity. At this time, the absolute values ​​of the positive voltage and the negative voltage supplied between the semiconductor layer 120 and the conductive layer 110 are respectively equal to the write voltage V described with reference to FIG. PGM and erase voltage V era is greater than the absolute value of

[0170] When the wake-up operation is performed, an electric field is applied to the portion 732a of the ferroelectric film 732, and the characteristics of the portion 732a change. After the wake-up operation is performed, the portion 732a of the ferroelectric film 732 mainly contains orthogonal crystals and exhibits ferroelectricity. For example, after the wake-up operation is performed, in the portion 732a, an area in which the angle difference between the direction of the polarization axis and the electric field direction (the radial direction of the semiconductor layer 120) is 45° or less occupies 75% or more of the entire portion.

[0171] Here, the gate insulating film 730 according to the seventh embodiment includes a plurality of insulating members 631 arranged in the Z direction, similar to the gate insulating film 630 according to the sixth embodiment. Therefore, even during the wake-up operation, the electric field lines from the conductive layer 110 reach the semiconductor layer 120, avoiding the insulating layer 101. Therefore, no electric field is applied to the portion 732b of the ferroelectric film 732, and the characteristics of the portion 732b do not change. Therefore, even after the wake-up operation is performed, the portion 732b mainly includes a crystal structure other than a rectangular crystal, and does not exhibit ferroelectricity.

[0172] [effect] In the semiconductor memory device of the seventh embodiment, as in the semiconductor memory device of the sixth embodiment, it is possible to suppress polarization inversion in the portion of the ferroelectric film 732 that is located at a height position corresponding to the insulating layer 101 or the adjacent word line WL.

[0173] Furthermore, in the semiconductor memory device according to the seventh embodiment, the crystal structure of the portion 732a of the ferroelectric film 732 is modified by a wake-up operation, thereby exhibiting ferroelectricity. The structure formed by such a method is less likely to deteriorate in characteristics even when write and erase operations are repeatedly performed. Therefore, the semiconductor memory device according to the seventh embodiment can extend the life of the semiconductor memory device.

[0174] [Manufacturing method] A method for manufacturing the semiconductor memory device according to the seventh embodiment will now be described with reference to Figures 41 to 43. Figures 41 to 43 are schematic cross-sectional views for explaining the manufacturing method.

[0175] In manufacturing the semiconductor memory device according to the seventh embodiment, for example, the steps up to the step described with reference to FIG. 37 out of the manufacturing steps of the semiconductor memory device according to the sixth embodiment are performed.

[0176] 41, for example, a fourth additive element is added to the region 634 of the ferroelectric film 732 through the memory hole MH. As a result, an additive region 731 of the ferroelectric film 732 is formed.

[0177] 42, a region 633 of the ferroelectric film 732 is formed inside the memory hole MH. This step is performed by a method such as CVD or ALD.

[0178] 43, the insulating film 132 and the semiconductor layer 120 are formed inside the memory hole MH. This process is performed by, for example, a method such as CVD.

[0179] Thereafter, a groove is formed by RIE or the like at a position corresponding to the electrode 140 described with reference to FIG. 3, the sacrificial layer 110A is removed by wet etching or the like through this groove, and a conductive layer 110 is formed by CVD or other means, thereby manufacturing a structure such as that described with reference to FIG. 40.

[0180] [Other embodiments] The semiconductor memory devices according to the first to seventh embodiments have been described above. However, the above description is merely an example, and the specific configurations and the like can be appropriately adjusted.

[0181] For example, in the first to seventh embodiments, the semiconductor layer 120 has been described as having a substantially cylindrical configuration. However, the semiconductor layer 120 may have a substantially cylindrical configuration, for example. Also, an insulating film such as silicon oxide (SiO2) may be embedded in the center of the semiconductor layer 120.

[0182] Also, for example, an additive region containing the second additive element (a region corresponding to the additive region 135 in FIG. 4) may be provided on the outer circumferential surface or in the vicinity of the ferroelectric film 332 (FIG. 18), the ferroelectric film 432 (FIG. 24), the ferroelectric film 632 (FIG. 34), and the ferroelectric film 732 (FIG. 40) as in the first embodiment, or a region not containing the second additive element (a region corresponding to the region 235 in FIG. 16) and an additive region containing the second additive element provided on the inner circumferential side thereof (a region corresponding to the additive region 236 in FIG. 16) may be provided as in the second embodiment.

[0183] According to this configuration, like the semiconductor memory device according to the first embodiment and the semiconductor memory device according to the second embodiment, it is possible to suppress the occurrence of erroneous writing accompanying the execution of a read operation.

[0184] Moreover, the gate insulating film 630 (FIG. 34) and the gate insulating film 730 (FIG. 40) may include a plurality of insulating members 331 and an insulating film 333 instead of the insulating film 132.

[0185] According to this configuration, similarly to the semiconductor memory device according to the third embodiment and the semiconductor memory device according to the fourth embodiment, it is possible to suppress the degradation of the threshold voltage characteristics caused by the increase in the number of write / erase operations, and also to suppress the decrease in the current flowing through the semiconductor layer 120.

[0186] As described above, the portion of the ferroelectric film 632 (FIG. 34) provided at a height position corresponding to the insulating layer 101 is divided into two parts having a relatively small thickness via the insulating member 631. Here, the portion of the ferroelectric film 632 (FIG. 34) provided at a height position corresponding to the insulating layer 101 may be divided into three or more parts.

[0187] To manufacture such a configuration, for example, in the process described with reference to FIG. 37, a large amount of the insulating member 631A is removed to form a step between the insulating member 631 and a part (region 634) of the ferroelectric film 632. Also, in the process described with reference to FIG. 38, a part of the ferroelectric film 632 is formed thin enough to maintain the step. Next, the insulating member 631A (FIG. 36) is formed again inside the memory hole MH. Thereafter, similar processes are repeatedly performed.

[0188] [others] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0189] 101...insulating layer, 110...conductive layer, 120...semiconductor layer, 130...gate insulating film, 131...ferroelectric film, 132, 133...insulating films (interface layers), 134, 135...additive regions, 136...memory region.

Claims

1. A semiconductor layer; a gate electrode facing the semiconductor layer; a first insulating film provided between the semiconductor layer and the gate electrode, containing oxygen (O), hafnium (Hf) and a first additive element and having a rectangular crystal structure; a second insulating film provided between the first insulating film and the gate electrode; Equipped with The first insulating film is A first additive region; a second doped region provided between the first doped region and the gate electrode; a memory region provided between the first additive region and the second additive region; Equipped with The first additive region includes at least one second additive element selected from the group consisting of ruthenium (Ru), titanium (Ti), molybdenum (Mo), tantalum (Ta), tungsten (W), and platinum (Pt); The second additive region includes at least one third additive element selected from the group consisting of ruthenium (Ru), titanium (Ti), molybdenum (Mo), tantalum (Ta), tungsten (W), and platinum (Pt); The memory region does not include the second additive element, or the concentration of the second additive element in the memory region is lower than the concentration of the second additive element in the first additive region; The memory region does not include the third additive element, or the concentration of the third additive element in the memory region is lower than the concentration of the third additive element in the second additive region. Semiconductor memory device.

2. The first insulating film contains at least one of the first additive elements selected from the group consisting of silicon (Si), zirconium (Zr), aluminum (Al), yttrium (Y), strontium (Sr), lanthanum (La), samarium (Sm), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), ytterbium (Yb), lutetium (Lu), and barium (Ba).

2. The semiconductor memory device according to claim 1.

3. the first dopant region includes a surface of the first insulating film on the semiconductor layer side, The second doped region includes a surface of the first insulating film on the gate electrode side.

2. The semiconductor memory device according to claim 1.

4. the first insulating film includes a region provided between the second doped region and the gate electrode; the first dopant region includes a surface of the first insulating film on the semiconductor layer side, The region includes a surface of the first insulating film on the gate electrode side.

2. The semiconductor memory device according to claim 1.

5. The concentration of the second additive element in the first additive region is 6.2×10 ２１ pieces / cm ３ is as follows: The concentration of the third additive element in the second additive region is 6.2×10 ２１ pieces / cm ３ is less than or equal to 2. The semiconductor memory device according to claim 1.

6. The distance between the first doped region and the second doped region is 8 nm or more.

2. The semiconductor memory device according to claim 1.

7. A plurality of conductive layers and a plurality of insulating layers alternately stacked in a stacking direction; a semiconductor layer extending in the stacking direction and facing the plurality of conductive layers; an insulating film provided between the plurality of conductive layers and the semiconductor layer, extending in the stacking direction, containing oxygen (O) and hafnium (Hf), and having a rectangular crystal structure; an interface layer provided between the insulating film and the semiconductor layer and extending in the stacking direction; Equipped with The interface layer is a plurality of first portions provided at a plurality of positions corresponding to the plurality of conductive layers in the stacking direction; a plurality of second portions provided at a plurality of positions corresponding to the plurality of insulating layers in the stacking direction; Equipped with A distance from the second portions to the semiconductor layer is greater than a distance from the first portions to the semiconductor layer. Semiconductor memory device.

8. a difference between a distance from the second portions to the semiconductor layer and a distance from the first portions to the semiconductor layer is 2 nm or more; 8. The semiconductor memory device according to claim 7.

9. The insulating film is a plurality of third portions provided at a plurality of positions corresponding to the plurality of conductive layers in the stacking direction; a plurality of fourth portions provided at a plurality of positions corresponding to the plurality of insulating layers in the stacking direction; Equipped with A distance from the plurality of fourth portions to the semiconductor layer is greater than a distance from the plurality of third portions to the semiconductor layer.

8. The semiconductor memory device according to claim 7.

10. a plurality of insulating members arranged along a surface of the semiconductor layer on the side of the plurality of conductive layers and in the stacking direction corresponding to the plurality of insulating layers; the interface layer extends in the stacking direction along surfaces of the semiconductor layer and the insulating members on the conductive layer side; The insulating film extends in the stacking direction along a surface of the interface layer on the side of the conductive layers.

8. The semiconductor memory device according to claim 7.

11. The insulating film includes an additive region, The additive region includes at least one additive element selected from the group consisting of ruthenium (Ru), titanium (Ti), molybdenum (Mo), tantalum (Ta), tungsten (W), and platinum (Pt).

8. The semiconductor memory device according to claim 7.

12. The additive region extends in the stacking direction over a range in the stacking direction corresponding to the plurality of conductive layers.

12. The semiconductor memory device according to claim 11.

13. The additive regions are provided at a plurality of positions corresponding to the conductive layers in the stacking direction.

12. The semiconductor memory device according to claim 11.

14. The insulating film is a plurality of portions including an orthorhombic crystal structure, the portions being provided at a plurality of positions corresponding to the plurality of conductive layers in the stacking direction; a plurality of other portions that are provided at a plurality of positions corresponding to the plurality of insulating layers in the stacking direction and that have a structure that is not an orthorhombic crystal structure; 8. The semiconductor memory device according to claim 7, comprising:

15. A plurality of conductive layers and a plurality of insulating layers alternately stacked in a stacking direction; a semiconductor layer extending in the stacking direction and facing the plurality of conductive layers; an insulating film provided between the plurality of conductive layers and the semiconductor layer, extending in the stacking direction, containing oxygen (O) and hafnium (Hf), and having a rectangular crystal structure; Equipped with The insulating film is a first region extending in the stacking direction along a surface of the semiconductor layer on the side of the plurality of conductive layers; a second region provided between the first region and the plurality of conductive layers and extending in the stacking direction; Equipped with the first region and the second region are spaced apart from each other at a plurality of first positions in the stacking direction corresponding to the plurality of insulating layers; At a plurality of second positions in the stacking direction corresponding to the plurality of conductive layers, the first region and the second region are connected to each other, or a distance between the first region and the second region is smaller than a distance between the first region and the second region at the plurality of first positions. Semiconductor memory device.

16. a plurality of insulating members arranged along a surface of the first region on the side of the plurality of conductive layers and in the stacking direction corresponding to the plurality of insulating layers; The second region extends in the stacking direction along the first region and the surfaces of the insulating members on the conductive layer side.

16. The semiconductor memory device according to claim 15.

17. a first distance between the plurality of insulating members and a surface of the insulating film on the semiconductor layer side is 5 nm or less; A second distance between the insulating members and a surface of the insulating film facing the conductive layers is 5 nm or less.

17. The semiconductor memory device according to claim 16.

18. The sum of the first distance and the second distance is 8 nm or more.

18. The semiconductor memory device according to claim 17.

19. A distance between a surface of each of the insulating members facing the semiconductor layer and a surface of each of the insulating members facing the conductive layers is 1 nm or more.

17. The semiconductor memory device according to claim 16.

20. the insulating film includes a plurality of additive regions aligned in the stacking direction in correspondence with the plurality of conductive layers between the first region and the second region, The additive region includes at least one additive element selected from the group consisting of titanium (Ti) and silicon (Si); The first region and the second region do not contain the additive element, or the concentration of the additive element in the first region and the second region is lower than the concentration of the additive element in the additive region.

16. The semiconductor memory device according to claim 15.

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