Semiconductor circuit device and switching regulator

Abstract

To provide a semiconductor circuit device that, even when the output voltage of a differential amplifier circuit is reduced, can maintain the characteristics of the differential amplifier circuit in a switching regulator.SOLUTION: A semiconductor circuit device 100 includes: a current detection circuit 134 that converts inductor current IL into voltage and outputs the voltage as current detection voltage Vramp; a differential amplifier circuit 110 that amplifies the difference between voltage DVOUT corresponding to output voltage VOUT and reference voltage VREF; a level shifter 190; and a comparison circuit 133 that compares the current detection voltage Vramp with level-shifted voltage LV to output a switching signal CSWT for a switching device SWT. The differential amplifier circuit 110 has a MOS transistor provided between a power supply node and an output node NVC. The level shifter 190 level-shifts the voltage VC at the output node NVC of the differential amplifier circuit 110 to a low potential side and outputs the level-shifted voltage LV.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor circuit device, a switching regulator, and the like. [Background technology]

[0002] Patent Document 1 discloses a switching power supply device including a P-type transistor, an N-type transistor, a driver, a differential amplifier, a level shifter, a comparator, and an RS flip-flop. A reference voltage and a voltage obtained by dividing a voltage appearing at a connection node between a coil and a capacitor by a resistor are input to the differential amplifier. The level shifter shifts the level of the voltage from the differential amplifier to the power supply potential. The comparator compares the voltage from the level shifter with a voltage representing a current flowing through the coil. The RS flip-flop and the driver control the P-type transistor and the N-type transistor based on the output from the comparator, and the P-type transistor and the N-type transistor drive the coil. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2005 / 078910 Summary of the Invention [Problem to be solved by the invention]

[0004] When the output voltage of the differential amplifier circuit is low, the characteristics of the differential amplifier circuit may deteriorate, and the characteristics of the switching regulator may not be as designed. For example, when the switching regulator is under a light load or when the power supply is turned on, the output voltage of the differential amplifier circuit may become low, and the characteristics of the differential amplifier circuit may deteriorate. In the above-mentioned Patent Document 1, the level shifter shifts the output voltage of the differential amplifier to a higher level. Therefore, the output voltage of the differential amplifier becomes lower than when the level shifter is not provided, and the characteristics of the differential amplifier circuit may deteriorate. [Means for solving the problem]

[0005] One aspect of the present disclosure relates to a semiconductor circuit device used in a switching regulator that uses a switch element and an inductor to regulate an input voltage and output an output voltage, the semiconductor circuit device including: a current detection circuit that converts an inductor current flowing through the inductor into a voltage and outputs the voltage as a current detection voltage; a differential amplifier circuit having a MOS transistor provided between a power supply node and an output node and amplifying the difference between a voltage corresponding to the output voltage and a reference voltage; a level shifter that level-shifts the voltage of the output node of the differential amplifier circuit to a low potential side and outputs the level-shifted voltage; and a comparison circuit that compares the current detection voltage with the level-shifted voltage to output a switching signal for the switch element.

[0006] Another aspect of the present disclosure relates to a switching regulator including the above-described semiconductor circuit device and the inductor. [Brief description of the drawings]

[0007] [Figure 1] An example of a switching regulator configuration. [Diagram 2] A first detailed configuration example of a level shifter. [Diagram 3] A second detailed configuration example of the level shifter. [Figure 4] An example of waveforms that explains the drop in the voltage output by a differential amplifier circuit under PWM control. [Diagram 5] An example of waveforms that explains the drop in the voltage output by a differential amplifier circuit under PWM control. [Figure 6] An example of waveforms that explains the drop in the voltage output by the differential amplifier circuit under PFM control. [Figure 7] 2 shows a detailed configuration example of a differential amplifier circuit. [Figure 8] An example of the frequency characteristics of a switching regulator when the output stage transistors of a differential amplifier circuit are connected in cascode. [Figure 9] 3 shows a detailed configuration example of a switching signal output circuit. [Figure 10] An example of a signal waveform from a switching signal output circuit. [Figure 11] A detailed configuration example of an inductance current detection circuit. [Figure 12] Example of signal waveform of inductance current detection circuit. [Figure 13] 1 shows a detailed configuration example of a slope generation circuit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] A preferred embodiment of the present disclosure will be described in detail below. Note that the present embodiment described below does not unduly limit the contents described in the claims, and all of the configurations described in the present embodiment are not necessarily essential configurations. For example, a step-down switching regulator will be described below as an example, but the method of the present embodiment can also be applied to a step-up switching regulator.

[0009] 1. Switching regulator and semiconductor circuit device 1 shows an example of the configuration of a switching regulator. The switching regulator 200 includes a semiconductor circuit device 100, an inductor 210, and a capacitor 220.

[0010] The power supply 250 is connected between a low potential side power supply node to which a low potential side power supply VSS is supplied and an input node NH of the switching regulator 200. The power supply 250 generates an input voltage VH to be applied to the switching regulator 200. The power supply 250 may be either an AC / DC converter or a DC / DC converter. Note that the connection in this embodiment includes an electrical connection. An electrical connection means a connection capable of transmitting an electrical signal, a voltage, or a current, and includes a connection that enables the transmission of information by an electrical signal. The electrical connection may be a connection via a passive element, an active element, or the like.

[0011] One end of the inductor 210 is connected to the switch node NSW, and the other end is connected to the output node NOUT of the switching regulator 200. One end of the capacitor 220 is connected to the node NOUT, and the other end is connected to the low potential side power supply node. A current IL flowing through the inductor 210 is referred to as an inductor current.

[0012] A load 290 of the switching regulator 200 is provided between the output node NOUT and the low potential side power supply node. The load 290 is a circuit that uses the output voltage VOUT of the switching regulator 200 as a power supply voltage.

[0013] The semiconductor circuit device 100 controls the switching regulator 200 so that the output voltage VOUT of the switching regulator 200 becomes a predetermined voltage. The semiconductor circuit device 100 is an integrated circuit device in which a plurality of circuit elements are integrated on a semiconductor substrate. The semiconductor circuit device 100 includes a switch element SWT, a diode 160, resistors RA1 and RA2, a reference voltage generating circuit 140, a differential amplifier circuit 110, a phase compensation circuit 120, a level shifter 190, and a switching signal output circuit 130. The switch element SWT, the diode 160, the resistors RA1 and RA2, and the reference voltage generating circuit 140 may be provided outside the semiconductor circuit device 100.

[0014] The switch element SWT is a transistor, and is controlled to be on or off by a switching signal CSWT. Although Fig. 1 shows an example in which the switch element SWT is an N-type transistor, it may be a P-type transistor. The source of the switch element SWT is connected to the switch node NSW, and the drain is connected to the input node NH. The switching signal CSWT is input to the gate of the switch element SWT.

[0015] The anode of the diode 160 is connected to the low potential side power supply node, and the cathode is connected to the switch node NSW. Note that a switch element may be provided instead of the diode 160. The switch element is off when the switch element SWT is on, and is on when the switch element SWT is off.

[0016] One end of resistor RA1 is connected to the output node NOUT, and the other end is connected to the inverting input terminal of the differential amplifier circuit 110. One end of resistor RA2 is connected to the inverting input terminal of the differential amplifier circuit 110, and the other end is connected to the low potential side power supply node. Resistors RA1 and RA2 divide the output voltage VOUT to a voltage DVOUT.

[0017] The reference voltage generating circuit 140 is connected between the non-inverting input terminal of the differential amplifier circuit 110 and a low potential side power supply node. The reference voltage generating circuit 140 generates a reference voltage VREF for setting the voltage value of the output voltage VOUT. The output voltage VOUT is controlled by feedback control performed by the semiconductor circuit device 100 so that the voltage DVOUT is equal to the reference voltage VREF.

[0018] The differential amplifier circuit 110 converts the voltage difference between the voltage DVOUT and the reference voltage VREF into a current, converts the current into a voltage VC by the output impedance of the differential amplifier circuit 110, and outputs the voltage VC to an output node NVC. The differential amplifier circuit 110 is also called a transconductance amplifier, a Gm amplifier, or an error amplifier.

[0019] The phase compensation circuit 120 is a circuit that performs phase compensation for the feedback loop and includes a resistor RC, a first capacitor CC1, and a second capacitor CC2.

[0020] The resistor RC and the first capacitor CC1 are connected in series between the output node NVC of the differential amplifier circuit 110 and the low potential power supply node. One end of the resistor RC is connected to the output node NVC, and the other end is connected to one end of the first capacitor CC1. The other end of the first capacitor CC1 is connected to the low potential power supply node. One end of the second capacitor CC2 is connected to the output node NVC, and the other end is connected to the low potential power supply node.

[0021] The switching regulator 200 is divided into a compensator and a plant. The compensator is a part including resistors RA1 and RA2, a differential amplifier circuit 110, and a phase compensation circuit 120. The plant is a part including a switch element SWT, a switching signal output circuit 130, an inductor 210, a diode 160, a capacitor 220, and a load 290. When the output impedance of the differential amplifier circuit 110 is RO, the compensator has a zero point at a frequency ωzc1=1 / (RC×CC1), a first pole at a frequency ωpc1=1 / (RO×CC1), and a second pole at a frequency ωpc2=1 / (RC×CC2). The resistance value of the resistor RC and the capacitance value of the first capacitor CC1 are set so that the zero point of the compensator and the pole of the plant are approximately the same. As a result, the pole of the plant and the zero point of the compensator are cancelled, and the transfer function of the switching regulator 200 as a whole has a first pole at a frequency ωpc1 and a second pole at a frequency ωpc2. The frequencies of these poles are controlled by a compensator, so that the bandwidth and phase margin of the switching regulator 200 can be controlled by determining the circuit constants of the compensator.

[0022] The level shifter 190 is provided between the output node NVC of the differential amplifier circuit 110 and a node NLV. The level shifter 190 level-shifts the voltage VC output by the differential amplifier circuit 110 to the low potential side, and outputs the result as a level-shifted voltage LV to the node NLV. As described later with reference to FIG. 2 and FIG. 3, the level shifter 190 is, for example, a source follower circuit. However, the level shifter 190 may be any circuit capable of shifting the voltage to the low potential side. The voltage shift amount is, for example, about the threshold voltage of a transistor, but is not limited thereto, and may be any shift amount sufficiently smaller than the power supply voltage. The shift amount may be equal to or greater than the overdrive voltage when a transistor included in the output stage of the differential amplifier circuit 110 operates in a saturated state.

[0023] The switching signal output circuit 130 controls the switch element SWT to be on or off based on the voltage LV output by the level shifter 190 and the inductor current IL. The switching signal output circuit 130 includes a current detection circuit 134 and a comparison circuit 133.

[0024] The current detection circuit 134 outputs a voltage Vramp based on the inductor current IL. Specifically, the inductor current IL is converted into a voltage by the on-resistance of the switch element SWT. The switching signal output circuit 130 generates the voltage Vramp based on the potential difference between both ends of the switch element SWT. In the following, Vramp is also referred to as a current detection voltage.

[0025] The comparator circuit 133 compares the voltage LV from the level shifter 190 with the current detection voltage Vramp from the current detection circuit 134. The comparator circuit 133 controls the pulse width of the switching signal CSWT, which is a PWM signal, by this voltage comparison. PWM is an abbreviation for Pulse Width Modulation.

[0026] The current detection voltage Vramp may be generated based on, for example, a potential difference across a sense resistor inserted in series with the inductor 210. The switching signal output circuit 130 is not limited to PWM control, and may perform, for example, PFM control. That is, the switching signal output circuit 130 may control the pulse frequency of the switching signal CSWT, which is a PFM signal, based on the voltage LV and the inductor current IL. PFM is an abbreviation for Pulse Frequency Modulation.

[0027] 2 shows a first detailed configuration example of the level shifter 190. The level shifter 190 is a source follower circuit, and includes an N-type MOS transistor TNL and a resistor RL.

[0028] The drain of the N-type MOS transistor TNL is connected to the node of the internal power supply voltage VDD, and the source is connected to the node NLV. The internal power supply voltage VDD is generated by a regulator 170, which will be described later in FIG. 9. The gate of the N-type MOS transistor TNL is connected to the output node NVC of the differential amplifier circuit 110. That is, a voltage VC is input to the gate of the N-type MOS transistor TNL. One end of a resistor is connected to the node NLV, and the other end is connected to the low potential side power supply node.

[0029] 3 shows a second detailed configuration example of the level shifter. The level shifter 190 is a source follower circuit and includes an N-type MOS transistor TNL and a current source IBL. The differences from FIG. 2 will be described.

[0030] One end of the current source IBL is connected to the node NLV, and the other end is connected to the low potential power supply node. The current source IBL supplies a bias current from the node NLV to the low potential power supply node.

[0031] 2 and 3, the level shifter 190 shifts the voltage VC output by the differential amplifier circuit 110 to the lower potential side by the threshold voltage of the N-type MOS transistor TNL, and outputs the result as a level-shifted voltage LV.

[0032] 4 and 5 are waveform examples illustrating a drop in the voltage output by the differential amplifier circuit in PWM control. In the following, a large load means that the current flowing through the load 290 is relatively large. A small load means that the current flowing through the load 290 is relatively small.

[0033] 4 shows an example of waveforms when the level shifter 190 is not provided. When the level shifter 190 is not provided, the voltage VC output by the differential amplifier circuit 110 is input to the switching signal output circuit .

[0034] As shown in FIG. 4, when the load changes from a heavy load state to a light load state, the output voltage VOUT of the switching regulator 200 tends to rise. The feedback control tries to keep the output voltage VOUT constant, so it tries to lower the output voltage VOUT. This causes the voltage VC to fall, and the duty of the switching signal CSWT to fall. Specifically, the output voltage VOUT tries to rise, so the voltage DVOUT obtained by dividing it also tries to rise. The voltage DVOUT is input to the inverting input node of the differential amplifier circuit 110, and the differential amplifier circuit 110 lowers the voltage VC by comparing it with the reference voltage VREF. The switching signal output circuit 130 lowers the inductor current IL by lowering the on-duty of the switch element SWT in response to the drop in the voltage VC. As a result, the current detection voltage Vramp based on the inductor current IL drops as the voltage VC drops. In this way, the feedback control is performed so that the inductor current IL is reduced when the load is light, and the output voltage VOUT is kept constant.

[0035] As described above, when the load is small, the voltage VC of the output node NVC of the differential amplifier circuit 110 tends to decrease. The MOS transistor included in the differential amplifier circuit 110 is assumed to operate in a saturated state. However, when the voltage VC of the output node NVC decreases, the overdrive voltage of the output stage transistor connected to the output node NVC cannot be secured, and the output stage transistor may not be able to operate in a saturated state. The overdrive voltage is the source-drain voltage required to operate the MOS transistor in the saturated region. For example, as will be described later in FIG. 7, when the output stage transistor of the differential amplifier circuit 110 is cascode-connected, it becomes even more difficult to secure the overdrive voltage, and the output stage transistor may not be able to operate in a saturated state.

[0036] When the output stage transistor of the differential amplifier circuit 110 cannot operate in a saturated state, for example, the DC gain of the differential amplifier circuit 110 becomes lower than when it operates in a saturated state. This causes a decrease in the DC gain of the entire feedback loop of the switching regulator 200. When the DC gain decreases, for example, the accuracy of the output voltage VOUT may decrease. For example, when the load fluctuates, the fluctuation of the output voltage VOUT may become larger than the design value.

[0037] Fig. 5 shows an example of waveforms in this embodiment when the level shifter 190 is provided. In Fig. 5, the amount of voltage shift by the level shifter 190 is denoted as ΔV.

[0038] In a state where the load is small, the post-level shift voltage LV, which is the input of the comparison circuit 133, decreases in the same manner as the voltage VC in FIG. 4. In the present embodiment, the voltage VC before the level shift, that is, the voltage VC output by the differential amplifier circuit 110, is a voltage that is higher than the post-level shift voltage LV by ΔV. Therefore, even if the post-level shift voltage LV decreases, it is easier to ensure a voltage VC that allows the output stage transistor of the differential amplifier circuit 110 to operate in the saturation state. For example, when the overdrive voltage of one MOS transistor is about 0.2V, the overdrive voltage is at most about 0.4V even if it is cascode-connected. Therefore, if the voltage shift amount ΔV is set to 0.4V or more, the output stage transistor of the differential amplifier circuit 110 can be operated in the saturation state.

[0039] The above is the case of PWM control. When the load becomes even smaller, the control shifts to PFM control. PFM is an abbreviation for Pulse Frequency Modulation. The shift to PFM control will be described later with reference to FIG. 9. FIG. 6 is an example of a waveform for explaining that the voltage output by the differential amplifier circuit decreases in PFM control. Here, an example of a waveform when the level shifter 190 is not provided is shown.

[0040] The clock signal CLK is, for example, a clock signal generated by an internal oscillation circuit (not shown). The comparison circuit 133 performs a comparison operation using the falling edge of the clock signal CLK as the comparison timing. Specifically, when Vramp < VC at the comparison timing, the comparison circuit 133 changes the switching signal CSWT from the low level to the high level to turn on the switch element SWT. When the current detection voltage Vramp reaches the voltage VC, the comparison circuit 133 changes the switching signal CSWT from the high level to the low level to turn off the switch element SWT. When the switch element SWT is on, the inductor current IL increases, and when the switch element SWT turns off, the inductor current IL converges. The output voltage VOUT increases as this inductor current IL charges the capacitor 220. When the output voltage VOUT increases, the differential amplifier circuit 110 decreases the voltage VC so that VC < Vramp.

[0041] As the load 290 discharges from the capacitor 220, the output voltage VOUT gradually decreases. However, since the load is small, the decrease in the output voltage VOUT is slow. Therefore, VC < Vramp is maintained at the next comparison timing. For this reason, at that comparison timing, the comparison circuit 133 does not perform the comparison operation, so the switch element SWT does not turn on. Then, at the comparison timing after the output voltage VOUT decreases and Vramp < VC, the switch element SWT turns on again. FIG. 6 shows an example in which the comparison operation is performed with Vramp < VC at intervals of 5 clocks. The interval during which the switch element SWT turns on, that is, the switching frequency, varies according to the magnitude of the load.

[0042] As described above, when the load is small and PFM control is performed, the voltage VC is likely to be maintained at a low level. For this reason, there is a high possibility that the output stage transistor of the differential amplifier circuit 110 cannot operate in the saturation state. According to the present embodiment, since the differential amplifier circuit 110 can increase the voltage VC output by ΔV, even in PFM control, the output stage transistor of the differential amplifier circuit 110 can be operated in the saturation state.

[0043] 2. Differential Amplifier Circuit FIG. 7 is a detailed configuration example of the differential amplifier circuit. FIG. 7 shows an example in which the output stage transistors of the differential amplifier circuit 110 are cascode-connected, but the output stage transistors do not have to be cascode-connected. Hereinafter, the N-type MOS transistor is referred to as an N-type transistor, and the P-type MOS transistor is referred to as a P-type transistor.

[0044] The differential amplifier circuit 110 includes a first differential pair transistor TND1, a second differential pair transistor TND2, output stage transistors TNQa, TNQb, TPQa, TPQb, P-type transistors TPD1 to TPD3, an N-type transistor TND3, and a current source circuit IBD. The power supply voltage of the differential amplifier circuit 110 is the internal power supply voltage VDD generated by the regulator 170 described later in FIG. 9.

[0045] The first differential pair transistor TND1 and the second differential pair transistor TND2 are N-type transistors and form a differential pair. A voltage DVOUT is input to the gate of the first differential pair transistor TND1, and a reference voltage VREF is input to the gate of the second differential pair transistor TND2. A current source circuit IBD causes a current to flow through the differential pair. The current flowing through the first differential pair transistor TND1 is defined as In, and the current flowing through the second differential pair transistor TND2 is defined as Ip.

[0046] 7, the differential amplifier circuit 110 includes current mirror circuits MCa and MCb. The current mirror circuit MCa mirrors the current In to a current flowing through an output stage transistor TNQa. The current mirror circuit MCa includes P-type transistors TPD1 and TPD2, and an N-type transistor TND3.

[0047] The current In flows through the P-type transistor TPD2. The P-type transistors TPD1 and TPD2 form a current mirror, and the current In flows through the P-type transistor TPD1. This current In flows through the N-type transistor TND3. The N-type transistor TND3 and the output stage transistor TNQa form a current mirror, and the current In flows through the output stage transistor TNQa.

[0048] The current mirror circuit MCb mirrors the current Ip to a current flowing through the output stage transistor TPQa. The current mirror circuit MCb includes a P-type transistor TPD3.

[0049] The current Ip flows through the P-type transistor TPD3. The P-type transistor TPD3 and the output stage transistor TPQa form a current mirror, and the current Ip flows through the output stage transistor TPQa.

[0050] The output stage transistors TNQa and TNQb are N-type transistors. The output stage transistor TNQa is provided between the low potential power supply node and the node Na. The output stage transistor TNQb is provided between the node Na and the output node NVC. The connection of the output stage transistors TNQa and TNQb can be said to be a so-called cascode connection.

[0051] A bias voltage VBa is input to the gate of the output stage transistor TNQb. For example, a voltage generation circuit (not shown) generates the bias voltage VBa. When the threshold voltage of an N-type transistor is Vthn, the bias voltage VBa=Vthn+2×Vovn. Vovn is the overdrive voltage of an N-type transistor. The overdrive voltage is the source-drain voltage required to operate a transistor in the saturation region. By setting VBa=Vthn+2×Vovn, the output stage transistors TNQa and TNQb operate in the saturation region when VC≧2×Vovn. As an example, Vovn is about 0.2V.

[0052] The output stage transistors TPQa and TPQb are P-type transistors. The output stage transistor TPQa is provided between a high potential power supply node and a node Nb. The output stage transistor TPQb is provided between the node Nb and an output node NVC. The connection of the output stage transistors TPQa and TPQb can be said to be a so-called cascode connection.

[0053] A bias voltage VBb is input to the gate of the output stage transistor TNQb. For example, a voltage generation circuit (not shown) generates the bias voltage VBb. When the threshold voltage of a P-type transistor is Vthp, the bias voltage VBb=Vthp+2×Vovp. Vovp is the overdrive voltage of a P-type transistor. By setting VBb=Vthp+2×Vovp, the output stage transistors TPQa and TPQb operate in the saturation region when VC≦VDD-2×Vovp. As an example, Vovp is about 0.2V.

[0054] The differential amplifier circuit 110 outputs a differential current IC=Ip-In between the current Ip flowing through the output stage transistors TPQa and TPQb and the current In flowing through the output stage transistors TNQa and TNQb. This differential current IC=Ip-In is converted to a voltage VC by the output impedance RO of the differential amplifier circuit 110. In other words, VC=IC×RO.

[0055] Figure 8 shows an example of the frequency characteristics of a switching regulator when the output stage transistors of a differential amplifier circuit are cascode-connected.

[0056] The upper and lower diagrams in FIG. 8 show the frequency characteristics of the transfer function of the switching regulator 200 as a whole. Lines A1 and B1 show the frequency characteristics when the output stage transistors of the differential amplifier circuit 110 are not cascode-connected. Lines A3 and B2 show the frequency characteristics when the output stage transistors of the differential amplifier circuit 110 are cascode-connected. As described above, the transfer function of the switching regulator 200 as a whole is determined by the transfer function of the compensator and the transfer function of the plant. Of the compensator and the plant, equation FC in FIG. 8 shows the transfer function Gc(s) of the compensator.

[0057] As shown in the formula FC in FIG. 8, the DC gain of the compensator is the DC gain Gm×RO of the differential amplifier circuit 110. As described in FIG. 7, the output stage transistor of the differential amplifier circuit 110 is cascode-connected. As a result, the output impedance RO of the DC gain Gm×RO becomes large. The first pole frequency in the frequency characteristics of the entire switching regulator 200 is ωpc1=1 / (RO×CC1), and ωpc1 becomes small when the output impedance RO increases. Therefore, as shown by the line A3 in the upper diagram of FIG. 8, the DC gain of the transfer function Ts increases with an increase in RO, but the first pole frequency ωpc1 decreases, so that the line A3 becomes the same as the line A1 at a frequency higher than the first pole. Therefore, the zero cross frequencies of the lines A1 and A3 are the same frequency ωzp1.

[0058] 8, even if the output impedance RO of the differential amplifier circuit 110 increases, the zero cross frequency does not change, and therefore the phase margin Δph1 does not change either. That is, by cascode-connecting the output stage transistors of the differential amplifier circuit 110, the DC gain of the feedback loop can be increased while maintaining the stability of the feedback loop. This makes it possible to improve the accuracy of the output voltage VOUT of the switching regulator while maintaining the stability of the feedback loop.

[0059] On the other hand, since the output stage transistors are cascode-connected to increase the output impedance RO, the overdrive voltage for operating the output stage transistors in a saturated state becomes high. According to this embodiment, the voltage VC becomes higher by the voltage shift amount ΔV compared to the case where the level shifter 190 is not provided, so the minimum voltage of the voltage VC becomes higher and the overdrive voltage for operating the output stage transistors in a saturated state can be secured.

[0060] In this embodiment, the semiconductor circuit device 100 is used in a switching regulator 200. The switching regulator 200 regulates an input voltage VH using a switch element SWT and an inductor 210. The semiconductor circuit device 100 includes a current detection circuit 134, a differential amplifier circuit 110, a level shifter 190, and a comparison circuit 133. The current detection circuit 134 converts an inductor current IL flowing through the inductor 210 into a voltage and outputs it as a current detection voltage Vramp. The differential amplifier circuit 110 has a MOS transistor provided between a power supply node and an output node NVC. The differential amplifier circuit 110 amplifies the difference between a voltage DVOUT corresponding to an output voltage VOUT and a reference voltage VREF. The level shifter 190 level-shifts a voltage VC at an output node NVC of the differential amplifier circuit 110 to a low potential side and outputs a level-shifted voltage LV. The comparator circuit 133 compares the current detection voltage Vramp with the level-shifted voltage LV to output a switching signal CSWT for the switch element SWT.

[0061] As described in FIG. 4 or FIG. 6, when the load is small, the voltage VC output by the differential amplifier circuit 110 becomes low, and the MOS transistor connected to the output node NVC of the differential amplifier circuit 110 may not operate in a saturated state. According to this embodiment, the level shifter 190 is provided, so that the voltage VC can be increased by the shift amount ΔV of the level shift. This allows the MOS transistor connected to the output node NVC of the differential amplifier circuit 110 to operate in a saturated state, so that the characteristics of the switching regulator 200 do not deteriorate. For example, if the MOS transistor does not operate in a saturated state, the DC gain of the feedback loop decreases, and the accuracy of the output voltage VOUT decreases. According to this embodiment, the MOS transistor operates in a saturated state, so the DC gain of the feedback loop does not decrease, and the accuracy of the output voltage VOUT can be maintained.

[0062] In this embodiment, the level shifter 190 may be a source follower circuit.

[0063] Specifically, the level shifter 190 may include an N-type MOS transistor TNL and a resistor RL or a current source IBL. A voltage VC of an output node NVC of the differential amplifier circuit 110 may be input to a gate of the N-type MOS transistor TNL. The N-type MOS transistor TNL may output a level-shifted voltage LV from its source. The resistor RL or the current source IBL may be provided between the source of the N-type MOS transistor TNL and a low-potential power supply node.

[0064] According to this embodiment, the shift amount ΔV of the level shift is approximately the threshold voltage of the N-type MOS transistor TNL. The minimum voltage of the voltage VC output by the differential amplifier circuit 110 is ΔV or more, so it is equal to or higher than the threshold voltage of the N-type MOS transistor TNL. Since the overdrive voltage of the MOS transistor connected to the output node NVC of the differential amplifier circuit 110 is assumed to be smaller than the threshold voltage of the N-type MOS transistor TNL, the MOS transistor connected to the output node NVC of the differential amplifier circuit 110 can be operated in a saturated state.

[0065] In this embodiment, the voltage shift amount ΔV by the level shifter 190 may be equal to or greater than the overdrive voltage when the transistor included in the output stage of the differential amplifier circuit 110 operates in a saturated state.

[0066] According to this embodiment, the voltage VC output by the differential amplifier circuit 110 is higher than the level-shifted voltage LV by the voltage shift amount ΔV, so that the voltage VC becomes equal to or higher than the overdrive voltage, thereby allowing the transistors included in the output stage of the differential amplifier circuit 110 to operate in a saturated state.

[0067] Furthermore, in this embodiment, the gain of the level shifter 190 may be smaller than the gain of a plant including the switch element SWT, the inductor 210, the current detection circuit 134, and the comparison circuit 133. Moreover, the gain of the level shifter 190 may be smaller than the gain of a compensator including the differential amplifier circuit 110. Moreover, the gain of the level shifter 190 may be smaller than the product of the gain of the plant and the gain of the compensator.

[0068] The plant and compensator here do not include the level shifter 190. That is, the gain of the feedback loop of the switching regulator 200 is the multiplication value of the gain of the plant, the gain of the compensator, and the gain of the level shifter 190. In this case, if the gain of the level shifter 190 is large, the zero cross frequency at which the gain becomes 0 dB becomes high, so that the phase margin becomes small and the stability of the feedback loop may decrease. According to this embodiment, the gain of the level shifter 190 is relatively smaller than the gain of the plant, etc., so that it is easy to ensure the phase margin.

[0069] In this embodiment, the gain of the level shifter 190 may be 0 dB.

[0070] According to this embodiment, the gain of the level shifter 190 does not affect the gain of the feedback loop of the switching regulator 200. As a result, even if the level shifter 190 is provided, the zero cross frequency does not change and the stability of the feedback loop does not decrease.

[0071] In this embodiment, the differential amplifier circuit 110 may include a first output stage transistor and a second output stage transistor. The first output stage transistor is provided between a first power supply node and a first node, and outputs a current. The second output stage transistor is provided between the first node and an output node, and a first bias voltage is input to the gate.

[0072] As described in Fig. 8 and other drawings, by increasing the output impedance RO of the differential amplifier circuit 110, it is possible to achieve both the accuracy of the output voltage VOUT and the stability of the feedback loop. On the other hand, since the output stage transistors of the differential amplifier circuit 110 are cascode-connected to increase the output impedance RO, the overdrive voltage for operating the output stage transistors in a saturated state becomes high. According to this embodiment, the voltage VC output by the differential amplifier circuit 110 increases by the voltage shift amount ΔV, making it easier to ensure the overdrive voltage.

[0073] The first output stage transistor here may be either TNQa or TPQa in Fig. 7. When TNQa is the first output stage transistor, TNQb is the second output stage transistor, the low potential side power supply node is the first power supply node, Na is the first node, and VBa is the first bias voltage. When TPQa is the first output stage transistor, TPQb is the second output stage transistor, the high potential side power supply node is the first power supply node, Nb is the first node, and VBb is the first bias voltage.

[0074] In this embodiment, the first power supply node may be a low-potential power supply node. The voltage shift amount ΔV by the level shifter 190 may be equal to or greater than an overdrive voltage when the first output stage transistor and the second output stage transistor operate in a saturated state.

[0075] According to this embodiment, even if the voltage VC output by the differential amplifier circuit 110 becomes low, the voltage remains equal to or greater than the voltage shift amount ΔV, so that the overdrive voltage is ensured when the first output stage transistor and the second output stage transistor operate in a saturated state.

[0076] In this case, the first output stage transistor is TNQa in FIG. 7, and the second output stage transistor is TNQb in FIG.

[0077] In this embodiment, the differential amplifier circuit 110 may include a first differential pair transistor TND1, a second differential pair transistor TND2, and a first current mirror circuit. A voltage DVOUT based on the output voltage VOUT of the switching regulator 200 may be input to the gate of the first differential pair transistor TND1. A reference voltage VREF may be input to the gate of the second differential pair transistor TND2. The first current mirror circuit may mirror a current flowing through one of the first differential pair transistor TND1 and the second differential pair transistor TND2 as a current flowing through the first output stage transistor.

[0078] In this embodiment, the differential amplifier circuit 110 may include a third output stage transistor, a fourth output stage transistor, and a second current mirror circuit. The third output stage transistor may be provided between a second power supply node having a different potential from the first power supply node and the second node, and may output a current. The fourth output stage transistor may be provided between the second node and the output node, and a second bias voltage may be input to the gate. The second current mirror circuit may mirror the current flowing through the other of the first differential pair transistor TND1 and the second differential pair transistor TND2 as a current flowing through the third output stage transistor.

[0079] According to this embodiment, a current flows through the differential pair transistors in response to a voltage input to the gates of the differential pair transistors, and the current is mirrored to the output stage transistor. As a result, the differential amplifier circuit 110 outputs a current corresponding to the input voltage. That is, the differential amplifier circuit 110 functions as a transconductance amplifier. According to this embodiment, the output stage transistors are cascode-connected on both the first power supply node side and the second power supply node side. The differential amplifier circuit 110 outputs the difference between the current flowing through the output stage transistor on the first power supply node side and the current flowing through the output stage transistor on the second power supply node side. In this embodiment, the impedance is high for the current on either power supply node side, so the output impedance RO of the differential amplifier circuit 110 is high.

[0080] When TNQa is the first output stage transistor, TNQb is the second output stage transistor, TPQa is the third output stage transistor, TPQb is the fourth output stage transistor, MCa is the first current mirror circuit, and MCb is the second current mirror circuit. When TPQa is the first output stage transistor, TPQb is the second output stage transistor, TNQa is the third output stage transistor, TNQb is the fourth output stage transistor, MCb is the first current mirror circuit, and MCa is the second current mirror circuit.

[0081] 3. Switching signal output circuit 9 is a detailed configuration example of a switching signal output circuit. The semiconductor circuit device 100 includes a regulator 170. The switching signal output circuit 130 includes a current detection circuit 134 and a comparison circuit 133. The current detection circuit 134 includes an inductance current detection circuit 131, an internal slope generation circuit 132, and a resistor R2.

[0082] The regulator 170 is a DC / DC converter that regulates the input voltage VH to the internal power supply voltage VDD. The regulator 170 is, for example, a linear regulator configured with an operational amplifier and a resistor, but is not limited to this.

[0083] The inductor current detection circuit 131 detects the inductor current IL based on the difference between the input voltage VH and the voltage VSW of the switch node NSW, and outputs the result as a detection current Isn.

[0084] The internal slope generating circuit 132 operates on the internal power supply voltage VDD, and generates a slope current Ise having a predetermined slope.

[0085] One end of the resistor R2 is connected to the output node of the inductance current detection circuit 131, the output node of the internal slope generation circuit 132, and the inverting input terminal of the comparison circuit 133. The other end of the resistor R2 is connected to the low potential side power supply node. The resistor R2 converts the detection current Isn and the slope current Ise into a voltage Vramp.

[0086] A voltage LV is input to a non-inverting input terminal of the comparison circuit 133 from the level shifter 190. The comparison circuit 133 compares the voltage Vramp with the voltage LV to generate a switching signal CSWT, which is a PWM signal or a PFM signal.

[0087] FIG. 10 shows an example of a signal waveform of a switching signal output circuit.

[0088] The comparison circuit 133 performs a comparison operation when the voltage Vramp is lower than the voltage LV at the comparison timing for each period Tp, and does not perform a comparison operation when the voltage Vramp is higher than the voltage LV at the comparison timing. That is, when the voltage Vramp is lower than the voltage LV at the comparison timing, the comparison circuit 133 resets the switching signal CSWT to a high level. When the switching signal CSWT is reset to a high level, the switching element SWT turns on from off, and the detection current Isn and the slope current Ise are output. At this time, Vramp = (Isn + Ise) × R2. When the voltage Vramp reaches the voltage LV, the comparison circuit 133 changes the switching element SWT from a high level to a low level. As a result, the switching element SWT turns off from on. When the switching element SWT turns off, the detection current Isn and the slope current Ise are no longer output. Note that the comparison timing is generated based on, for example, a clock signal generated by an internal oscillation circuit (not shown). However, the comparison timing may be generated based on a clock signal supplied from outside the semiconductor circuit device 100, or may be generated using a counter or the like.

[0089] In FIG. 10, the voltage LV is shown as a constant voltage, but actually it is affected by the output voltage VOUT. When the load of the switching regulator 200 is large, the output voltage VOUT drops rapidly after the switching element SWT turns off. For this reason, the voltage LV is maintained at a relatively high voltage, and the time until Vramp returns to Vramp < LV is shorter than the period Tp. For this reason, Vramp < LV at each comparison timing, and a comparison operation is performed. In this case, the control of the switching element SWT becomes PWM control.

[0090] On the other hand, when the load of the switching regulator 200 is small, after the switching element SWT turns off, it takes time for the output voltage VOUT to drop. As a result, the voltage LV becomes a relatively low voltage, and the time until Vramp returns to less than LV becomes longer than the period Tp. For this reason, once the switching element SWT turns on and off, Vramp becomes less than LV after one or more periods Tp, and the comparison operation is performed. In this case, the control of the switching element SWT becomes PFM control.

[0091] FIG. 10 shows an example of PWM control. As described above, the voltage LV fluctuates in the short term, but the voltage LV as the long-term average is controlled so that the divided voltage DVOUT of the output voltage VOUT matches the reference voltage VREF. When the voltage LV changes, the on-time Ton of the switching element SWT changes, the on-duty of the switching signal CSWT, which is a PWM signal, changes, and the output voltage VOUT changes. In this way, feedback control is performed so that the output voltage VOUT as the long-term average becomes constant.

[0092] FIG. 11 is a detailed configuration example of the inductance current detection circuit. The inductance current detection circuit 131 includes switches SW1 and SW2, resistors R1a, R1b, and R1c, P-type transistors TPE1, TPE2, and TPE3, N-type transistors TNE1 and TNE2, and a current source circuit IBE. Hereinafter, the operation of the inductance current detection circuit 131 will be described using signal waveform examples.

[0093] FIG. 12 is a signal waveform example of the inductance current detection circuit. Let the on-resistance of the switching element SWT be Ron. Assume that the resistance values of the resistors R1a, R1b, and R1c are equal, and let the resistance value be R1.

[0094] As shown in Fig. 12, when the switch element SWT is on, the switch SW1 is off and the switch SW2 is on. The inductor current IL gradually increases. This inductor current IL is converted into a potential difference of the following equation (1) by the on-resistance Ron. The inductor current detection circuit 131 generates a detection current Isn from this potential difference VH-VSW. VH-VSW=IL×Ron (1)

[0095] Specifically, the current source circuit IBE passes a current Iref through the resistor R1a and the P-type transistor TPE1. The voltage of the node N1a between the resistor R1a and the P-type transistor TPE1 is Vx. The potential difference across the resistor R1a is VSW-Vx, so the current Iref is given by the following equation (2). Iref = (VSW - Vx) / R1 (2)

[0096] The P-type transistors TPE1 and TPE2 form a current mirror, and a current Iref flows through the resistor R1b and the P-type transistor TPE2. The P-type transistors TPE1 and TPE3 form a current mirror, and a current Iref flows through the resistor R1c and the P-type transistor TPE3. As a result, the voltage of the node N1b between the resistor R1b and the P-type transistor TPE2, and the voltage of the node N1c between the resistor R1c and the P-type transistor TPE3 become equal to Vx.

[0097] Since the potential difference across the resistor R1c is VH-Vx, the current Ivh flowing through the resistor R1c and the P-type transistor TPE3 is expressed by the following equation (3). Ivh = (VH - Vx) / R1 (3)

[0098] The current Iref flowing through the P-type transistor TPE2 flows through the N-type transistor TNE1. The N-type transistors TNE1 and TNE2 form a current mirror, and the current Iref flows through the N-type transistor TNE2. The inductance current detection circuit 131 outputs the difference between the current IVh flowing through the P-type transistor TPE3 and the current Iref flowing through the N-type transistor TNE2 as the detection current Isn. From the above equations (1) to (3), the detection current Isn is given by the following equation (4). Isn=Ivh-Iref=(VH-VSW) / R1=IL×Ron / R1 (4)

[0099] When the switch element SWT is off, the switch SW1 is on and the switch SW2 is off. The inductor current IL gradually decreases. Since the switch SW1 is on, Iref=Ivh and Isn=0.

[0100] 13 is a detailed configuration example of the slope generating circuit. The internal slope generating circuit 132 includes current source circuits IBF1 and IBF2, a PNP transistor TBF1, an NPN transistor TBF2, P-type transistors TPF2 and TPF3, a switch SW3, a capacitor CF, and a resistor RF. The operation of the internal slope generating circuit 132 will be described below.

[0101] When the switch element SWT is on, the switch SW3 is off. The current source circuit IBF1 supplies a current to a node NF1 at one end of the capacitor CF, causing the voltage VCF of the node NF1 to rise at a predetermined slope.

[0102] The base of PNP transistor TBF1 is connected to node NF1. Assume that the base-emitter voltage of the bipolar transistor is Vbe. The voltage of node NF2, the emitter of PNP transistor TBF1, is VCF+Vbe. The base of NPN transistor TBF2 is connected to node NF2. The voltage of node NF3, the emitter of the NPN transistor, is (VCF+Vbe)-Vbe=VCF.

[0103] Resistor RF is provided between node NF3 and the low potential power supply node. When the voltage of the low potential power supply VSS is 0V, a current VCF / RF flows through resistor RF. This current flows through P-type transistor TPF2 and NPN transistor TBF2. P-type transistors TPF2 and TPF3 form a current mirror, and current VCF / RF flows through P-type transistor TPF3. Internal slope generation circuit 132 outputs the current flowing through P-type transistor TPF3 as slope current Ise. That is, slope current Ise is expressed by the following equation (5). Ise=VCF / RF (5)

[0104] When the switch element SWT is off, the switch SW3 is on. Both ends of the capacitor CF are shorted by the switch SW3, so the voltage VCF becomes 0 V. As a result, Ise=0.

[0105] Although the present embodiment has been described in detail as above, it will be easily understood by those skilled in the art that many modifications are possible without substantially departing from the novel matters and effects of the present disclosure. Therefore, all such modifications are intended to be included in the scope of the present disclosure. For example, a term described at least once in the specification or drawings together with a different term having a broader meaning or synonymy can be replaced with that different term anywhere in the specification or drawings. In addition, all combinations of the present embodiment and modifications are also included in the scope of the present disclosure. In addition, the configurations and operations of the differential amplifier circuit, phase compensation circuit, switching signal output circuit, semiconductor circuit device, and switching regulator are not limited to those described in the present embodiment, and various modifications are possible. [Explanation of symbols]

[0106] 100...semiconductor circuit device, 110...differential amplifier circuit, 120...phase compensation circuit, 130...switching signal output circuit, 131...inductance current detection circuit, 132...internal slope generation circuit, 133...comparison circuit, 134...current detection circuit, 140...reference voltage generation circuit, 160...diode, 170...regulator, 190...level shifter, 200...switching regulator, 210...inductor, 220...capacitor, 250...power supply, 290...load, CSWT...switch switching signal, IL...inductor current, LV...voltage after level shift, MCa, MCb...current mirror circuit, SWT...switching element, TND1...first differential pair transistor, TND2...second differential pair transistor, TNQa, TNQb, TPQa, TPQb...output stage transistor, VBa, VBb...bias voltage, VC...voltage of output node of differential amplifier circuit, VH...input voltage, VOUT...output voltage, VREF...reference voltage, Vramp...current detection voltage, ΔV...amount of voltage shift

Claims

1. A semiconductor circuit device used in a switching regulator that uses a switch element and an inductor to regulate an input voltage and output an output voltage, a current detection circuit that converts an inductor current flowing through the inductor into a voltage and outputs the voltage as a current detection voltage; a differential amplifier circuit having a MOS transistor provided between a power supply node and an output node, the differential amplifier circuit amplifying a difference between a voltage corresponding to the output voltage and a reference voltage; a level shifter that level-shifts a voltage of the output node of the differential amplifier circuit to a low potential side and outputs the level-shifted voltage; a comparison circuit that compares the current detection voltage with the level-shifted voltage to output a switching signal for the switch element; A semiconductor circuit device comprising:

2. 2. The semiconductor circuit device according to claim 1, The semiconductor circuit device is characterized in that the level shifter is a source follower circuit.

3. 3. The semiconductor circuit device according to claim 2, The source follower circuit comprises: an N-type MOS transistor having a gate to which the voltage of the output node of the differential amplifier circuit is input and having a source to output the level-shifted voltage; a resistor or a current source provided between the source and a low potential side power supply node; A semiconductor circuit device comprising:

4. 2. The semiconductor circuit device according to claim 1, A semiconductor circuit device, characterized in that an amount of voltage shift by the level shifter is equal to or greater than an overdrive voltage when a transistor included in an output stage of the differential amplifier circuit operates in a saturated state.

5. 2. The semiconductor circuit device according to claim 1, The gain of the level shifter is is smaller than a gain of a plant including the switch element, the inductor, the current detection circuit, and the comparison circuit, is smaller than the gain of a compensator including the differential amplifier circuit, and a gain of the compensator that is smaller than a product of the gain of the plant and the gain of the compensator.

6. 2. The semiconductor circuit device according to claim 1, A semiconductor circuit device, wherein the gain of the level shifter is 0 dB.

7. 2. The semiconductor circuit device according to claim 1, The differential amplifier circuit includes: a first output stage transistor provided between a first power supply node and a first node, the first output stage transistor outputting a current; a second output stage transistor provided between the first node and the output node, the second output stage transistor having a gate to which a first bias voltage is input; A semiconductor circuit device comprising:

8. 8. The semiconductor circuit device according to claim 7, the first power supply node is a low potential power supply node, A semiconductor circuit device, characterized in that an amount of voltage shift by the level shifter is equal to or greater than an overdrive voltage when the first output stage transistor and the second output stage transistor operate in a saturated state.

9. 9. The semiconductor circuit device according to claim 8, The differential amplifier circuit includes: a first differential pair transistor having a gate to which a voltage based on the output voltage of the switching regulator is input; a second differential pair of transistors, the gates of which receive the reference voltage; a first current mirror circuit that mirrors a current flowing through one of the first differential pair transistors and the second differential pair transistors as a current flowing through the first output stage transistor; A semiconductor circuit device comprising:

10. 10. The semiconductor circuit device according to claim 9, The differential amplifier circuit includes: a third output stage transistor that is provided between a second node and a second power supply node having a potential different from that of the first power supply node and outputs a current; a fourth output stage transistor provided between the second node and the output node, the fourth output stage transistor having a gate to which a second bias voltage is input; a second current mirror circuit that mirrors a current flowing through the other of the first differential pair transistors and the second differential pair transistors as a current flowing through the third output stage transistor; A semiconductor circuit device comprising:

11. 2. The semiconductor circuit device according to claim 1, a phase compensation circuit connected to the output node of the differential amplifier circuit; The phase compensation circuit includes: a resistor and a first capacitor connected in series between the output node of the differential amplifier circuit and a low potential side power supply node;

12. A semiconductor circuit device according to any one of claims 1 to 11, The inductor; A switching regulator comprising:

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