Semiconducting crystal particle and manufacturing method thereof
By using hexagonal peripheral pads and rectangular central pads in semiconductor crystal grains, the issues of stress and thermal damage are addressed, resulting in improved reliability and current density.
Patent Information
- Application Number
- JP2024074744
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2024-04-02
- Filing Date
- 2024-05-02
- Publication Date
- 2025-05-12
- Estimated Expiration
- 2044-05-02
AI Technical Summary
Semiconductor crystal grains, particularly in silicon carbide (SiC) MOSFETs, face issues with stress and thermal damage during manufacturing, leading to potential pad damage and reduced reliability.
The implementation of semiconductor crystal grains with peripheral region pads having a hexagonal outer edge and central region pads with a rectangular outer edge, which helps in distributing stress and heat uniformly, thereby preventing pad damage.
This configuration enhances the reliability of semiconductor crystal grains by reducing stress concentration and thermal deposition in the peripheral region, while also improving current density and reducing on-resistance per unit area.
Smart Images
Figure 2025073054000001_ABST
Abstract
Description
[Technical field]
[0001] The present disclosure relates to semiconductor crystal grains and methods for producing the same. [Background technology]
[0002] Typically, in a silicon carbide (SiC) metal oxide semiconductor field effect transistor (MOSFET), the gate pad, source pad, and drain pad of the transistor are arranged in a rectangular shape.
[0003] However, the peripheral regions of a semiconductor die are more susceptible to stress and thermal damage than the central region during the manufacturing process. For example, transistor pads located at the corners and edges of a semiconductor die may fracture or burst due to stress during wafer separation. Moreover, these pads are also susceptible to damage due to heat accumulation during packaging processes and reliability tests. This may reduce the reliability of the semiconductor die, and is a major challenge in the thermal design of semiconductor devices.
[0004] Therefore, how to propose semiconductor crystal grains and a manufacturing method thereof that can solve the above problems is one of the problems that the industry is currently investing research and development resources to solve. Summary of the Invention [Problem to be solved by the invention]
[0005] In view of this, one object of the present disclosure is to propose a semiconductor element and a manufacturing method thereof that can solve the above problems. [Means for solving the problem]
[0006] In order to achieve the above-mentioned object, according to some embodiments of the present disclosure, a semiconductor crystal grain is provided, comprising: a first transistor located in a peripheral region of the semiconductor crystal grain and including a first pad having a first outer edge that is hexagonal in a planar view; and a second transistor located in a central region of the semiconductor crystal grain and including a second pad having a second outer edge that is rectangular in a planar view, wherein the peripheral region surrounds the central region, and the first transistor is a semiconductor crystal grain that commonly surrounds the second transistor.
[0007] According to another embodiment of the present disclosure, there is provided a method for manufacturing semiconductor crystal grains, comprising the steps of providing a substrate including a central region and a peripheral region surrounding the central region, forming a first transistor in the peripheral region having a first pad, each of which has a first outer edge that is hexagonal in plan view, and forming a second transistor in the central region having a second pad, each of which has a second outer edge that is rectangular in plan view, wherein the first transistor commonly surrounds the second transistor. Effect of the Invention
[0008] As described above, in the semiconductor crystal grains and the manufacturing method thereof according to some embodiments of the present disclosure, when the pads in the central region are maintained rectangular, the pads in the peripheral region are provided in a hexagonal shape, thereby improving the problems of stress concentration and heat deposition in the peripheral region and preventing the pads located in the peripheral region from bursting or failing. Note that the hexagonal pads have a higher channel density and current density than the rectangular pads, which contributes to reducing the on-resistance per unit area, and therefore can contribute to improving the leakage current of the transistor. Compared with general semiconductor crystal grains and the manufacturing method thereof, the reliability of the device can be improved.
[0009] These and other aspects of the present disclosure will become apparent from the following description of preferred embodiments taken in conjunction with the drawings, in which:
[0010] The drawings illustrate one or more embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure. Wherever possible, the same reference numbers are used throughout the drawings to refer to similar or identical elements of the embodiments. [Brief description of the drawings]
[0011] [Figure 1] 1 is a top schematic view of a wafer according to some embodiments of the present disclosure. [Diagram 2] 1 is a planar schematic diagram of a semiconductor grain according to some embodiments of the present disclosure. [Diagram 3] 3 is a cross-sectional schematic diagram of a peripheral region of a semiconductor grain taken along line 3 in FIG. 2 according to some embodiments of the present disclosure. [Figure 4] 1 is a planar schematic diagram of a semiconductor grain according to some embodiments of the present disclosure. [Diagram 5] 1 is a planar schematic diagram of a semiconductor grain according to some embodiments of the present disclosure. [Figure 6] 4 is a schematic plan view of a semiconductor grain according to some further embodiments of the present disclosure. [Figure 7] 4A-4C are schematic plan views of semiconductor grains according to further embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0012] In the following, in order to disclose and clearly explain the embodiments of the present disclosure in the drawings, many practical details are described in the following description. However, it should be understood that these practical details are not intended to limit the present disclosure. That is, in some embodiments of the present disclosure, these practical details are not necessary. Moreover, in order to simplify the drawings, some of the conventional structures and elements are simply illustrated in the drawings.
[0013] Please refer to FIG. 1 and FIG. 2. FIG. 1 is a plan view schematic diagram of a wafer W according to some embodiments of the present disclosure. FIG. 2 is a plan view schematic diagram of a semiconductor grain 100 according to some embodiments of the present disclosure. As shown in FIG. 1, the wafer W includes a plurality of semiconductor grains 100. As shown in FIG. 2, the semiconductor grain 100 has a peripheral region PA and a central region CA. The peripheral region PA surrounds the central region CA. As shown in FIG. 2, the peripheral region PA has an outermost edge E0 (also referred to as the outermost edge of the substrate 101 of the semiconductor grain 100). In some embodiments, the outermost edge E0 is rectangular.
[0014] In some embodiments, the semiconductor crystal grain 100 includes a plurality of first transistors (represented in the figures by first pads 110 included therein) and one second transistor (represented in the figures by second pads 120 included therein). As shown in FIG. 2, the first transistors are provided substantially uniformly in the peripheral region PA. The second transistors are provided in the central region CA. The peripheral region PA surrounds the central region CA, and the first transistors provided in the peripheral region PA commonly surround the second transistor provided in the central region CA.
[0015] Typically, during the manufacturing process, the first transistor in the peripheral area PA is susceptible to stress and heat damage, so some embodiments of the present disclosure propose a structure that contributes to uniform distribution of stress and heat to the transistor located in the peripheral area PA.
[0016] Specifically, each first transistor includes at least one first pad 110. As shown in the plan view of FIG. 2, the first pad 110 has a first outer edge E1 that is hexagonal. In some embodiments, the first pad 110 may be a source or a gate of the first transistor. In some embodiments, two first pads 110 may be a source and a gate of the same first transistor, respectively. In some embodiments, adjacent first pads 110 are separated from each other.
[0017] The second transistor includes a second pad 120. As shown in the plan view of FIG. 2, the second pad 120 has a rectangular second outer edge E2. In some embodiments, the second pad 120 may be a source or a gate of the second transistor. In some embodiments, the second pad 120 and the adjacent first transistor are isolated from each other.
[0018] The outer edge of a hexagon has more straight sides and a larger angle between the two straight sides than the outer edge of a rectangle, which can improve heat dissipation efficiency.In addition, since the channel density and current density of a hexagonal pad are higher than those of a rectangular pad, the on-resistance (Ron) per unit area of the hexagonal pad is smaller, which contributes to improving the leakage current of the transistor.
[0019] As shown in FIG. 2, in order to disperse heat deposition around the semiconductor crystal grain 100, at least a part of one first transistor is present between the periphery of the second transistor and the outermost edge E0 of the semiconductor crystal grain 100. Specifically, as shown in FIG. 2, the second outer edge E2 of the second pad 120 has a first straight side E21, a second straight side E22, a third straight side E23, and a fourth straight side E24. Between the first straight side E21 and the outermost edge E0, there is a first pad 110 of the first transistor. Similarly, between the second straight side E22 and the outermost edge E0, between the third straight side E23 and the outermost edge E0, and between the fourth straight side E24 and the outermost edge E0, there is a first pad 110 of the first transistor, respectively. In this way, the heat deposited in the peripheral area PA is dispersed through the hexagonal pad without being transferred to and accumulated at the corners or edges of the rectangular pad.
[0020] Please refer to Fig. 3. Fig. 3 is a cross-sectional schematic diagram of a peripheral area PA of a semiconductor grain 100 according to some embodiments of the present disclosure, taken along line segment 3 in Fig. 2. For clarity, Fig. 3 omits substrate 101 of semiconductor grain 100.
[0021] As shown in FIG. 3, the semiconductor crystal grain 100 further includes a drain pad 130 and a device layer 140. The device layer 140 includes a first transistor T1 and a first transistor T2. The first transistor T1 and the first transistor T2 each include a source, a gate, and a drain. The source and gate of the first transistor T1 are electrically connected to two first pads 110 on the top, respectively. The drain of the first transistor T1 is electrically connected to the drain pad 130 on the bottom. Similarly, the source or gate of the first transistor T2 is electrically connected to another first pad 110 on the top, and the drain is electrically connected to the drain pad 130 on the bottom.
[0022] Please refer to both Figures 2 and 3. A method for fabricating semiconductor grains 100 will be described with reference to Figures 2 and 3 in the following paragraphs.
[0023] The method includes first providing a substrate 101. As shown in Figure 2, the substrate 101 includes a peripheral area PA and a central area CA. The peripheral area PA surrounds the central area CA.
[0024] The method further includes forming a plurality of first transistors in the peripheral area PA. As shown in FIG. 2, each of the first transistors has a first pad 110. In a plan view, a first outer edge E1 of the first pad 110 is hexagonal. These first pads 110 may be sources or gates of the first transistors. In some embodiments, the first pads 110 are provided on the top surface of the element layer 140, as shown in FIG. 3.
[0025] The method then includes coupling the first pads 110 to a gate voltage or a source voltage based on the electrical connectivity of these first pads 110.
[0026] The method further comprises forming second transistors in the central region CA. As shown in FIG. 2, the second transistors have second pads 120. The first transistors commonly surround the second transistors. The first pads 110 commonly surround the second pads 120. In plan view, the second outer edges E2 of the second pads 120 are rectangular. Similarly, these second pads 120 may be sources or gates of the second transistors and may be provided on the top surface of the element layer 140.
[0027] The method then includes coupling the second pads 120 to a gate voltage or a source voltage based on the electrical connectivity of these second pads 120 .
[0028] 3, the method may further include forming a drain pad 130 on a lower surface of the device layer 140. In some embodiments, the drain pad 130 is formed entirely on the lower surface of the device layer 140. The method may further include coupling the drain pad 130 to a drain voltage.
[0029] Please refer to FIG. 4. FIG. 4 is a schematic plan view of a semiconductor grain 100' according to some embodiments of the present disclosure. The semiconductor grain 100' differs from the semiconductor grain 100 in that the semiconductor grain 100' includes a plurality of second transistors in a central region CA. As shown in FIG. 4, the semiconductor grain 100' includes four second pads 120. The first pad 110 commonly surrounds the four second pads 120.
[0030] It should be noted that, similar to the semiconductor grains 100, there is at least one first pad 110 between the periphery of each second pad 120 and the outermost edge E0 of the semiconductor grains 100' in order to distribute the heat evenly around the periphery.
[0031] Please refer to FIG. 5. FIG. 5 is a schematic plan view of a semiconductor grain 100″ according to some embodiments of the present disclosure. The semiconductor grain 100″ differs from the semiconductor grain 100′ in that the first pads (e.g., first pads 110-1) of the semiconductor grain 100″ are alternately distributed to increase the array density.
[0032] In some embodiments, a first pad may extend partially between two second pads to achieve a tighter arrangement. For example, as shown in FIG. 5, first pad 110-1 extends between second pad 120-1 and second pad 120-2.
[0033] Accordingly, in some embodiments, the method for manufacturing the semiconductor grain 100″ may further include forming a plurality of second transistors in the central region such that a first pad 110-1 of one first transistor extends between a second pad 120-1 of one second transistor and a second pad 120-2 of another second transistor to achieve a higher array density.
[0034] Semiconductor grain 100″ differs from semiconductor grain 100′ in that it may further include a third transistor in the peripheral region. In some embodiments, the third transistor is located between the first transistor and the second transistor. In some embodiments, the third transistor is located between the first transistor and the outermost edge E0. The third transistor and the first transistor commonly surround the second transistor.
[0035] For example, the third transistor may include a third pad 110-2. As shown in the plan view of FIG. 5, the third pad 110-2 is surrounded by a plurality of first pads and a plurality of second pads. In the plan view, the third pad 110-2 has a trapezoidal third outer edge E3. The bottom side of the trapezoid of the third outer edge E3 is close to the second pad. The third pad 110-2 may be the source or gate of the third transistor, similar to the first pad.
[0036] For example, the third transistor may include a third pad 110-3. As shown in FIG. 5, the third pad 110-3 is located between the first pad and the outermost edge E0. In a plan view, the third pad 110-3 has a trapezoidal third outer edge E3. The bottom side of the trapezoid of the third outer edge E3 is close to or overlaps with the outermost edge E0. Similarly, the third pad 110-3 may be the source or gate of the third transistor.
[0037] Accordingly, in some embodiments, the method for manufacturing the semiconductor grain 100″ may include forming a third transistor between the plurality of first transistors and the plurality of second transistors in the peripheral region. In some embodiments, the method for manufacturing the semiconductor grain 100″ may include forming a third transistor between the plurality of first transistors and the outermost edge E0 in the peripheral region. In addition, the method for manufacturing the semiconductor grain 100″ may further include coupling the third pad to a gate voltage or a source voltage.
[0038] Please refer to FIG. 6. FIG. 6 is a schematic plan view of a semiconductor grain 200 according to another embodiment of the present disclosure. The semiconductor grain 200 differs from the semiconductor grain 100 in that the first pad 210 has a rectangular fourth outer edge E4 and the second pad 220 has a rectangular fifth outer edge E5, as shown in FIG. 6. Furthermore, the fourth outer edge E4 is substantially square, and the fifth outer edge E5 is elongated. In some embodiments, the side length of any one of the fourth outer edges E4 is greater than the side length of any one of the fifth outer edges E5.
[0039] 6, the semiconductor crystal grain 200 differs from the semiconductor crystal grain 100 in that the minimum distance between the first pad 210 and the second pad 220 is greater than the minimum distance between the first pad 110 and the second pad 120 of the semiconductor crystal grain 100. By adjusting the size and distribution density of the characteristic length in the central region and the peripheral region of the pad, it is possible to control the distribution of current density and further improve the uniformity of heat distribution and stress distribution.
[0040] Please refer to Fig. 7. Fig. 7 is a schematic plan view of a semiconductor grain according to further embodiments of the present disclosure. In these embodiments, the features of the semiconductor grain 100 and the semiconductor grain 200 are combined to provide hexagonal pads in the peripheral region PA and rectangular pads, such as the first pad 210 and the second pad 220 similar to those of the semiconductor grain 200, in the central region CA, and the first pad 210 commonly surrounds the second pad 220 in the central region CA, thereby further optimizing the heat distribution in the central region CA.
[0041] From the detailed description of the specific embodiments of the present disclosure, it has become clear that in the semiconductor crystal grains and the manufacturing method thereof according to some embodiments of the present disclosure, when the pad in the central region is maintained rectangular, the pad in the peripheral region is provided in a hexagonal shape, thereby improving the problems of stress concentration and heat deposition in the peripheral region and preventing the pad located in the peripheral region from bursting or failing. In addition, the hexagonal pad has a larger channel density and current density than the rectangular pad, which contributes to reducing the on-resistance per unit area, and therefore can contribute to improving the leakage current of the transistor. Compared with the general semiconductor crystal grains and the manufacturing method thereof, the reliability of the device can be improved.
[0042] The foregoing is merely an illustration and description of exemplary embodiments of the present disclosure and is not intended to be exhaustive or to limit the invention to the precise forms disclosed in the present disclosure. Modifications or variations of the above teachings may be made.
[0043] The selected and described embodiments are used to illustrate the contents of the present disclosure and their practical applications, and encourage those skilled in the art to utilize the present disclosure and the various embodiments to make various modifications to suit the expected specific applications. Alternative embodiments will be apparent to those skilled in the art without departing from the spirit and scope of the present disclosure. Therefore, the scope of the present disclosure is not limited by the foregoing specification and the exemplary embodiments described therein, but is limited based on the scope of the attached patent application. [Explanation of symbols]
[0044] 3: Line segment 100, 100', 100", 200: Semiconductor grains 101: Base material 110, 110-1, 210: 1st pad 110-2, 110-3: 3rd pad 120, 120-1, 120-2, 220: 2nd pad 130: Drain pad 140: Element layer CA: central area E0: Outermost edge E1: First outer edge E2: Second outer edge E21: First straight edge E22: Second straight edge E23: Third straight edge E24: Fourth straight edge E3: Third outer edge E4: The fourth outer edge E5: Fifth outer edge PA: Peripheral area T1, T2: first transistor W: Wafer
Claims
1. A semiconductor grain comprising: a plurality of first transistors each including a first pad located in a peripheral region of the semiconductor crystal grain and each having a first outer edge that is hexagonal in plan view; a second transistor including a second pad located in a central region of the semiconductor crystal grain and having a second outer edge that is rectangular in plan view; Equipped with The peripheral region surrounds the central region, and the first transistor commonly surrounds the second transistor.
2. 2. The semiconductor crystal grain of claim 1, wherein the semiconductor crystal grain has an outermost edge, and the second outer edge of the second pad has a first straight side, a second straight side, a third straight side, and a fourth straight side, at least a portion of a first one of the plurality of first transistors is between the first straight side and the outermost edge, at least a portion of a second one of the plurality of first transistors is between the second straight side and the outermost edge, at least a portion of a third one of the plurality of first transistors is between the third straight side and the outermost edge, and at least a portion of a fourth one of the plurality of first transistors is between the fourth straight side and the outermost edge.
3. 2. The semiconductor crystalline grain of claim 1, further comprising: another second transistor in the central region, wherein the first pad of one of the plurality of first transistors extends between the second pad of the second transistor and the second pad of the other second transistor.
4. The semiconductor grain of claim 1 , wherein the first pad is a source or a gate, and the second pad is a source or a gate.
5. 2. The semiconductor crystal grain according to claim 1, further comprising a third transistor located in the peripheral region, the third pad having a trapezoidal third outer edge in a planar view, and positioned between the second transistor and one of the plurality of first transistors.
6. 2. The semiconductor crystal grain according to claim 1, further comprising a third transistor located in the peripheral region, the third pad having a trapezoidal third outer edge in a planar view, and positioned between the outermost edge of the semiconductor crystal grain and one of the plurality of first transistors.
7. providing a substrate comprising a central region and a peripheral region surrounding the central region; forming a plurality of first transistors in the peripheral region, each having a first pad with a first outer edge that is hexagonal in plan view; forming a second transistor in a central region, the second transistor having a second pad having a second outer edge that is rectangular in plan view; Equipped with A method for manufacturing a semiconductor crystal grain, wherein the plurality of first transistors commonly surround the second transistor.
8. 8. The method of claim 7, further comprising forming another second transistor in the central region, the first pad of one of the plurality of first transistors extending between the second pad of the second transistor and the second pad of the other second transistor.
9. 8. The manufacturing method according to claim 7, further comprising a step of forming a third transistor in the peripheral region, the third transistor including a third pad having a trapezoidal third outer edge in a plan view, and being located between the second transistor and one of the plurality of first transistors.
10. 8. The manufacturing method according to claim 7, further comprising a step of forming a third transistor in the peripheral region, the third transistor including a third pad having a trapezoidal third outer edge in a plan view, and being located between the outermost edge of the substrate and one of the plurality of first transistors.