Array board and display panel

Abstract

To provide an array board and a display panel capable of suppressing an interlayer leak current caused by ESD.SOLUTION: In an array board 11, a first wire 21 that comprises a first conductive film 41 and extends toward a non-display area is provided in a display area, a second wire 24 that comprises the first conductive film 41 and expands planarly, a third wire 26 that comprises a second conductive film 42, extends along an extension direction of the first wire 21, and allows an end in the display area side to be superposed on the end of the first wire 21 extended from the display area to a non-display area side and is connected by a first contact hole CH1, and an island-shaped fourth wire 27 that comprises the second conductive film 42 and is superposed on the second wire 24, is disposed adjacent to the third wire 26, and is disposed such that the end of the display area side is adjacent to the end of the display area side of the second wire 24 are provided in the non-display area, and the fourth wire 27 is connected to the second wire 24 by a second contact hole CH2 in a position that is adjacent to the third wire 26 and is adjacent to the display area.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to an array substrate and a display panel. [Background technology]

[0002] A liquid crystal panel, a key component of a liquid crystal display device, is constructed by sealing a liquid crystal layer between a pair of substrates, with a large number of pixel electrodes and switching elements arranged in a matrix on one of the substrates (array substrate, active matrix substrate). The array substrate is generally formed during the manufacturing process by depositing and etching various thin films.

[0003] During the manufacturing process of an array substrate, when a metal film made of a metal material is patterned using a known photolithography method, the metal film may become charged. This can cause electrostatic discharge (ESD) between isolated metal film patterns, resulting in short leakage and reduced yield due to line defects. In particular, leakage current in a circuit section (including a driver circuit for driving the liquid crystal panel) monolithically formed outside the display area (i.e., the non-display area) of the array substrate can significantly cause display defects. More specifically, if ESD occurs in a portion of the non-display area where a first metal film and a second metal film stacked with an insulating film interposed therebetween, the insulating film can be destroyed, causing interlayer leakage current between the first and second metal films, resulting in line-shaped display defects across the entire display area.

[0004] As a countermeasure against ESD, it is known to form discharge protrusions that function as lightning rods on the pads on the scanning wiring of the array substrate, or to form avoidance patterns or electrostatic protection elements to disperse the electric charge generated by electrification, and an example of this is disclosed in Patent Document 1. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 8-234227 Summary of the Invention [Problem to be solved by the invention]

[0006] However, the configuration in which protrusions are formed on pads on the scanning wiring as in Patent Document 1 above has the problem that the scanning lines themselves are shorted out, making the shorted scanning lines unusable. Also, extra space is required to form the discharge protrusions, which can hinder the narrowing of the non-display area.

[0007] The technology described in this specification has been developed based on the above-mentioned circumstances, and aims to provide an array substrate and a display panel that can suppress interlayer leakage current caused by ESD. [Means for solving the problem]

[0008] (1) An array substrate according to the technology described in the present specification has a display area for displaying an image and a non-display area adjacent to the display area where no image is displayed, wherein the display area is provided with a plurality of first wirings made of a first conductive film and extending toward the non-display area, and the non-display area is provided with second wirings made of the first conductive film different from the first wirings and extending in a planar shape, and a second conductive film disposed above the first conductive film via an insulating film, the second wirings extending in the extension direction of the first wirings and having ends on the display area side in the non-display area extending in a direction parallel to the extension direction of the first wirings and extending from the display area to the non-display area. and a third wiring that is overlapped with an end of the first wiring that extends toward the display area and is connected by a first contact hole; and an island-shaped fourth wiring that is made of the second conductive film different from the third wiring, overlaps with the second wiring, and is arranged adjacent to the third wiring, and is arranged so that the end of the fourth wiring on the display area side in the non-display area is adjacent to the end of the second wiring on the display area side in the non-display area, and the fourth wiring is connected to the second wiring by a second contact hole that is provided at a position adjacent to the third wiring among the fourth wirings and adjacent to the display area.

[0009] (2) In addition to (1) above, the array substrate may have a notch recessed toward the opposite side of the display area at the end of the second wiring on the display area side in the non-display area where it intersects with the third wiring.

[0010] (3) In addition to the above (2), the array substrate may be configured such that the width of the notch is set to be larger than the width of the third wiring.

[0011] (4) In addition to (2) or (3) above, the array substrate may be configured such that the depth dimension of the cutout is set so that the bottom of the cutout is positioned farther from the display area than the second contact hole.

[0012] (5) In addition to any one of (1) to (4) above, the array substrate may have a protrusion that protrudes toward the third wiring at the end of the non-display area on the display area side, and the second contact hole may be provided in the protrusion.

[0013] (6) A display panel according to the technology described in the present specification includes an array substrate according to any one of (1) to (5) above, and an opposing substrate disposed opposite the array substrate. [Effects of the Invention]

[0014] According to the technology described in this specification, it is possible to provide an array substrate and a display panel that are capable of suppressing interlayer leakage current caused by ESD. [Brief explanation of the drawings]

[0015] [Figure 1] 1 is a schematic plan view of a liquid crystal panel according to a first embodiment; [Figure 2] Cross section of a liquid crystal panel [Figure 3] Circuit diagram showing pixel arrangement in the display area of ​​the array substrate [Figure 4] FIG. 1 is a plan view showing a part of a first circuit unit in a non-display area of ​​an array substrate; [Figure 5] Enlarged view of part of Figure 4 [Figure 6] Section II of Figure 4 [Figure 7] FIG. 10 is a plan view showing a part of a first circuit unit in a non-display area of ​​an array substrate according to a second embodiment. [Figure 8] FIG. 10 is a plan view showing a part of a first circuit unit in a non-display area of ​​an array substrate according to a third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0016] <Embodiment 1> A liquid crystal panel (an example of a display panel) 10 according to embodiment 1 will be described with reference to Figures 1 to 6. The drawings show X-axis, Y-axis, and Z-axis, and are drawn so that each axis direction is a common direction in each drawing.

[0017] As shown in Fig. 1, the liquid crystal panel 10 is divided into a display area (active area) AA, which is capable of displaying an image and is located in the center, and a non-display area (non-active area) NAA, which is located on the outer periphery of the display area AA and has a frame-like (picture frame-like) shape in a plan view. In Fig. 1, the dashed-dotted line represents the outline of the display area AA, and the area outside the dashed-dotted line is the non-display area NAA. Although the planar shape of the liquid crystal panel 10 is not limited, in this embodiment, the panel has a slightly vertically elongated rectangular shape overall, with its short side aligned with the X-axis, its long side aligned with the Y-axis, and its thickness aligned with the Z-axis in each drawing.

[0018] As shown in FIG. 2, the liquid crystal panel 10 is formed by bonding a pair of substrates 11 and 12 together. Between the pair of substrates 11 and 12 are at least a liquid crystal layer 13 and a sealing portion 14 that seals the liquid crystal layer 13. The liquid crystal layer 13 contains liquid crystal molecules, which are a substance whose optical properties change when an electric field is applied. The sealing portion 14 has a rectangular frame shape in a plan view as a whole, and surrounds the liquid crystal layer 13 in the non-display area NAA. The sealing portion 14 maintains a gap (cell gap) equal to the thickness of the liquid crystal layer 13. A polarizing plate 15 is attached to the outer surface of each of the pair of substrates 11 and 12.

[0019] Of the pair of substrates 11, 12, the one disposed on the front side (display surface side) is the counter substrate (CF substrate) 12, and the one disposed on the back side is the array substrate (active matrix substrate, TFT substrate) 11. Both the counter substrate 12 and the array substrate 11 are formed by laminating various films on the inner side (liquid crystal layer 13 side) of a glass substrate GS that is substantially transparent and has excellent light transmittance.

[0020] The array substrate 11 is larger than the counter substrate 12, and a portion of it protrudes beyond the counter substrate 12. A flexible substrate 16 is mounted on the protruding portion 11A of the array substrate 11. The flexible substrate 16 is configured by forming a number of wiring patterns on an insulating and flexible base material. One end of the flexible substrate 16 is connected to the array substrate 11, and the other end is connected to an external control substrate (signal supply source). Various signals supplied from the control substrate are transmitted to the liquid crystal panel 10 via the flexible substrate 16.

[0021] As shown in FIG. 3, a display area AA of the array substrate 11 is provided with a grid-like arrangement of a number of source lines (data lines, signal lines) 20 extending along the Y-axis direction (the vertical direction in FIG. 3) and gate lines (scanning lines, an example of first lines) 21 extending along the X-axis direction (the horizontal direction in FIG. 3) perpendicular to the source lines 20. As shown in FIG. 3, switching elements (more specifically, TFTs (Thin Film Transistors) 22) and pixel electrodes 23 are formed in each area surrounded by the source lines 20 and gate lines 21. A large number of TFTs 22 and pixel electrodes 23 are arranged in a matrix across the entire display area AA. A common electrode (not shown), which is supplied with a reference potential and overlaps with the pixel electrodes 23, is provided above the pixel electrodes 23 in the display area AA of the array substrate 11. The liquid crystal panel 10 of this embodiment operates in a so-called FFS (Fringe Field Switching) mode. When a signal is input from the source line 20 and the gate line 21 to the TFT 22, the pixel electrode 23 connected to the TFT 22 is charged, and the potential difference between the pixel electrode 23 and the common electrode changes. This potential difference controls the electric field applied to the liquid crystal layer 13, appropriately switching the alignment state of the liquid crystal molecules and driving the liquid crystal panel 10.

[0022] As described above, the source wiring 20 extends generally linearly along the Y-axis direction. A plurality of source wirings 20 are arranged at intervals in the X-axis direction. One end of each source wiring 20 is connected to a second circuit unit 17B (described later) via an extraction wiring, and a data signal (image signal) is supplied to the source wiring 20 from a source drive circuit in the second circuit unit 17B.

[0023] The gate wiring (an example of first wiring) 21 extends in a generally linear fashion along the X-axis direction, with both left and right ends extending from the display area AA toward the non-display area NAA. One end 21E of the gate wiring 21 is connected to a GDM (Gate Driver Monolithic circuit) section of the first circuit section 17A (described later) via a gate connection wiring 26 (described later), and a scanning signal is supplied to the gate wiring 21 from the GDM section. The GDM section is connected to the flexible substrate 16 via lead wiring (not shown) extending from a terminal arranged in the mounting area of ​​the flexible substrate 16. The GDM section is supplied with various signals transmitted by the flexible substrate 16.

[0024] 1, a circuit section 17 is provided in the non-display area NAA of the array substrate 11. The circuit section 17 includes a first circuit section 17A and a second circuit section 17B. A pair of first circuit sections 17A are arranged so as to sandwich the display area AA from both sides in the X-axis direction, but they may be provided on only one side.

[0025] The first circuit section 17A is provided in a strip-shaped range extending along the Y-axis direction. The first circuit section 17A is for supplying scanning signals to the gate lines 21, and is provided monolithically on the array substrate 11. The first circuit section 17A is a GDM (Gate Driver Monolithic) circuit. The first circuit section 17A includes a shift register circuit that outputs scanning signals at predetermined timing, a buffer circuit that amplifies the scanning signals, and the like.

[0026] The second circuit unit 17B is disposed at a position sandwiched between the display area AA and the flexible substrate 16 in the Y-axis direction. The second circuit unit 17B is provided in a strip-shaped range extending along the X-axis direction. The second circuit unit 17B is for supplying image signals (data signals) to the source lines 20, and is provided monolithically on the array substrate 11. The second circuit unit 17B includes a demultiplexer circuit (source signal division circuit) and the like. The second circuit unit 17B has a switch function that divides image signals (source signals) supplied by the source driver and distributes them to each source line 20.

[0027] Next, the configuration of the portion of the first circuit section 17A adjacent to the display area AA will be described with reference to Figs. 4 to 6. Fig. 4 is a plan view showing the portion of the first circuit section 17A (the first circuit section 17A on the left side in Fig. 1) on the array substrate 11 adjacent to the display area AA. As shown in Figs. 4 to 6, the first circuit section 17A has the following: A plurality of gate wirings (an example of first wirings) 21 made of a first metal film (an example of a first conductive film) 41, which are continuous from the display area AA and extend linearly in the X direction; A common trunk line (an example of a second line) 24 made of a first metal film 41 different from the gate line 21, which extends in a planar shape from the end 21E of the gate line 21 to the outer periphery side (the opposite side of the display area AA), a gate connection wiring (an example of a third wiring) 26 made of a second metal film (an example of a second conductive film) 42 disposed above the first metal film 41 via a first insulating film (an example of an insulating film) 25, extending linearly in the X direction, with an end 26E (the end on the right side in FIGS. 4 and 5 ) on the display area AA side overlapping the upper side of the end 21E of the gate wiring 21, and electrically connected to the gate wiring 21 via a first contact hole CH1 provided in the first insulating film 25; A plurality of common connection electrodes (an example of fourth wiring) 27 each made of a second metal film 42 different from the gate connection wiring 26, which are rectangular islands and overlap the upper layer side of the common main wiring 24 via the first insulating film 25 and are arranged adjacent to the gate connection wiring 26; A plurality of common branch wirings 30 made of a third metal film 43, each of which has a rectangular island shape and is superimposed on the upper layer side of the common connection electrode 27 via a second insulating film 28 and a planarizing film 29; The common connection wiring 31 is made of a third metal film 43 and extends linearly in the X direction from the common branch wiring 30 toward the display area AA, and is connected to the common wiring arranged in the display area AA.

[0028] Of the end 24E (the end extending in the Y direction on the right side in FIG. 5) of the planar common trunk wiring 24 on the display area AA side, a U-shaped notch 32 is formed in the portion overlapping the gate connection wiring 26 (the portion intersecting with the gate connection wiring 26) facing the opposite side of the display area AA. The notch width of the notch 32 is set to be larger than the line width of the gate connection wiring 26.

[0029] Among these, the plurality of rectangular island-shaped common connection electrodes 27 are all arranged such that their end portions 27E on the display region AA side (end portions extending in the Y direction on the right side in FIG. 5) are adjacent to the end portion 24E of the common main wiring 24 on the display region AA side. In this embodiment, the end portion 27E of the common connection electrode 27 is arranged slightly away from the end portion 24E of the common main wiring 24 on the display region AA side. The common connection electrode 27 is electrically connected to the common main wiring 24 through a plurality of second contact holes CH2 provided in the first insulating film 25 and formed at equal intervals along the end portion 27F (end portion extending in the X direction) of the common connection electrode 27 that is adjacent to the gate connection wiring 26. Of the plurality of second contact holes CH2, the second contact hole CH2E that is arranged closest to the display region AA side is provided adjacent to the end portion 27E of the island-shaped common connection electrode 27 that is arranged on the display region AA side.

[0030] The plurality of rectangular island-shaped common branch wirings 30 are slightly smaller than the common connection electrode 27, and are entirely overlapped on the common connection electrode 27. Each common branch wiring 30 is electrically connected to the common connection electrode 27 through a plurality of third contact holes CH3 formed in the second insulating film 28 and the planarizing film 29 and arranged at equal intervals at the end of the common branch wiring 30 extending in the X direction.

[0031] Fig. 6 is a partially enlarged cross-sectional view (cross-sectional view II in Fig. 4) of a portion adjacent to the display area AA in the non-display area NAA of the array substrate 11. In the non-display area NAA of the array substrate 11, as shown in Fig. 6, a first metal film (an example of a first conductive film) 41, a first insulating film (an example of an insulating film) 25, a second metal film (an example of a second conductive film) 42, a second insulating film 28, a planarizing film 29, and a third metal film 43 are laminated in this order from the lower layer side (the glass substrate Gs side).

[0032] The first metal film 41, the second metal film 42, and the third metal film 43 are each a single layer made of a single metal material selected from copper, titanium, aluminum, molybdenum, tungsten, etc., or a laminated film or alloy made of different metal materials, providing electrical conductivity and light-blocking properties. The first metal film 41 is a metal film that primarily constitutes the gate lines 21 and common trunk lines 24 extending from the display area AA in the non-display area NAA. In the display area AA, it constitutes the gate lines 21 as well as the gate electrodes of pixel transistors. The second metal film 42 is a metal film that primarily constitutes the gate connection lines 26 and the common connection electrode 27 in the non-display area NAA. In the display area AA, it constitutes the source lines 20 and the source and drain electrodes of pixel transistors. The third metal film 43 is a metal film that primarily constitutes the common branch lines 30 and the common connection line 31 in the non-display area NAA. The third metal film 43 is directly laminated on the common lines made of a transparent electrode film formed in the display area AA without an insulating film therebetween, and is connected to the common electrode.

[0033] The first insulating film 25 and the second insulating film 28 are made of inorganic materials such as silicon nitride (SiNx) and silicon oxide (SiO2), respectively. The planarizing film 29 is made of an organic insulating material (organic material) such as PMMA (acrylic resin), and its thickness is greater than that of the other insulating films 25 and 28, which are made of inorganic materials. The planarizing film 29 flattens the surface of the array substrate 11.

[0034] Of these, the first insulating film 25 keeps the lower first metal film 41 and the upper second metal film 42 in an insulated state. This first insulating film 25 functions as a gate insulating film that insulates the intersections between the gate lines 21 made of the first metal film 41 and the source lines 20 made of the second metal film 42 in the display area AA. As described above, the first insulating film 25 has first contact holes CH1 opened and formed at positions overlapping both the gate lines 21 and the gate connection lines 26 to connect them. Furthermore, the first insulating film 25 has multiple second contact holes CH2 opened and formed at positions overlapping both the common trunk lines 24 and the common connection electrodes 27 to connect them.

[0035] The second insulating film 28 and the planarizing film 29 keep the lower second metal film 42 and the upper third metal film 43 in an insulated state. As described above, the second insulating film 28 and the planarizing film 29 have a plurality of third contact holes CH3 formed therein at positions where they overlap with both the common branch wiring 30 and the common connection electrode 27 to connect them.

[0036] When such an array substrate 11 is manufactured by photolithography from the bottom up, and when the second metal film 42 has been formed, electric charges generated in the display area AA may flow from the gate line 21 to the gate connection line 26 through the first contact hole CH1, causing a potential difference to occur between the gate connection line 26 and the common main line 24 that overlaps with the gate connection line 26 via the first insulating film 25. If a potential difference occurs between the two metal films 41, 42 when the two metal films 41, 42 are arranged overlapping each other via the insulating film 25, ESD (electrostatic discharge) may occur between the isolated metal film patterns (between the common main line 24 and the gate connection line 26), destroying the first insulating film 25 and causing line defects.

[0037] To address such concerns, according to this embodiment, the common connection electrode 27 disposed adjacent to the gate connection line 26 is connected to the common main line 24, which has a large capacity, through the second contact hole CH2E provided adjacent to the display area AA, so that charges flowing into the gate connection line 26 are easily electrostatically discharged to the common connection electrode 27 side, which is not yet covered by the second insulating film 28, and are easily flowed from the common connection electrode 27 to the common main line 24 side through the second contact hole CH2. This prevents electrostatic discharge from occurring directly from the gate connection line 26 to the common main line 24 through the first insulating film 25, thereby preventing electrostatic breakdown of the first insulating film 25.

[0038] Furthermore, since the common main wiring 24 is provided with a notch 32, the overlapping portion of the gate connection wiring 26 and the common main wiring 24 (the portion where ESD is likely to occur) is closer to the second contact hole CH2E, making it easier for the charge that has flowed into the gate connection wiring 26 to be electrostatically discharged toward the common connection electrode 27.

[0039] Next, the effects will be described. The array substrate 11 of this embodiment has a display area AA for displaying an image and a non-display area NAA adjacent to the display area AA for not displaying an image. The display area AA is provided with a plurality of gate lines 21 made of a first metal film 41 and extending toward the non-display area NAA. The non-display area NAA is provided with a common trunk line 24 made of the first metal film 41 different from the gate lines 21 and extending in a planar shape, and a second metal film 42 disposed above the first metal film 41 with a first insulating film 25 interposed therebetween. The common trunk line 24 extends in the direction of extension of the gate lines 21 (X direction), and an end 26E of the non-display area NAA on the display area AA side is extended from the display area AA to the non-display area NAA. and an island-shaped common connection electrode 27 made of a second metal film 42 different from the gate connection wiring 26, overlapping the common main wiring 24 and arranged adjacent to the gate connection wiring 26, with its end 27E on the display area AA side in the non-display area NAA adjacent to the end 24E of the common main wiring 24 on the display area AA side in the non-display area NAA, and the common connection electrode 27 is connected to the common main wiring 24 by a second contact hole CH2E provided in a position of the common connection electrode 27 adjacent to the gate connection wiring 26 and adjacent to the display area AA.

[0040] According to the above configuration, when a metal film made of a metal material is patterned by photolithography in the manufacturing process of the array substrate 11, electric charges generated in the display area AA flow from the gate line 21 through the first contact hole CH1 into the gate connection line 26, and even if a potential difference occurs between the gate connection line 26 and the common trunk line 24 overlapping the gate connection line 26 with the first insulating film 25 interposed therebetween, the electric charges that flowed into the gate connection line 26 are easily electrostatically discharged toward the common connection electrode 27 arranged adjacent to the gate connection line 26, and are easily flowed from the common connection electrode 27 toward the common trunk line 24 with a larger capacity through the second contact hole CH2E. This prevents electrostatic discharge from the gate connection line 26 to the common trunk line 24 through the first insulating film 25, thereby preventing electrostatic breakdown of the first insulating film 25.

[0041] That is, it is possible to prevent an interlayer leakage current from occurring between the first metal film 41 and the second metal film 42 (first insulating film 25) due to insulating film breakdown caused by ESD at the portion where the first metal film 41 and the second metal film 42 stacked via the first insulating film 25 overlap. Moreover, with the configuration of this embodiment, it is only necessary to provide the second contact hole CH2E at a position adjacent to the end 27E of the common connection electrode 27 on the display area AA side, and there is no need to secure extra space or perform an additional process.

[0042] Furthermore, a notch 32 recessed toward the opposite side of the display area AA is provided at the position of the end 24E of the common main wiring 24 on the display area AA side in the non-display area NAA where the end intersects with the gate connection wiring 26. With this configuration, the position where the common main wiring 24 and the gate connection wiring 26 overlap is located farther from the display area AA than in a configuration without the notch 32, so that charge that has flowed from the gate wiring 21 into the gate connection wiring 26 is more likely to be electrostatically discharged toward the common connection electrode 27. In other words, electrostatic breakdown of the first insulating film 25 is less likely to occur.

[0043] Furthermore, the width of the notch 32 is set to be larger than the width of the gate connection wiring 26. With this configuration, compared to a configuration in which the width of the notch 32 is equal to or smaller than the width of the gate connection wiring 26, electric charges that have flowed from the gate wiring 21 into the gate connection wiring 26 are more likely to be electrostatically discharged toward the common connection electrode 27. In other words, with this configuration as well, electrostatic breakdown of the first insulating film 25 is less likely to occur.

[0044] <Embodiment 2> Next, a second embodiment will be described with reference to Fig. 7. Note that only the configurations different from the first embodiment will be described below, and the same configurations as those in the first embodiment will be given the same reference numerals, and duplicated explanations will be omitted.

[0045] The array substrate 111 of this embodiment differs from that of the first embodiment in the shape of an end 127F of the common connection electrode 127 that is arranged adjacent to the gate connection line 26. Specifically, the end 127F of the common connection electrode 127 of this embodiment has a protrusion 127G that protrudes in a rectangular shape toward the gate connection line 26 at the end on the display area AA side (the end on the right side in FIG. 7). A new second contact hole CH2F is additionally provided at a position adjacent to the corner of this protrusion 127G that is arranged on the display area AA side.

[0046] Furthermore, the array substrate 111 of this embodiment differs from the above embodiment in the depth dimension of the notch 132 provided in the common main wiring 124. Specifically, the depth dimension of the notch 132 is set so that the bottom 132A of the notch 132 is located farther from the display area AA than the second contact hole CH2F.

[0047] According to this embodiment, compared to the configuration of the first embodiment, the common connection electrode 127 is disposed at a position closer to the gate connection line 26, and the second contact hole CH2F can be provided there, so that charge that has flowed from the gate line 21 into the gate connection line 26 is more easily electrostatically discharged toward the common connection electrode 127. Furthermore, by configuring the bottom 132A of the cutout 132 to be at the same position as the second contact hole CH2F, or by arranging the bottom 132A of the cutout 132 at a position farther from the display area AA than the second contact hole CH2F, charge that has flowed from the gate line 21 into the gate connection line 26 is more easily electrostatically discharged toward the common connection electrode 127.

[0048] <Embodiment 3> Next, a third embodiment, which is a further improvement of the second embodiment, will be described with reference to Fig. 8. Note that only the configurations different from the second embodiment will be described below, and the same configurations as the second embodiment will be assigned the same reference numerals, and redundant description will be omitted.

[0049] The array substrate 211 of this embodiment differs from that of the second embodiment in the shape of a notch 232 provided at an end 224E of the common trunk wiring 224 on the display area AA side in the non-display area NAA. Specifically, the notch 232 of this embodiment has a two-step shape, and is composed of an opening side portion 232A having an opening width sufficiently larger than the width of the gate connection wiring 26 on the opening side of the notch 232 (the right side in FIG. 8), and a back side portion 232B continuing from the opening side portion 232A and having a width narrower than the opening side portion 232A but larger than the width of the gate connection wiring 26.

[0050] According to this embodiment, the electric charge that has flowed from the gate wiring 21 into the gate connection wiring 26 is more likely to be electrostatically discharged to the common connection electrode 127 side than in the second embodiment.

[0051] <Other embodiments> The technology disclosed in this specification is not limited to the embodiments described above and illustrated in the drawings, and the following embodiments, for example, are also included in the technical scope.

[0052] (1) In the above embodiments, the notches 32, 132, and 232 are provided at positions of the common trunk wiring 24, 124, and 224 that intersect with the gate connection wiring 26. However, the technical scope also includes a configuration in which no notches are provided. Furthermore, even when notches are provided, the configuration of the notches is not limited to that of the above embodiments.

[0053] (2) This technology is not limited to LCD panels, but can also be applied to other types of display panels, such as organic EL panels. [Explanation of symbols]

[0054] 10: Liquid crystal panel (display panel) 11, 111, 211: Array substrate 12: Counter substrate 17A: First circuit section 21: Gate wiring (first wiring) 24, 124, 224: Common main wiring (second wiring) 25: First insulating film (insulating film) 26: Gate connection wiring (third wiring) 27, 127: Common connection electrode (fourth wiring) 32, 132, 232: Notch 41: First metal film (first conductive film) 42: Second metal film (second conductive film) 127G: Protrusion AA: Display area CH1: First contact hole CH2, CH2E, CH2F: Second contact hole NAA: Non-display area

Claims

1. An array substrate having a display area for displaying an image and a non-display area disposed adjacent to the display area and not displaying an image, a plurality of first wirings made of a first conductive film and extending toward the non-display area are provided in the display area; In the non-display area, a second wiring formed of the first conductive film different from the first wiring and extending in a planar shape; a third wiring made of a second conductive film disposed above the first conductive film via an insulating film, extending along the extension direction of the first wiring, with an end portion of the third wiring on the display area side in the non-display area overlapping an end portion of the first wiring extended from the display area toward the non-display area and connected by a first contact hole; an island-shaped fourth wiring made of the second conductive film different from the third wiring, overlapping the second wiring and arranged adjacent to the third wiring, with an end of the fourth wiring on the display area side in the non-display area adjacent to an end of the second wiring on the display area side in the non-display area, The fourth wiring is adjacent to the third wiring and is connected to the second wiring by a second contact hole at a position adjacent to the end of the display area.

2. 2. The array substrate according to claim 1, wherein a notch recessed toward the opposite side of the display area is provided at an end of the second wiring on the display area side in the non-display area and at a position where the second wiring intersects with the third wiring.

3. 3. The array substrate according to claim 2, wherein the width of the notch is set to be larger than the width of the third wiring.

4. 4. The array substrate according to claim 2, wherein the depth of the notch is set so that the bottom of the notch is located farther from the display area than the second contact hole.

5. 3. The array substrate according to claim 1, wherein the fourth wiring has a protrusion that protrudes toward the third wiring at an end of the non-display area on the display area side, and the second contact hole is provided in the protrusion.

6. 3. A display panel comprising: the array substrate according to claim 1; and a counter substrate disposed opposite to the array substrate.

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