Substrate support having a plurality of buried electrodes - Patents.com

Abstract

To provide a method and a device for biasing a region of a substrate within a plasma-assisted processing chamber.SOLUTION: A plasma processing chamber 100 biases a substrate 115 or a region thereof to increase the potential difference between the substrate and plasma 135 formed within the processing chamber to accelerate ions from the plasma toward the active surface of a substrate region. A plurality of bias electrodes 238A to 238C are spatially arranged across a substrate support 227 in a pattern advantageous for managing uniformity of processing results across the substrate.SELECTED DRAWING: Figure 1

Description

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[0001] (Field) FIELD OF THE INVENTION The embodiments described herein relate generally to processing chambers used in semiconductor manufacturing, and more particularly to processing chambers having a substrate support assembly configured to bias a substrate and methods of biasing a substrate.

[0002] Description of Related Art Reliably producing high-aspect ratio features is one of the key technological challenges for the next generation of very large-scale integration (VLSI) and ultra-large-scale integration (ULSI) semiconductor devices. One method for forming high-aspect ratio features uses plasma-assisted etching processes to form high-aspect ratio openings in a material layer, such as a dielectric layer, of a substrate. In a typical plasma-assisted etching process, a plasma is formed in a processing chamber, and ions from the plasma are accelerated toward the substrate and an opening formed in an overlying mask, forming the opening in the material layer below the mask surface. Typically, low-frequency RF power, ranging from 400 kHz to 2 MHz, is coupled to the substrate, accelerating the ions toward the substrate and generating a bias voltage there. However, when RF power is coupled to the substrate, the substrate does not receive a single voltage relative to the plasma. In commonly used configurations, the potential difference between the substrate and the plasma oscillates at the frequency of the RF power from a value near zero to a maximum negative value. The nonuniform potential accelerating ions from the plasma to the substrate results in a wide range of ion energies at the substrate surface and the opening (feature) formed in the material layer. In addition, differences in ion trajectories due to the RF bias result in a large angular distribution of ions relative to the substrate surface. When etching openings in high aspect ratio features, a wide range of ion energies is undesirable because ions will not reach the bottom of the feature with sufficient energy to maintain a desirable etch rate. A large angular distribution of ions relative to the substrate surface is also undesirable because it will cause deformation of the feature profile, such as necking or bowing of its vertical sidewalls.

[0003] Therefore, there is a need in the art for the ability to provide high energy ions with a narrow angular distribution and energy range at the material surface of a substrate during plasma assisted etching processes.

[0004] The present disclosure relates generally to plasma-assisted or plasma-enhanced processing chambers. More particularly, embodiments herein relate to electrostatic chuck (ESC) substrate supports configured to provide individual pulsed (periodic) DC voltages to regions of a substrate during plasma-assisted or plasma-enhanced semiconductor manufacturing processes, and methods for biasing regions of a substrate.

[0005] In one embodiment, a substrate support assembly is provided that includes a substrate support comprising: a plurality of first electrodes within the substrate support, each electrode of the plurality of first electrodes being electrically insulated from and coplanar with every other electrode of the plurality of first electrodes, and each electrode of the plurality of first electrodes being configured to supply pulsed DC power to a region of the substrate by capacitive coupling therewith; and a second electrode disposed within the substrate support and electrically insulated from the plurality of first electrodes, the second electrode electrically clamping the substrate to the substrate support.

[0006] In other embodiments, a processing chamber is provided that includes one or more sidewalls and a bottom defining a processing volume and a substrate support, the substrate support including a plurality of first electrodes within the substrate support, each electrode of the plurality of first electrodes being electrically isolated from and coplanar with every other electrode of the plurality of first electrodes and configured to supply a pulsed DC bias to a region of the substrate by capacitive coupling therewith, and a second electrode disposed within the substrate support and electrically isolated from the plurality of first electrodes, the second electrode electrically clamping the substrate to the substrate support.

[0007] In another embodiment, a method for biasing a substrate with multiple periodic DC voltages is provided. The method includes flowing a process gas into a process chamber, forming a plasma from the process gas, electrically clamping the substrate to a substrate support disposed in the process chamber, and biasing the substrate across multiple regions. Biasing the substrate across multiple regions includes capacitively coupling multiple periodic DC voltages supplied by a switching system to multiple bias electrodes disposed on the substrate support to respective regions of the substrate through the capacitance of a first dielectric layer of the substrate support. The multiple periodic DC voltages herein include a range of frequencies and / or multiple polarities. [Brief explanation of the drawings]

[0008] In order that the foregoing features of the present disclosure may be understood in detail, a more particular description of the present disclosure, briefly summarized above, will now be made with reference to various embodiments, some of which are illustrated in the accompanying drawings. However, since the present disclosure may include other equally effective embodiments, it should be noted that the accompanying drawings illustrate only typical embodiments of the present disclosure and therefore should not be construed as limiting its scope. [Figure 1] 1 is a schematic cross-sectional view of a processing chamber having an electrostatic chuck (ESC) substrate support assembly disposed therein, according to one embodiment. [Figure 2A] 2 is an enlarged cross-sectional view of a substrate support assembly used in the processing chamber of FIG. 1. [Figure 2B] FIG. 2B is a top view of the substrate support assembly shown in FIG. 2A. [Figure 3] FIG. 1 is a flow diagram illustrating a method for biasing regions of a substrate during plasma-assisted processing according to embodiments described herein. Detailed Description

[0009] FIELD OF THE DISCLOSURE Embodiments of the present disclosure generally relate to plasma processing chambers, such as plasma-assisted or plasma-enhanced processing chambers. More specifically, embodiments herein relate to an electrostatic chuck (ESC) substrate support configured to provide a capacitively coupled pulsed DC voltage to a substrate disposed thereon during plasma-assisted or plasma-enhanced semiconductor manufacturing processes. Capacitive coupling of the substrate to a periodic DC power supply (applying a pulsed DC bias to the substrate) increases the potential difference between the substrate and the plasma formed in the processing chamber, thereby accelerating ions from the plasma toward the active surface of the substrate. In contrast to an RF bias, a pulsed DC bias provides a single potential to ions, accelerating them from the plasma to the substrate. The substrate support herein includes multiple bias electrodes, each independently connected to a portion of a pulsed DC power supply switching system and configured to provide an adjustable bias to a region of the substrate via capacitive coupling thereto. The multiple bias electrodes herein are spatially arranged across the substrate support in a pattern advantageous for managing uniformity of process results across the substrate.

[0010] 1 is a schematic cross-sectional view of a processing chamber 100 having an electrostatic chuck (ESC) substrate support assembly 200 disposed therein, according to one embodiment. In this embodiment, the processing chamber 100 is a plasma processing chamber, such as a plasma etch chamber, a plasma-enhanced deposition chamber (e.g., a plasma-enhanced chemical vapor deposition (PECVD) chamber or a plasma-enhanced atomic layer deposition (PEALD) chamber), or a plasma-based ion implantation chamber (e.g., a plasma doping (PLAD) chamber).

[0011] The processing chamber 100 features a chamber lid 103, one or more sidewalls 102, and a chamber bottom 104 that define a processing volume 120. A showerhead 112 having a plurality of openings 118 disposed therethrough is disposed on the chamber lid 103 and is used to uniformly distribute process gases from a gas inlet 114 into the processing volume 120. The showerhead 112 is connected to an RF power source 142, or in some embodiments, a VHF power source, to capacitively couple the process gases into a plasma 135. The processing volume 120 is fluidly connected to a vacuum, such as one or more dedicated vacuum pumps, via a vacuum outlet 152, which maintains the processing volume 120 at sub-atmospheric pressure conditions and evacuates the process gases and other gases therefrom. A substrate support assembly 200 disposed within the processing volume 120 is disposed on a support shaft 124 that sealingly extends through the chamber bottom 104. The support shaft 124 is connected to a controller 140 that raises and lowers the support shaft 124 and the substrate support assembly 200 disposed thereon to facilitate processing of the substrate 115 and transporting the substrate 115 in and out of the processing chamber 100. Typically, when the substrate support assembly 200 is in the raised or processing position, the substrate 115 is separated from the showerhead 112 by a gap of between about 0.75 inches and 1.75 inches (e.g., about 1.25 inches).

[0012] Substrates 115 are loaded into the process volume 120 through an opening 126 in one of the one or more sidewalls 102. The transfer opening 126 is conventionally sealed with a door or valve (not shown) during processing of the substrate 115. A plurality of lift pins 136 disposed on a lift pin hoop 134 are movably disposed through the substrate support assembly 200 to facilitate transfer of the substrate 115 thereto. The lift pin hoop 134 is connected to a lift hoop shaft 131 that sealingly extends through the chamber bottom 104, and the lift hoop shaft 131 is raised and lowered by an actuator 130. The substrate support assembly 200 has a substrate support 227 on which a substrate is placed for processing. When the lift pin hoop 134 is in the raised position, the plurality of lift pins 136 extend above the surface of the substrate support 227 to lift the substrate 115 therefrom, allowing access to the substrate 115 by a robotic handler (not shown). When the lift pin hoop 134 is in the lowered position, the plurality of lift pins 136 are flush with or below the surface of the substrate support 227, and the substrate 115 rests directly thereon for processing.

[0013] The substrate support assembly 200 herein includes a cooling base 125. A substrate support 227 is disposed and thermally coupled to the cooling base 125. The cooling base 125 of the substrate support assembly 200 is used to regulate the temperature of the substrate support 227, thereby regulating the temperature of the substrate 115 disposed on the substrate support surface 203, during processing. The cooling base 125 herein may include one or more fluid conduits 137 disposed therein. The fluid conduits 137 are fluidly connected to and in fluid communication with a coolant source 133, such as a refrigerant or water source. Typically, the cooling base 125 is formed of a corrosion-resistant, thermally conductive material (e.g., a corrosion-resistant metal such as aluminum, an aluminum alloy, or stainless steel) and is thermally coupled to the substrate support 227 by adhesive or mechanical means.

[0014] During processing, ion bombardment of the substrate 115 can heat the substrate 115 to undesirably high temperatures due to poor thermal conduction between the substrate 115 and the substrate support surface 203 when the processing volume 120 is underpressure. Therefore, in embodiments herein, a backside gas is supplied between the substrate 115 and the substrate support surface 203 during processing, which thermally couples the substrate 115 to the substrate support surface 203 and enhances heat transfer therebetween. Typically, the substrate support surface 203 includes a plurality of protrusions 228 extending therefrom that allow the backside gas to flow or occupy the space between the substrate 115 and the substrate support surface 203 when the substrate 115 is positioned thereon. The backside gas flows to the substrate support surface 203 through one or more gas conduits 147 disposed through the substrate support 227. Herein, the one or more gas conduits 147 are connected to a thermally conductive inert backside gas source 146, such as a helium gas source.

[0015] 2A is an enlarged cross-sectional view of a substrate support assembly 200 used in the processing chamber 100 of FIG. 1. FIG. 2B is a top view of the substrate support assembly 200 shown in FIG. 2A. Herein, the substrate support 227 includes a first layer 227A and a second layer 227B, each of which is formed from a dielectric material including a metal oxide or metal nitride, or a mixture of metal oxides or metal nitrides, such as Al2O3, AlN, YO3, or a combination thereof. In some embodiments, the first layer 227A is formed from a dielectric material having a breakdown voltage of about 20 V / μm to about 200 V / μm (e.g., about 100 V / μm to about 200 V / μm, or about 20 V / μm to about 100 V / μm). In one embodiment, first layer 227A is formed from 99.5% alumina having a breakdown voltage of about 9 kV at about 160 μm. In some embodiments, substrate support 227 is formed by bonding a bulk dielectric material to second layer 227B and multiple electrodes disposed therein or thereon, and then grinding the bulk dielectric material to a desired thickness D to form first layer 227A. Typically, thickness D of first layer 227A is between about 5 μm and about 300 μm (e.g., between about 100 μm and about 300 μm, e.g., about 160 μm). In other embodiments, first layer 227A is formed using any suitable coating method, such as CVD, PECVD, ALD, PEALD, evaporation, sputtering, plasma arc coating, aerosol coating, or a combination thereof.

[0016] The plurality of electrodes disposed on and / or embedded in the substrate support herein includes a plurality of bias electrodes 238A-C and a single ESC electrode 222. Each electrode of the plurality of bias electrodes is electrically isolated from all other electrodes of the plurality of bias electrodes and from the single ESC electrode 222. Each electrode of the plurality of bias electrodes 238A-C herein is configured to supply one or more independent pulsed DC biases to a respective region of the substrate 115 by capacitive coupling therewith. The single ESC electrode 222 applies a potential between the substrate 115 and the substrate support surface 203, thereby providing a clamping force therebetween. Typically, the ESC electrodes are connected to a static DC power supply. Herein, the DC power supply provides a voltage of about −5000 V to about 5000 V (e.g., about 100 V to about 4000 V, e.g., about 1000 V to about 3000 V, e.g., about 2000 V).

[0017] In embodiments herein, the substrate support 227 may be configured to support a 300 mm diameter substrate and may include two to twenty bias electrodes (such as the three bias electrodes 238A-C shown). However, larger substrate supports for processing larger substrates and / or substrates of various shapes may include any number of bias electrodes. The multiple bias electrodes 238A-C are each formed of one or more electrically conductive material portions (such as metal mesh, foil, plate, or combination thereof). In some embodiments, each of the multiple bias electrodes 238A-C is formed of two or more discontinuous electrically conductive material portions (such as multiple metal meshes, foils, plates, or combinations thereof), which are electrically connected to one or more connectors (not shown) disposed on the substrate support 227, such that the electrically connected discontinuous material portions form a single electrode (such as the center bias electrode 238A, the middle bias electrode 238B, or the outer bias electrode 238C).

[0018] The plurality of bias electrodes 238A-C are spatially arranged across the substrate support 227 in a pattern advantageous for managing uniformity of process results across the substrate 115. In the embodiment shown in FIG. 2A , the circular plate of the central bias electrode 238A and the discontinuous annular portions of the bias electrodes 238B-C define a plurality of concentric zones. Other spatial arrangements include a spoke pattern, a grid pattern, a line pattern, a spiral pattern, an interdigitated pattern, a random pattern, or a combination thereof. Each of the plurality of bias electrodes 238A-C herein is coplanar with all other electrodes of the plurality of bias electrodes and with the single ESC electrode 222. The single ESC electrode 222 is disposed planar with the substrate support 227 and parallel to the substrate support surface 203. Each of the plurality of bias electrodes 238A-C is electrically insulated from the single ESC electrode 222 by forming an opening in the single ESC electrode 222 so that the dielectric material of the substrate support 227 is disposed therebetween. In other embodiments, each electrode of the plurality of bias electrodes 208A-C, or a portion thereof, is coplanar with at least a portion of all other electrodes of the plurality of bias electrodes, and the plurality of bias electrodes 208A-C is closer to the substrate support surface 203 than the single ESC electrode 222.

[0019] Here, each of the multiple bias electrodes 238A-C is independently electrically connected to a portion of the DC power switching system 150, which includes multiple solid-state pulsers / switchers. Here, the multiple first switches S1, S3, S5 and the multiple second switches S2, S4, S6 can convert high-voltage (HV) DC power into a periodic DC voltage having a frequency ranging from approximately 10 Hz or less to approximately 100 kHz. The multiple first switches S1, S3, S5 and the multiple second switches S2, S4, S6 can further convert the high-voltage (HV) DC power into a periodic DC voltage having a duty cycle ranging from 2% to 98%. The switches S1-S6 operate periodically at a frequency, or according to any pattern or no pattern as needed. Each of the multiple bias electrodes is electrically connected to one of the multiple first switches S1, S3, S5 and one of the multiple second switches S2, S4, S6.

[0020] Herein, the plurality of first switches S1, S3, S5 are electrically connected to a first DC voltage source 156B, which may be, for example, a positive (+ve) voltage source, and the plurality of second switches S2, S4, S6 are electrically connected to a second DC voltage source 156A, which may be, for example, a negative (-ve) voltage source. In other embodiments, the two voltage sources 156A and 156B may be power sources with different voltages, both positive or both negative. Herein, the first DC voltage source 156B and the second DC voltage source 156A provide a positive or negative DC bias, each with a voltage magnitude between about 0 V and about 10 kV.

[0021] Each set of switches, such as S1 and S2, S3 and S4, or S5 and S6, operates independently to provide a respective frequency, pattern, or operation of a periodic DC voltage of positive or negative polarity to each bias electrode 238A-C of the substrate support 227, which in turn capacitively couples to provide a respective pulsed DC bias to a respective region of the substrate 115 disposed on the substrate support 227. Typically, applying a negative DC pulse to the substrate region increases the potential difference between the substrate region and the plasma 135, causing the substrate region to become more negatively charged than the plasma during the pulse. This negative DC bias accelerates positively charged species within the plasma toward the surface of the substrate region, thereby achieving processing of the substrate region. Applying a positive DC pulse to the substrate region increases the potential difference between the substrate region and the plasma 135, causing the substrate region to become more positively charged than the plasma during the pulse. This positive DC bias accelerates negatively charged species within the plasma toward the surface of the substrate region, thereby achieving processing of the substrate region. The ability to adjust the frequency, duty cycle, and / or duration of the periodic DC voltage supplied to various substrate regions for both positive and negative DC bias conditions allows for tuning and improving process uniformity across the substrate. Another useful feature is that the ability to apply both positive and negative DC bias pulses provides charge neutralization of the substrate region, so that the surface of the substrate region can be periodically driven to a neutral charge state.

[0022] 3 is a flow diagram illustrating a method 300 of biasing a region of a substrate during plasma-assisted processing according to embodiments described herein. At step 310, the method 300 includes flowing a process gas into a processing chamber, and at step 320, the method includes forming a plasma from the process gas.

[0023] In step 330, the method 300 includes electrically clamping the substrate to a substrate support disposed in the processing chamber using a chuck electrode disposed on the substrate support, where the substrate support includes a first dielectric layer and a second dielectric layer.

[0024] In step 340, method 300 includes applying multiple periodic DC voltages to multiple bias electrodes disposed within the substrate support, where each periodic DC voltage provides a respective pulsed DC bias to a region of the substrate through capacitive coupling therewith. In some embodiments, the multiple periodic DC voltages include multiple polarities, multiple frequencies, multiple duty cycles, and / or multiple durations. The pulsed DC bias accelerates ions in the plasma formed in step 330 toward the substrate to perform material processing, such as deposition or removal, on the substrate. It should be noted that the plasma may be formed after step 320, after step 330, after step 340, or after step 350.

[0025] The substrate support assemblies and methods described herein enable capacitively coupled pulsed DC biasing of individual substrate regions during plasma-assisted processing, compatible with the use of electrostatic clamping forces. Pulsed DC biasing improves control of ion energy and angular distributions at the substrate surface and / or regions thereof, and at feature openings formed therein. Improved control is desirable, at least in the formation of features requiring high aspect ratios and / or perpendicular etch profiles. Examples include silicon etching for shallow trench isolation (STI) applications or for silicon fins used in FinFET technology. The ability to apply DC pulses of varying frequency, duty cycle, polarity, and / or duration to different regions of the substrate allows for tailoring and improving process uniformity across the substrate.

[0026] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the present disclosure may be made without departing from the basic scope thereof, which scope is defined by the following claims.

Claims

[Claim 1] 1. A method for processing a substrate, comprising: placing the substrate on a substrate support disposed within a processing volume of a processing chamber; flowing a process gas into the process volume; forming a plasma of a process gas; biasing a plurality of regions of the substrate with a corresponding plurality of periodic DC voltages; each of the plurality of periodic DC voltages is independently controlled using a pulsed DC bias switching system including a plurality of first switches and a plurality of second switches; The method, wherein each first switch of the plurality of first switches is electrically connected to a first DC power source and each second switch of the plurality of second switches is electrically connected to a second DC power source.

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