Semiconductor rectifier element and method for manufacturing the same

Abstract

To provide a conductor rectifier and a manufacturing method of the same.SOLUTION: A semiconductor rectifier element comprises: an epitaxial layer having a top surface and a bottom surface; a first concave groove 41 that includes a first side wall 41C and a second side wall 41D that are extended from the top surface to the bottom surface and are opposite each other, and a first bottom surface 41B connecting both side walls; a second concave groove 42 that includes a third side wall 42C and a fourth side wall 42D that are adjacent to the first concave groove and are opposite to each other, and a second bottom surface 42B connecting both side walls; a first dope region 221 that is extended from the top surface to the bottom surface and is adjacent to the first bottom surface of at least a part of the first side wall of the first concave groove; a second dope region 222 that is adjacent to the first dope region, is separated therefrom, is extended from the top surface to the bottom surface, and is adjacent to the third side wall of the second concave group, the fourth side wall, and the second bottom surface; a gate structure that is installed on the top surface between the first and second concave grooves and has a bottom surface adjacent to the first and second dope regions; and a contact metal layer.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The present invention relates to the structure of a semiconductor rectifying element and a method for manufacturing the same, and more specifically, to a structure having a semiconductor rectifying element formed on silicon carbide and a method for manufacturing the same.

Background Art

[0002] As is well known, semiconductor materials have a wide bandgap (such as a bandgap energy value Eg exceeding 1.1 eV), low on-resistance (RON), high thermal conductivity, high operating frequency, and high charge carrier saturation velocity, and are very suitable for the production of electronic components such as diodes and transistors, especially for applications to power supplies. A material having the above characteristics and designed for manufacturing electronic components is silicon carbide (SiC). In particular, silicon carbide is superior to silicon in terms of the above-listed characteristics in terms of its different polytypes (such as 3C-SiC, 4H-SiC, 6H-SiC).

[0003] An electronic element on a silicon carbide substrate has various advantages such as a lower dynamic output resistance, a smaller leakage current, a higher operating temperature, and a higher operating frequency compared to a similar element on a silicon substrate. A semiconductor structure using silicon carbide as a substrate needs to be activated by an annealing process at a high temperature (for example, 1700 °C or higher), but polycrystalline silicon and common gate materials cannot withstand such a high-temperature annealing process, making process integration difficult and increasing the cost of the entire process.

Summary of the Invention

[0004] Embodiments of the present disclosure relate to semiconductor rectifier elements. The semiconductor rectifier element includes an epitaxial layer having a top surface and a bottom surface facing each other; a first groove extending from the top surface to the bottom surface and including a first side wall and a second side wall facing each other, and a first bottom surface connecting the first side wall and the second side wall; a second groove extending from the top surface to the bottom surface and adjacent to the first groove, including a third side wall and a fourth side wall facing each other, and a second bottom surface connecting the third side wall and the fourth side wall; and a second groove extending from the top surface to the bottom surface and including the second side wall of the first groove and at least the The material includes: a first doped region adjacent to a portion of the first bottom surface; a second doped region adjacent to the first doped region, separated from each other, extending from the top surface to the bottom surface, and adjacent to the third side wall, the fourth side wall, and the second bottom surface of the second groove; a gate structure installed on the top surface between the first groove and the second groove, with its bottom surface adjacent to the first and second doped regions; and a contact metal layer installed on the top surface of the epitaxial layer along the first groove, the gate structure, and the second groove.

[0005] Embodiments of the present disclosure relate to a method for manufacturing a semiconductor rectifier element. The method includes forming a patterned layer on a silicon carbide layer, etching the silicon carbide layer using the patterned layer as a mask to form a first groove and a second groove adjacent to the first groove, ion implantation of the silicon carbide layer using the patterned layer as a mask, thermal annealing of the silicon carbide layer, and forming a gate structure on the silicon carbide layer between the first groove and the second groove after the thermal annealing, wherein the gate structure has a first sidewall and a second sidewall facing each other, the first sidewall and one sidewall of the first groove are continuous sidewalls, and the second sidewall and one sidewall of the second groove are also continuous sidewalls.

[0006] By reading the following detailed description in conjunction with the drawings, one can best understand the aspects of some embodiments of this disclosure. It should be noted that the various structures do not have to be constructed in proportion. In practice, the size of the various structures can be arbitrarily enlarged or reduced for the sake of clarity in the discussion. [Brief explanation of the drawing]

[0007] [Figure 1] Figure 1 shows one or more steps in a method for manufacturing a semiconductor rectifier element based on several embodiments of this invention. [Figure 2] Figure 2 shows one or more steps in a method for manufacturing a semiconductor rectifier element based on several embodiments of this invention. [Figure 3] Figure 3 shows one or more steps in a method for manufacturing a semiconductor rectifier element based on several embodiments of this invention. [Figure 4] Figure 4 shows one or more steps in a method for manufacturing a semiconductor rectifier element based on several embodiments of this invention. [Figure 5] Figure 5 shows one or more steps in a method for manufacturing a semiconductor rectifier element based on several embodiments of this invention. [Figure 6] Figure 6 shows one or more steps in a method for manufacturing a semiconductor rectifier element based on several embodiments of this invention. [Figure 7] Figure 7 shows one or more steps in a method for manufacturing a semiconductor rectifier element based on several embodiments of this invention. [Figure 8] Figure 8 shows one or more steps in a method for manufacturing a semiconductor rectifier element based on several embodiments of this invention. [Figure 9] Figure 9 shows one or more steps in a method for manufacturing a semiconductor rectifier element based on several embodiments of this invention. [Figure 10] Figure 10 shows one or more steps in a method for manufacturing a semiconductor rectifier element based on several embodiments of this invention. [Figure 11]Figure 11 shows one or more steps in a method for manufacturing a semiconductor rectifier element based on several embodiments of this invention. [Figure 12] Figure 12 shows one or more steps in a method for manufacturing a semiconductor rectifier element based on several embodiments of this invention. [Figure 13] Figure 13 shows one or more steps in a method for manufacturing a semiconductor rectifier element based on several embodiments of this invention. [Figure 14] Figure 14 shows one or more steps in a method for manufacturing a semiconductor rectifier element based on several embodiments of this invention. [Figure 15] Figure 15 is a top view of a semiconductor rectifier element based on a different embodiment of this invention. [Figure 16] Figure 16 is a top view of a semiconductor rectifier element based on a different embodiment of this invention. [Figure 17] Figure 17 shows one or more steps in a method for manufacturing a semiconductor rectifier element based on several embodiments of this invention. [Figure 18] Figure 18 shows one or more steps in a method for manufacturing a semiconductor rectifier element based on several embodiments of this invention. [Figure 19] Figure 19 shows one or more steps in a method for manufacturing a semiconductor rectifier element based on several embodiments of this invention. [Figure 20] Figure 20 shows one or more steps in a method for manufacturing a semiconductor rectifier element based on several embodiments of this invention. [Figure 21] Figure 21 shows one or more steps in a method for manufacturing a semiconductor rectifier element based on several embodiments of this invention. [Figure 22] Figure 22 shows one or more steps in a method for manufacturing a semiconductor rectifier element based on several embodiments of this invention. [Figure 23] Figure 23 shows one or more steps in a method for manufacturing a semiconductor rectifier element based on several embodiments of this invention. [Figure 24] Figure 24 shows one or more steps in a method for manufacturing a semiconductor rectifier element based on several embodiments of this invention. [Figure 25] Figure 25 shows one or more stages in a method of manufacturing a semiconductor rectifying element according to some embodiments of the present case. [Figure 26] Figure 26 shows one or more stages in a method of manufacturing a semiconductor rectifying element according to some embodiments of the present case. [Figure 27] Figure 27 shows one or more stages in a method of manufacturing a semiconductor rectifying element according to some embodiments of the present case. [Figure 28] Figure 28 shows one or more stages in a method of manufacturing a semiconductor rectifying element according to some embodiments of the present case. [Figure 29] Figure 29 shows one or more stages in a method of manufacturing a semiconductor rectifying element according to some embodiments of the present case. [Figure 30] Figure 30 shows one or more stages in a method of manufacturing a semiconductor rectifying element according to some embodiments of the present case.

Mode for Carrying Out the Invention

[0008] Identical or similar components are denoted by like reference numerals throughout the drawings and the detailed description. Some embodiments of the present disclosure can be readily understood from the following detailed description and the drawings.

[0009] The following disclosure provides numerous different embodiments or examples for implementing various features of the target being provided. Specific examples of parts and arrangements are described below. Of course, these are merely examples and should not be limiting. In this disclosure, a reference to forming a first feature above or on a second feature may include embodiments in which the first and second features form direct contact, and may also include embodiments in which another feature is formed between the first and second features, where the first and second features do not form direct contact. Also in this disclosure, reference numerals and / or letters may be duplicated within each embodiment. This duplication is done for simplicity and clarity and does not in itself indicate a relationship between each embodiment and / or arrangement discussed.

[0010] The following sections discuss in detail embodiments of this disclosure. However, it should be understood that this disclosure provides many application concepts that can be materialized in various specific environments. The specific embodiments discussed are illustrative and do not limit the scope of this disclosure.

[0011] This disclosure provides a structure for a semiconductor rectifier element and a method for manufacturing the same. Compared to general methods for manufacturing semiconductor rectifier elements, the method of this disclosure includes an activation step before forming the polycrystalline silicon material or dielectric material, thereby properly aligning the rectifier element on silicon carbide. Furthermore, the method of this disclosure further includes a gate structure self-alignment step, which reduces the potential damage to the substrate that may occur during the patterning process, while also reducing the use of photomasks and thus lowering the overall process cost.

[0012] Figures 1 to 14 show one or more steps in the manufacturing method of a semiconductor rectifier element 1 based on several embodiments of this invention. At least some of these drawings have already been simplified to better illustrate aspects of this disclosure.

[0013] Referring to Figure 1, the manufacturing method for the semiconductor rectifier element 1 includes forming a silicon carbide layer 12 by epitaxial growth on the surface 11A of the semiconductor material layer 11, and forming doped regions 21 within the silicon carbide layer 12. The semiconductor material layer 11 has opposing surfaces 11A and 11B. In some embodiments, surfaces 11A and 11B may be horizontal. For ease of explanation, the direction perpendicular to surfaces 11A and 11B is defined as the vertical direction, and the direction perpendicular to the vertical direction is defined as the horizontal direction. In some embodiments, surface 11A is the top surface of the semiconductor material layer 11, and surface 11B is the bottom surface of the semiconductor material layer 11. In some embodiments, surface 11A is the top surface of the silicon wafer. The material of the semiconductor material layer 11 may be polycrystalline silicon or single-crystal silicon. The semiconductor material layer 11 may include doped regions. For example, the semiconductor material layer 11 includes a p-type doped region and an n-type doped region (also configurable as a p-type transistor) that can be configured as an n-type transistor. The n-type doped region is doped with an n-type dopant, such as phosphorus, arsenic, or other n-type dopants or combinations thereof. The p-type doped region is doped with a p-type dopant, such as boron, indium, or other p-type dopants or combinations thereof. The n-type or p-type doped region can be formed by performing an ion implantation step, a diffusion step, and / or other suitable doping steps. The semiconductor material layer 11 has a first-type doped region that extends from surface 11A to surface 11B and covers the entire surface 11A. For ease of explanation, the first type is described below using the n-type as an example, but the disclosure is not limited thereto, and the n-type (first-type) or p-type (second-type) semiconductor material layer 11 can be adjusted according to the conductivity type of the semiconductor rectifier element 1.

[0014] The silicon carbide layer 12 has the same conductivity type as the semiconductor material layer 11, i.e., it is type 1 doping. In some embodiments, the N-type silicon carbide layer 12 is formed by implanting N-type electrically charged ions during epitaxial growth, so there is no need to perform separate ion implantation. Since the N-type electrically charged ions are distributed throughout the silicon carbide layer 12, a doped region 25 can be formed located throughout the silicon carbide layer 12. The silicon carbide layer 12 has a surface 12A and a surface 12B opposite to surface 12A. In some embodiments, surfaces 12A and 12B may be horizontal. In some embodiments, surface 12A is the top surface of the silicon carbide layer 12, and surface 12B is the bottom surface of the silicon carbide layer 12. In some embodiments, the surface of surface 12B of the silicon carbide layer 12 is in contact with surface 11A of the semiconductor material layer 11.

[0015] Next, ion implantation is performed on the surface 12A of the silicon carbide layer 12 to form a doped region 21 having type 2 doping. In some embodiments, the doped region 21 is a doped region that serves as a circuit termination and is also called a termination doped region. In some embodiments, the doped region 21 serves as a guard ring. In some embodiments, the doped region 21 is annular when viewed from a top view (not depicted in the figure). The method for forming the doped region 21 involves forming an oxide layer on the surface 12A of the silicon carbide layer 12, and then forming a patterned photomask on the oxide layer. The oxide layer is patterned using the patterned photomask, and after removing the photomask, ion implantation is performed on the surface 12A of the silicon carbide layer 12 using the patterned oxide layer as a mask. The patterned oxide layer is removed after the ion implantation step. The method for forming the doped region 21 described above is based on examples provided in some embodiments of this disclosure, but this disclosure is not limited thereto. Furthermore, since the doped region 21 cancels out the conductivity of the doped region 25, electrically speaking, the coverage area of ​​the doped region 25 is defined as a part of the silicon carbide layer 12 outside the doped region 21.

[0016] Referring to Figure 2, the manufacturing method for the semiconductor rectifier element 1 includes forming a patterned layer 51 on the surface 12A of the silicon carbide layer 12 of the semiconductor material, exposing a portion of the silicon carbide layer 12 and covering a portion of the doped region 21. In some embodiments, the patterned layer 51 exposes a portion of the doped region 21 and a portion of the silicon carbide layer 12 connected to the doped region 21. In some embodiments, the patterned layer 51 has openings 511 and 512, exposing a portion of the silicon carbide layer 12. The patterned layer 51 may be a material layer suitable as a mask for a subsequent etching process, such as a photomask, a curing layer, or a dielectric layer (e.g., an oxide layer or a nitride layer). In some embodiments, the patterned layer 51 contains an oxide (e.g., silicon oxide). In some embodiments, an oxide layer is formed to cover the entire surface 12A of the silicon carbide layer 12, a patterned photomask is formed on the oxide layer, a portion of the oxide layer is removed using the patterned photomask, and then the photomask is removed to form a patterned layer 51 that exposes a portion of the silicon carbide layer 12.

[0017] Referring to Figure 3, the manufacturing method for the semiconductor rectifier element 1 includes performing an etching process on the silicon carbide layer 12 using the patterned layer 51 as a mask to form a plurality of grooves (grooves 41, 42 shown in Figure 3). The plurality of grooves are adjacent to each other and extend from surface 12A to surface 12B of the silicon carbide layer 12. Since they are formed through the same etching step, the plurality of grooves have approximately the same depth. In some embodiments, the bottom surfaces of the plurality of grooves are located on approximately the same horizontal plane 12D. In some embodiments, the depth D41 of groove 41 is approximately the same as the depth D42 of groove 42. In some embodiments, the depth D41 of groove 41 or the depth D42 of groove 42 is between 4000 and 5000 angstroms. In some embodiments, the bottom surface 41B of groove 41 and the side wall 42D of groove 41 have approximately the same horizontal height and are located on the horizontal plane 12D. In some embodiments, the bottom surface 41B and the side wall 42D of the groove 41 are located on the same horizontal plane 12D. In some embodiments, the depth of the multiple grooves 41, 42 is less than the depth of the doped region 21. The patterned layer 51 exposes a portion of the doped region 21, and since the depth of the groove 41 is less than the depth of the doped region 21, the doped region 21 is adjacent to a portion of the side wall 41D and bottom surface 41B of the groove 41. Also, since the multiple grooves (including grooves 41, 42) are formed using the patterned layer 51 as a mask, the patterned layer 51 corresponds to multiple openings of the multiple grooves. The side walls 41C and 41D of the groove 41 are aligned with the side walls of the corresponding first opening 511 of the patterned layer 51, and the side walls 42C and 42D of the groove 42 are aligned with the side walls of the corresponding second opening 512 of the patterned layer 51, of which the side walls 41C and 41D are individually connected to the bottom surface 41B and face each other, and the side walls 42C and 42D are individually connected to the bottom surface 42B and face each other. In some embodiments, the first opening 511 of the patterned layer 51 overlaps with a portion of the doped area 21 along the vertical direction, as shown in Figure 3.

[0018] Referring to Figure 4, the manufacturing method of the semiconductor rectifier element 1 includes ion implantation into the silicon carbide layer 12 using the patterned layer 51 as a mask to form a plurality of doped regions 22, of which the plurality of doped regions 22 have the same conductivity type as doped region 21. Similar to the above description, since the doped region 22 cancels out the conductivity of doped region 25, electrically speaking, the coverage area of ​​doped region 25 is defined as a part of the silicon carbide layer 12 outside of doped regions 21 and 22.

[0019] The multiple doped regions 22 include doped regions 221 and 222. In some embodiments, doped region 221 extends from surface 12A to surface 12B and is adjacent to a portion of the sidewall 41C and bottom surface 41B of the groove 41. In some embodiments, doped region 221 extends along a portion of the sidewall 41C and bottom surface 41B of the groove 41 into the interior of the silicon carbide layer 12. To individually diffuse the multiple doped regions 22 laterally along their corresponding groove sidewalls, the steps shown in Figure 4 include at least one oblique ion implantation. In some embodiments, the steps shown in Figure 4 include multiple ion implantations, of which at least one is an oblique ion implantation. In some embodiments, the steps shown in Figure 4 include multiple oblique ion implantations, and different inclination angles can be set for each implantation to achieve a desired lateral diffusion range. In some embodiments, the depth from surface 12A to surface 12B of the doped region 21 is greater than or equal to the depth from surface 12A to surface 12B of the doped region 22.

[0020] Since the patterned layer 51 exposes a portion of the doped region 21, the doped region 221 is in contact with the doped region 21. In some embodiments, during the ion implantation step in Figure 4, ions are implanted into the exposed doped region 21, and the region 211 shown by the dashed box in Figure 4 represents the region in the doped region 21 into which secondary ions have been implanted; therefore, region 211 has a high doping concentration. The multiple doped regions 22 are bulk doped regions of the semiconductor rectifier element 1, and doped region 21 is a terminating doped region. Region 211 is covered with a dielectric material in a subsequent step and does not act as a bulk doped region, but as a terminating doped region. For ease of explanation, region 211 is defined as part of the doped region 21, and the boundary between region 211 and doped region 221 corresponds to the boundary between doped region 21 and doped region 221. In some embodiments, region 211 has a higher doping concentration than doped region 221. In some embodiments, region 211 has a higher doping concentration than the rest of doped region 21. In some embodiments, doped region 22 has a different doping concentration than doped region 21. In some embodiments, the doping concentration of doped region 21 is 1 * 10 per cubic centimeter. 17 ~1*10 18 (cm -3 ) is between. In some embodiments, the doping concentration of doped region 22 is 1*10 16 ~1*10 17 cm -3 It is between these two points.

[0021] The doped region 222 is adjacent to and separate from the doped region 221. In some embodiments, the doped region 222 extends from surface 12A to surface 12B and is adjacent to the opposing side walls 42C, 42D and bottom surface 42B of the groove 42. In some embodiments, the doped region 222 extends along the side walls 42C, 42D and bottom surface 42B of the groove 42 into the interior of the silicon carbide layer 12. Since the doped region 222 is formed by the same ion implantation step as the doped region 221, it has approximately the same depth and doping concentration as the doped region 221.

[0022] Referring to Figure 5, the manufacturing method for the semiconductor rectifier element 1 includes forming a carbon-containing layer 52 to cover the silicon carbide layer 12, and then performing high-temperature annealing on the silicon carbide layer 12. In some embodiments, the carbon-containing layer 52 covers the entire silicon carbide layer 12. In some embodiments, the carbon-containing layer 52 conformally covers the silicon carbide layer 12. Since the silicon carbide layer 12 is subsequently subjected to high-temperature annealing to activate the ions in the doped regions 21 and 22, the carbon-containing layer 52 can prevent silicon deposition at high temperatures. After the carbon-containing layer 52 is formed, high-temperature annealing is performed on the silicon carbide layer 12. In some embodiments, the temperature of the high-temperature annealing step is between 1400 and 2500 degrees Celsius (°C). In some embodiments, the time for performing the high-temperature annealing step is between 20 and 40 minutes. The carbon-containing layer 52 is removed after the high-temperature annealing step.

[0023] Referring to Figure 6, the manufacturing method for the semiconductor rectifier element 1 includes forming a dielectric layer 13 to cover the doped region 21 after the high-temperature annealing step. To ensure that the dielectric layer 13 covers the entire doped region 21, the dielectric layer 13 further covers the doped region 21 and a portion of the adjacent doped region 221. The method for forming the dielectric layer 13 can be described by referring to the method for forming the patterned layer 51 described above, so it will not be described again here. In some embodiments, the dielectric layer 13 covers a portion of the side wall 41D and bottom surface 41B of the groove 41. In some embodiments, the dielectric layer 13 contains an oxide (e.g., silicon oxide).

[0024] Referring to Figure 7, the manufacturing method for the semiconductor rectifier element 1 includes forming the dielectric layer 13, then forming a dielectric layer 14 to fill the remaining grooves 41 and 42. In some embodiments, a vapor deposition process is performed to form a dielectric material, covering the entire silicon carbide layer 12, and then dry etching is performed on the dielectric material to remove the dielectric material above the surface 12A, thereby forming the dielectric layer 14. In some embodiments, the dielectric material and the silicon carbide layer 12 have an etching selectivity ratio, so the dry etching step is stopped at the surface 12A of the silicon carbide layer 12.

[0025] The top surface 14A of the dielectric layer 14 is flush with or coplanar with the surface 12A of the silicon carbide layer 12. The dielectric layer 14 may include multiple portions that fill a plurality of grooves. In some embodiments, the dielectric layer 14 includes a partial dielectric layer 141 located in a groove 41 and a partial dielectric layer 142 located in a groove 42. In some embodiments, the top surface 141A of the partial dielectric layer 141 is flush with or coplanar with the surface 12A of the silicon carbide layer 12. In some embodiments, the top surface 142A of the partial dielectric layer 142 is flush with or coplanar with the surface 12A of the silicon carbide layer 12. In some embodiments, the top surface 142A of the partial dielectric layer 142 is located at approximately the same horizontal height as the top surface 142A of the partial dielectric layer 142. Furthermore, the dielectric layer 14 has a different dielectric material from the dielectric layer 13 so that there can be an etching selectivity ratio between the dielectric layer 13 and the dielectric layer 14 in a subsequent etching process. In some embodiments, the dielectric layer 14 includes a nitride (e.g., silicon nitride).

[0026] Referring to Figure 8, the manufacturing method for the semiconductor rectifier element 1 includes removing a portion of the silicon carbide layer 12 so that the top surface of the exposed portion of the silicon carbide layer 12 is lower than the top surface 14A of the dielectric layer 14. In some embodiments, the silicon carbide layer 12 is dry-etched to remove the portion of the silicon carbide layer 12 that is not covered by the dielectric layers 13 and 14. After the dry etching step, the silicon carbide layer 12 has an exposed surface 12C, the horizontal height of surface 12C is lower than the horizontal height of surface 12A and higher than the horizontal height of the bottom surfaces of the plurality of grooves (including 41 and 42). In some embodiments, surface 12C may be a horizontal plane. In some embodiments, the top surface of the silicon carbide layer 12 after the dry etching step includes horizontal planes having different horizontal heights. In some embodiments, the top surface of the silicon carbide layer 12 after the dry etching step includes surface 12A and surface 12C, and the horizontal height of surface 12A is higher than the horizontal height of surface 12C. In the dry etching step, a silicon carbide layer 12 of a predetermined thickness is removed, and this predetermined thickness is less than the depth of the groove 41. In the subsequent step, a gate structure is formed on the surface 12C, so the thickness of the gate structure is determined by the thickness of the removed silicon carbide layer 12. Therefore, the predetermined thickness can be adjusted based on the required thickness of the gate structure. In some embodiments, the dry etching step may be a time-mode, where the dry etching step is performed for a predetermined time to control the thickness of the removed silicon carbide layer 12 to reach the predetermined thickness. In some embodiments, the predetermined thickness is between 1000 angstroms and 3000 angstroms. In other words, the vertical distance D12 from the surface 12C of the silicon carbide layer 12 to the top surface 14A of the dielectric layer 14 (including top surfaces 141A and 142A) is between 1000 angstroms and 3000 angstroms. In some embodiments, a portion of the silicon carbide layer 12 covering the dielectric layer 13 partially leaves surface 12A, and the vertical distance between surface 12C and surface 12A (same as D12) is between 1000 angstroms and 3000 angstroms. In some embodiments, the side walls 41C, 42C, and 42D have approximately the same height.In some embodiments, the height of the side wall 41D exceeds the height of the side walls 41C, 42C, or 42D.

[0027] In the subsequent steps, the gate structure is formed on the surface 12C of the silicon carbide layer 12. Therefore, it should be noted that in the silicon carbide layer 12 near the surface 12C between the grooves 41 and 42, a passage is formed during the operation of the semiconductor rectifier element 1, and the doped regions 221 and 222 extend laterally in the silicon carbide layer 12 below the gate structure, which is advantageous for current flow. As shown in Figure 4 above, since the patterned layer 51 is covered, even if oblique ion implantation is performed, the range of the contact surface 12A of the doped regions 221 and 222 is limited. However, after the dry etching process shown in Figure 8, the range of the contact surface 12C of the doped regions 221 and 222 increases, which is advantageous for current flow and improves the efficiency of the semiconductor rectifier element 1. In some embodiments, after the dry etching step, the height of the side wall 41C is lower than the height of the side wall 41D. In some embodiments, after the dry etching step, the corners of the side wall 41C and the surface 12C of the doped region 221 are adjacent. In some embodiments, after the dry etching step, the doped region 221 has a portion of the side wall 41C and surface 12C adjacent to each other. Similarly, the heights of the side walls 42C and 42D of the groove 42 are approximately the same as the height of the side wall 41C. Furthermore, the positional relationship between the doped region 222 and surface 12C is similar to that between the doped region 221 and side wall 41C, so it will not be described again here.

[0028] Referring to Figure 9, the manufacturing method for the semiconductor rectifier element 1 includes forming a dielectric layer 15 on the exposed surface 12C of the silicon carbide layer 12. In some embodiments, the dielectric layer 15 comprises an oxide (e.g., silicon oxide). In some embodiments, the dielectric layer 15 is formed by a step of thermal oxidation of the silicon carbide layer 12. In some embodiments, the thickness of the dielectric layer 15 is between 50 angstroms and 200 angstroms. In some embodiments, the dielectric layer 15 is the gate dielectric layer of a gate structure that is subsequently formed. In some embodiments, the dielectric layer 15 covers the entire surface 12C where the silicon carbide layer 12 is exposed. The dielectric layer 15 comprises multiple portions, each extending between adjacent portions of the dielectric layer 14. For example, the dielectric layer 15 includes a partial dielectric layer 151 and a partial dielectric layer 152. In some embodiments, portions of the dielectric layers 151 and 152 are separated from each other. In some embodiments, the partial dielectric layer 151 extends on the surface 12C between grooves 41 and 42. In some embodiments, the partial dielectric layer 151 is located between and in contact with the partial dielectric layers 141 and 142. In some embodiments, the partial dielectric layer 152 extends onto the surface 12C between the partial dielectric layer 142 and the rest of another adjacent dielectric layer 14 (not shown in the figure).

[0029] Referring to Figure 10, the manufacturing method for the semiconductor rectifier element 1 includes forming a gate electrode layer 16 on a dielectric layer 15. In some embodiments, the gate electrode layer 16 includes polycrystalline silicon. In some embodiments, the gate electrode layer 16 is formed by performing a deposition step to form the gate electrode material, covering the entire silicon carbide layer 12, and then performing an etching step to remove the gate electrode material higher than the top surface 14A of the dielectric layer 14. Similar to the dielectric layer 15, the gate electrode layer 16 also includes multiple parts, each formed on a different part of the dielectric layer 15. For example, the gate electrode layer 16 includes a gate electrode 161 on a partial dielectric layer 151 and a gate electrode 162 adjacent to the gate electrode 161 on a partial dielectric layer 152, with the gate electrodes 161 and 162 separated from each other.

[0030] The gate electrode layer 16 and the dielectric layer 14 have an etching selectivity ratio, and the etching step performed on the gate electrode material stops at the top surface 14A of the dielectric layer 14. Therefore, the top surface 16A of the gate electrode layer 16 and the top surface 14A of the dielectric layer 14 are located at approximately the same horizontal height. In some embodiments, the top surface 16A of the gate electrode layer 16 is flush with or coplanar with the top surface 14A of the dielectric layer 14. In other words, the top surface 161A of the gate electrode 161 is at the same horizontal height as or coplanar with one or more of the top surfaces 141A of the partial dielectric layer 141, the top surface 142A of the partial dielectric layer 142, and the top surface 162A of the gate electrode 162. Furthermore, since the top surface 14A of the dielectric layer 14 is flush with or coplanar with the surface 12A of the silicon carbide layer 12, the top surface 16A of the gate electrode layer 16 is flush with or coplanar with the surface 12A of the silicon carbide layer 12. In other words, one or more of the top surfaces 161A of the gate electrode 161 and the top surfaces 162A of the gate electrode 162 are located at the same horizontal height as the surface 12A of the silicon carbide layer 12.

[0031] Referring to Figure 11, the manufacturing method of the semiconductor rectifier element 1 includes removing the dielectric layer 14. In some embodiments, wet etching is performed to remove the dielectric layer 14 in the grooves 41 and 42. The gate electrode 161 and partial dielectric layer 151 jointly constitute a gate structure 171, and the gate electrode 162 and partial dielectric layer 152 jointly constitute a gate structure 172. In some embodiments, the side walls 41C adjacent to the side wall 41C of the gate structure 171 are in a straight line when viewed in a cross-sectional view, and the side walls 42D adjacent to the side wall 42D of the gate structure 171 are also in a straight line when viewed in a cross-sectional view. The gate structure 172 has a similar arrangement to the gate structure 171, so it will not be described again here.

[0032] Referring to Figure 12, the manufacturing method for the semiconductor rectifier element 1 includes conformally forming a contact metal layer 31 on the silicon carbide layer 12 and the gate structure 17. The contact metal layer 31 may include suitable metallic materials such as titanium (Ti), nickel (Ni), molybdenum (Mo), titanium nitride (TiN), molybdenum nitride (MoN), or combinations thereof. In some embodiments, the contact metal layer 31 is in contact with part of the side walls 41C and bottom surface 41B of the groove 41, and with the side walls 42C, 42D and bottom surface 42B of the groove 42. Furthermore, since the process of forming the contact metal layer 31 or thereafter may involve steps at a temperature of 400-600°C, metal silicides are formed between the contact metal layer 31 and the silicon carbide layer 12, and between the contact metal layer 31 and the gate electrode layer 16. The formation of metal silicides can reduce the electrical resistance between the contact metal layer 31 and the silicon carbide layer 12, or between the contact metal layer 31 and the gate electrode layer 16, thereby improving the performance of the semiconductor rectifier element 1.

[0033] Referring to Figure 13, the manufacturing method for the semiconductor rectifier element 1 includes forming a first electrode layer 32 on a contact metal layer 31. The first electrode layer 32 may include, but is not limited to, suitable metallic materials or alloys such as titanium tungstenide (TiW), aluminum-silicon-copper alloy (AlSiCu), or a combination thereof. After forming the first electrode layer 32, the first electrode layer 32 and the contact metal layer 31 can be etched to electrically connect some gate structures 17 and electrically isolate some gate structures 17. The etching step is performed based on the required circuit design, so the drawings do not depict the etching step, but those skilled in the art can adjust the etching step based on the above-described content of this disclosure to form the required patterns for the first electrode layer 32 and the contact metal layer 31.

[0034] Referring to Figure 14, the manufacturing method for the semiconductor rectifier element 1 includes forming an inactivating layer 33 on a first electrode layer 32 and forming a second electrode layer 34 below the silicon carbide layer 12. In some embodiments, the inactivating layer 33 can be formed via a deposition step and a patterning step. The portion of the inactivating layer 33 that exposes the first electrode layer 32 is used to electrically connect with a conductive plug (not shown in the figure) in a subsequent step of forming a conductive plug. In some embodiments, the second electrode layer 34 has the same conductive material as the first electrode layer 32. The second electrode layer 34 and the first electrode layer 32 are located on opposite sides of the silicon carbide layer 12. In some embodiments, the second electrode layer 34 is formed on the surface 11B of the semiconductor material layer 11. In some embodiments, the second electrode layer 34 is in contact with the semiconductor material layer 11. In some embodiments, the thickness of the semiconductor material layer 11 is reduced by polishing or etching the semiconductor material layer 11 before forming the second electrode layer 34.

[0035] The arrows in Figure 14 indicate the direction of current flow during the operation of the semiconductor rectifier element 1, and it can be understood that the larger the area of ​​the lateral contact surface 12C of the doped region 221, the more it assists the current flow. As explained above, the oblique ion implantation in Figure 4 helps the doped region 22 to extend horizontally along the groove sidewalls (e.g., 41C, 42C, 42D), but the patterned layer 51 limits the extent to which the portion of the doped region 22 that is close to the surface 12A extends horizontally. This problem is precisely solved by the steps in Figure 8. The portion of the doped region 221 at the bottom of the gate structure 171 can provide an effect of extending the doped region (similar to the lightly doped drain extension (LDD) of a transistor), which can increase the operating speed of the semiconductor rectifier element 1.

[0036] Self-aligned gate processes help reduce the use of photomasks, avoiding alignment problems and lowering the overall process cost. However, conventional gate structure self-alignment processes use the gate structure as a mask for ion implantation into the substrate, requiring the annealing step to activate the ions to be performed after the gate structure is formed, making it impossible to apply self-aligned gates to silicon carbide materials. As shown in the steps in Figures 1 to 14, the high-temperature annealing step of this disclosure is performed before the gate structure 17 formation step, thus solving the problem in the prior art where the gate structure is damaged due to excessively high annealing temperatures, and further advancing the application to silicon carbide materials. Both the doped region 22 and the gate structure 17 can be defined by the patterned layer 51, achieving the effects of the conventional self-aligned gate process without requiring a separate photomask. Furthermore, since the doped region 22 is formed by the oblique ion implantation step, this disclosure can achieve the effect of self-aligned extension of the doped region.

[0037] Figures 15 and 16 show top views of semiconductor rectifier elements 2 and 3 based on various embodiments of this invention, illustrating that the gate structure 17 can have various arrangements. It should be noted that the arrangements of the gate structure 17 shown in Figures 15 and 16 are for illustrative purposes only and do not limit this disclosure.

[0038] Referring to Figure 15, in some embodiments, the gate structure 17 comprises multiple groups, and the extension directions of adjacent groups of gate structures 17 are perpendicular to each other. In some embodiments, the doped region 21 is annular and surrounds the entire gate structure 17. In some embodiments, the gate structures 171 and 172 in Figure 14 are connected to each other. In some embodiments, the gate structures 171 and 172 belong to opposite sides of the same gate structure, where these opposite sides are opposite and parallel to each other. In some embodiments, Figures 1-14 are schematic cross-sectional views of multiple stages based on the A-A' tangent in Figure 15. In some embodiments, Figures 1-14 are schematic cross-sectional views of multiple stages based on the B-B' tangent in Figure 15. In some embodiments, the doped region 25 is adjacent to the surface 12A and, when viewed from the top view, surrounds the doped region 221.

[0039] Referring to Figure 16, in some embodiments, the gate structure 17 has multiple adjacent, parallel gate structures 17. In some embodiments, the doped region 21 is annular and surrounds all of the gate structures 17. In some embodiments, the extending direction of the gate structures 17 is parallel to one side of the semiconductor rectifier element 3 and they are connected to each other. In some embodiments, the gate structures 171 and 172 in Figure 14 are connected to each other. In some embodiments, the gate structures 171 and 172 belong to opposite sides of the same gate structure, of which the opposite sides are opposite and parallel to each other. In some embodiments, Figures 1-14 are schematic cross-sectional views of multiple stages based on the C-C' tangent in Figure 16. In some embodiments, the doped region 25 is adjacent to the surface 12A and, when viewed from the top view, surrounds the doped region 221.

[0040] According to the structure and process of the present disclosure described above, identical or similar vertical power semiconductor elements and semiconductor rectifier elements can be realized for the same purpose and concept by making adjustments and substituting the order of steps in the above process. Figures 17-23 show one or more steps in the method for manufacturing a semiconductor rectifier element 4 based on several other embodiments of the present. At least some of these drawings have already been simplified to allow for a better understanding of the embodiments of the present disclosure. For the sake of simplicity, only the parts that differ from the process shown in Figures 1-14 above will be described below, and identical or similar steps will not be repeated.

[0041] Referring to Figures 17 to 18, multiple grooves are formed by the steps described in Figures 1 to 3, but the difference is that in the embodiment of Figure 18, the multiple grooves further include grooves 43 adjacent to groove 42, grooves 43 and groove 41 are located on opposite sides of the groove, and groove 41 is formed within the doped region 21. In some embodiments, the patterned layer 51 further includes openings 513 corresponding to grooves 43. In some embodiments, as seen in the cross-sectional view, the openings 511 are located within the coverage area of ​​the projection along the vertical direction of the doped region 21. In some embodiments, as seen in the cross-sectional view, the side walls 41C, 41D and the bottom surface 41B are adjacent to the grooves 41 of the doped region 21.

[0042] Referring to Figure 19, multiple doped regions 22 are formed based on the steps in Figure 4 described above, but the difference is that in the ion implantation step shown in Figure 19, the groove 41 is formed within the range covered by the doped region 21 of the silicon carbide layer 12, and therefore the doped region 221 overlaps with the doped region 21. In other words, the doped region 21 adjacent to the side walls 41C, 41D and bottom surface 41B of the groove 41 is ion implanted simultaneously in the step of forming the doped region 22. In some embodiments, the doped region 221 is formed within the doped region 21. In some embodiments, the doping concentration of the doped region 221 is higher than that of the doped region 21 or other doped regions 22 (doped regions 222, 223, etc.). After the steps in Figure 19, a carbon-containing layer is formed based on the steps in Figure 5 described above, followed by a high-temperature annealing step, and after the high-temperature annealing step, the carbon-containing layer is removed.

[0043] Referring to Figure 20, the dielectric layer 14 is formed based on the steps in Figure 7 described above, but the difference is that the dielectric layer 14 shown in Figure 20 further includes a partial dielectric layer 143 located within the groove 43, and the opposing side walls and bottom surface of the partial dielectric layer 141 are adjacent to the doped region 221.

[0044] Referring to Figure 21, a portion of the silicon carbide layer 12 adjacent to surface 12A has been removed based on the steps in Figure 8, but the difference is that the silicon carbide layer 12 shown in Figure 20 is not covered by the dielectric layer 13 in Figure 8, and therefore the silicon carbide layer 12 cannot simultaneously have surfaces 12A and 12C located at different horizontal heights. In some embodiments, the etching process is performed on all surfaces 12A where the dielectric layer 14 is exposed. In other words, in some embodiments, the top surface of the silicon carbide layer 12 after the etching step (corresponding to surface 12C) is lower than the top surface 14A of the dielectric layer 14.

[0045] Referring to Figure 22, the dielectric layer 13 is formed based on the steps in Figure 6 described above, but the difference is that the dielectric layer 13 shown in Figure 22 is located on the surface 12C and does not cover the groove 41. In some embodiments, the dielectric layer 13 is separated from the partial dielectric layer 141.

[0046] Referring to Figure 23, the semiconductor rectifier element 4 is formed based on the steps in Figures 9 to 14 described above, but the difference is that the gate structure 17 in Figure 23 further includes gate structures 173 and 174. In some embodiments, the dielectric layer 15 further includes partial dielectric layers 153 and 154, of which the partial dielectric layer 153 is located on a portion of the surface 12C adjacent to the groove 43, on the side of the groove 43 facing the partial dielectric layer 152, and the partial dielectric layer 154 is located on the surface 12C between the groove 41 and the dielectric layer 13. In some embodiments, the gate electrode layer 16 further includes a gate electrode 163 located on the partial dielectric layer 153 and a gate electrode 164 located on the partial dielectric layer 154. In some embodiments, the gate structure 173 includes the partial dielectric layer 153 and the gate electrode 163, and the gate structure 174 includes the partial dielectric layer 154 and the gate electrode 164. The gate structure 174 is adjacent to the dielectric layer 13 and does not contribute to the operation and performance of the semiconductor rectifier element 4, so it is also called a dummy gate.

[0047] Based on the structure and process of the present disclosure described above, identical or similar semiconductor rectifier elements can be realized for the same purpose and concept by making adjustments or substituting the order of the steps in the above process. Figures 24 to 30 show one or more steps in the method of manufacturing a semiconductor rectifier element 5 based on several other embodiments of the present. At least some of these drawings have already been simplified to allow for a better understanding of the embodiments of the present disclosure. For the sake of simplicity, the following description will only focus on parts that differ from the process shown in Figures 17 to 23 above, and will not repeat the same or similar steps.

[0048] Referring to Figure 24, multiple doped regions 22 are formed based on the steps in Figure 18 described above, but the difference is that in the embodiment of Figure 24, ions are vertically implanted into the silicon carbide layer 12 in the ion implantation step. In some embodiments, the ion implantation step includes vertical ion implantation. In some embodiments, the ion implantation step does not include oblique ion implantation. By adjusting the parameters of the ion implantation process, the multiple doped regions 22 that are formed can be made to be separated from the surface 12A or adjacent to the surface 12A. In some embodiments, each doped region 22 (including 221, 222, and 223) is separated from the surface 12A, and the vertical distance D13 between each doped region 22 (including 221, 222, and 223) and the surface 12A is between 1000 and 2000 angstroms. In some embodiments, each doped region 22 (including 221, 222, and 223) is adjacent to the surface 12A (similar to doped regions 221, 222, and 223 in Figure 19).

[0049] Referring to Figure 25, the manufacturing method for the semiconductor rectifier element 5 further includes forming sidewall spacers 54 on the side walls of the openings 511, 512, and 513 of the patterned layer 53. The formation of the sidewall spacers 54 includes, for example, conformally depositing a dielectric material onto the patterned layer 53 and the silicon carbide layer 12, and then performing an etching process on the dielectric material to remove the dielectric material from the horizontal portions.

[0050] Referring to Figure 26, multiple grooves (including 41, 42, and 43) are formed based on the etching steps of Figure 18 (or Figure 3) described above, but the difference is that in the embodiment of Figure 26, etching is performed on the silicon carbide layer 12 using the patterned layer 53 and sidewall spacers 54 as masks. In some embodiments, the widths of the grooves 41, 42, and 43 are less than the widths of the openings 511, 512, and 513, respectively. In some embodiments, the patterned layer 53 and sidewall spacers 54 contain the same dielectric material. In some embodiments, the patterned layer 53 and sidewall spacers 54 can be removed simultaneously (or in a single etching step).

[0051] Referring to Figures 27 to 30, the semiconductor rectifier element 5 is formed based on the steps in Figures 20 to 23 described above. However, the difference is that the doping region 22 formation step in Figure 30 does not include oblique ion implantation, so the arrangement of the doped region 22 of the semiconductor rectifier element 5 may be slightly different from the arrangement of the doped region 22 of the semiconductor rectifier element 4. Furthermore, in some embodiments, the doped region 22 of the semiconductor rectifier element 5 and the surface 12A are separated (as shown in Figure 27), so the predetermined thickness of the etching step in Figure 28 is controlled to be greater than or equal to the distance D13 shown in Figure 24 in order to ensure that multiple doped regions 221, 222, and 223 (especially 222 and 223) are in contact with the surface 12C.

[0052] The semiconductor rectifier elements 4 and 5 formed by the above method have a structure similar to that of semiconductor rectifier element 1, and their advantages over the prior art are the same as those of semiconductor rectifier element 1, so they will not be repeated here. Thanks to the material properties of silicon carbide, the semiconductor rectifier elements provided in this disclosure can reduce power consumption and improve switching efficiency. Furthermore, the manufacturing method provided in this disclosure can effectively align the self-alignment process on the silicon oxide material, avoid damage to the gate structure caused by the high-temperature annealing process, and reduce the overall cost of the process.

[0053] In this text, for ease of description, spatial terms such as “below,” “bottom,” “lower part,” “upper part,” “upper part,” “left side,” and “right side” are used to distinguish one part or feature shown in the drawings from one or more other parts or features. In addition to the directions indicated in the drawings, spatial terms may also cover different directions when the device is in use or operating. The orientation of the device (90-degree rotation, or other orientations) can be determined in other ways, and similarly, spatial terms used in this text can be interpreted in corresponding ways. When it is written that a part is “connected” or “linked” to another part, it should be understood that it may be directly connected or linked to the other part, or there may be an intermediate part.

[0054] As used in this text, the terms “approximately,” “nearly,” “basically,” and “about” are used to describe and interpret small changes. When used in connection with an event or situation, the terms may refer to instances where the event or situation has definitely occurred, and instances where the event or situation is about to occur. When used in this text in relation to a given value or range, the term “about” means that overall it is within ±10%, ±5%, ±1%, or ±0.5% of the given value or range. In this text, a range may be expressed as from one endpoint to another, or between two endpoints. All ranges disclosed in this text include endpoints unless otherwise specified. The term “nearly coplane” may refer to a difference of a few micrometers (μm) between the positions of two surfaces located along the same plane, for example, a difference of 10 μm, 5 μm, 1 μm, or 0.5 μm between the positions located along the same plane. When numerical values ​​or characteristics are considered "approximately" identical, the term may refer to values ​​within ±10%, ±5%, ±1%, or ±0.5% of the mean of the aforementioned values.

[0055] The foregoing outlines the characteristics of some embodiments and the details of this disclosure. The embodiments described herein can readily be used as a basis for designing or modifying other processes and structures to accomplish the same or similar purposes and / or to realize the same or similar advantages of the embodiments described herein. Such equivalent structures can be modified, substituted and altered in various ways, without departing from the spirit and scope of this disclosure. [Explanation of Symbols]

[0056] 1, 2, 3, 4, 5 Semiconductor rectifier elements 11 Semiconductor material layer 11A, 11B surface 12. Silicon Carbide Layer 12A, 12B, 12C surface 12D horizontal plane 13 Dielectric layer 14 Dielectric layer 141, 142, 143 Partial dielectric layers 14A, 141A, 142A Top 15 Dielectric layer 151, 152, 153, 154 Partial dielectric layers 16 Grid control layer 161, 162, 163, 164 gates 16A, 161A, 162A Top 17 Gate structure 171, 172, 173, 174 Gate structure 21 Doping Area 211 areas 22 Doping Area 221, 222, 223 Doping areas 25 Doping Area 31 Contact metal layer 32 1st electrode layer 33 Passivation layer 34 Second electrode layer 41 groove 41B Bottom 41C, 41D side wall 42 grooves 42B Bottom 42C, 42D side walls 43. Grooves 51 Patterned Layers 511, 512, 513 aperture 52 Carbon-containing layer 53 Patterned Layers 54 Side wall spacers D12, D13 distance D41, D42 Depth

Claims

1. In semiconductor rectifier elements, An epitaxial layer having opposing top and bottom surfaces, A first groove comprising a first side wall and a second side wall extending in the direction from the top surface toward the bottom surface and facing each other, and a first bottom surface connecting the first side wall and the second side wall, wherein the first height of the first side wall of the first groove exceeds the second height of the second side wall, A second groove extending in the direction from the top surface toward the bottom surface and adjacent to the first groove, the second groove including a third side wall and a fourth side wall facing each other, and a second bottom surface connecting the third side wall and the fourth side wall, A first doped region extending in the direction from the top surface toward the bottom surface, and adjacent to the second side wall of the first groove and at least a portion of the first bottom surface, A second doped region adjacent to and separated from the first doped region, extending in the direction from the top surface to the bottom surface, and adjacent to the third side wall, the fourth side wall and the second bottom surface of the second groove, The present invention is characterized by comprising: a gate structure installed on the top surface between the first groove and the second groove, with its bottom surface adjacent to the first doped region and the second doped region; and a contact metal layer installed on the top surface of the epitaxial layer along the first groove, the gate structure, and the second groove. Semiconductor rectifier element.

2. The semiconductor rectifier element according to claim 1, wherein the gate structure includes a fifth side wall and a sixth side wall facing each other, the fifth side wall and the second side wall of the first groove are in a straight line when viewed from a cross-sectional view taken from a plane horizontal in the direction from the top surface to the bottom surface, and the sixth side wall of the gate structure and the third side wall of the second groove are in a straight line when viewed from the cross-sectional view.

3. The semiconductor rectifier element according to claim 1, wherein the first side wall of the first groove is connected to the first portion of the top surface, and the portion of the top surface between the first groove and the second groove is the second portion of the top surface, and the first portion and the second portion are located at substantially the same horizontal height.

4. The semiconductor rectifier element according to claim 1, wherein the first side wall of the first groove is connected to the first portion of the top surface, the portion of the top surface between the first groove and the second groove is the second portion of the top surface, and the horizontal height of the first portion exceeds the horizontal height of the second portion.

5. It further includes a third doping region that extends in the direction from the top surface toward the bottom surface, overlaps with at least a portion of the first doping region, and whose depth exceeds the depth of the first doping region. The semiconductor rectifier element according to claim 1.

6. The semiconductor rectifier element according to claim 5, wherein the portion of the third doped region close to the first doped region has a high doping concentration.

7. The semiconductor rectifier element according to claim 1, wherein the contact metal layer is in contact with the second side wall of the first groove, the bottom surface of the first groove, the third and fourth side walls of the second groove, and the bottom surface of the second groove.

8. The semiconductor rectifier element according to claim 1, wherein the first doped region is further adjacent to the first side wall of the first groove.

9. The semiconductor rectifier element according to claim 1, wherein the third height of the third side wall of the second groove is the same as the fourth height of the fourth side wall, and the second height, third height, and fourth height are the same.

10. In a method for manufacturing semiconductor rectifier elements, Forming a patterned layer on a silicon carbide layer having opposing top and bottom surfaces, The silicon carbide layer is etched using the patterned layer as a mask to form a first groove and a second groove adjacent to the first groove. Ion implantation is performed on the silicon carbide layer using the patterned layer as a mask. The silicon carbide layer is subjected to thermal annealing, The method includes forming a gate structure on the silicon carbide layer between the first groove and the second groove after the thermal annealing, wherein the gate structure has a first side wall and a second side wall facing each other, the first side wall and one side wall of the first groove are continuous side walls, and the second side wall and one side wall of the second groove are also continuous side walls. A method for manufacturing semiconductor rectifier elements.

11. Prior to the aforementioned thermal annealing, a carbon-containing layer is formed to cover the silicon carbide layer, The process further includes removing the carbon-containing layer after the thermal annealing. The manufacturing method according to claim 10.

12. A first dielectric layer for filling the first groove and the second groove, wherein the top surface of the first dielectric layer is flush with the top surface of the silicon carbide layer, The method involves removing a portion of the silicon carbide layer adjacent to the top surface of the exposed silicon carbide layer to form a first surface lower than the top surface of the silicon carbide layer, wherein the first surface is higher than the bottom surface of the first groove, and the first surface is spaced perpendicularly from the top surface of the silicon carbide layer. The further includes forming the gate structure on the first surface, The manufacturing method according to claim 10.

13. Forming a gate structure on the first surface is Forming a second dielectric layer on the first surface, This includes forming a gate electrode layer on the second dielectric layer, the gate electrode layer having a top surface flush with the top surface of the first dielectric layer. The manufacturing method according to claim 12.

14. The manufacturing method according to claim 12, wherein the vertical distance between the first surface and the top surface of the silicon carbide layer is between 1500 and 2000 angstroms.

15. The further step includes forming a terminal doped region within the silicon carbide layer before forming the patterned layer. The manufacturing method according to claim 10.

16. The manufacturing method according to claim 15, wherein the patterned layer exposes a portion of the terminal doping region, and the terminal doping region is adjacent to the first groove.

17. The manufacturing method according to claim 15, wherein the patterned layer includes an opening defining the first groove, and when viewed from a cross-sectional view taken from a plane horizontal in the direction from the top surface to the bottom surface, the opening overlaps with a part of the terminal doped region in the vertical direction.

18. The manufacturing method according to claim 15, wherein the patterned layer includes an opening defining the first groove, and when viewed from a cross-sectional view taken from a plane horizontal in the direction from the top surface to the bottom surface, the opening is located within the coverage area of ​​the projection along the vertical direction of the terminal doped region.

19. The process further includes forming a third dielectric layer to cover the terminal doped region and a portion of the first groove adjacent to the terminal doped region, before forming the gate structure on the silicon carbide layer between the first groove and the second groove. The manufacturing method according to claim 15.

20. A contact metal layer is conformally formed on the silicon carbide layer and the gate structure, in which contact is made with the side walls and bottom surface of the first groove, and also with the side walls and bottom surface of the second groove. Forming a first electrode layer on the aforementioned contact metal layer, The invention further includes forming a second electrode layer below the silicon carbide layer, wherein the first electrode layer and the second electrode layer are located on opposite sides of the silicon carbide layer. The manufacturing method according to claim 10.

21. To provide a substrate, The silicon carbide layer is formed by performing epitaxial growth on the substrate, To reduce the thickness of the aforementioned substrate, The further includes forming the second electrode layer that contacts the substrate, The manufacturing method according to claim 20.

22. The manufacturing method according to claim 10, wherein the depth of the first groove or the second groove is between 4,000 and 5,000 angstroms.

23. The manufacturing method according to claim 10, wherein the ion implantation includes oblique ion implantation.

24. The process further includes forming sidewall spacers on multiple sidewalls of the patterned layer after the ion implantation. The manufacturing method according to claim 10.

25. The manufacturing method according to claim 24, wherein the formation of the first groove and the second groove is performed on the silicon carbide layer using the patterned layer and the side wall spacer as a mask.

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