Semiconductor device

Abstract

This semiconductor device includes: a laminated structure that is obtained by laminating a first metal electrode layer on a p-type semiconductor layer comprising p-type Si, and that exhibits rectification properties; and / or a laminated structure that is obtained by laminating a second metal electrode layer on an n-type semiconductor layer comprising n-type Si, and that exhibits ohmic properties. A layered compound layer comprising a layered compound of Sb and / or Bi and Te is interposed between the p-type Si semiconductor layer and the first metal electrode layer and / or between the n-type semiconductor layer and the second metal electrode layer.

Description

Semiconductor Devices

[0001] The present invention relates to a semiconductor device including a stacked structure in which a metal electrode layer is stacked on a semiconductor layer made of Si. This application claims priority to Japanese Patent Application No. 2023-125852, filed on August 1, 2023, the contents of which are incorporated herein by reference.

[0002] When a semiconductor layer made of Si is brought into contact with a metal layer, it may form a "diode junction (Schottky junction)" that exhibits rectification, or it may form an "ohmic junction" that does not exhibit such rectification. This difference depends on the magnitude of the energy barrier between the Si semiconductor layer and the metal layer, and on whether the Si semiconductor layer is made of a p-type or n-type semiconductor, as well as the type of metal to be combined.

[0003] For example, Patent Document 1 discloses a semiconductor device including a merged pin Schottky (MPS) structure in which Schottky diodes and pn-type diodes are alternately arranged on one surface of a semiconductor element, and a Schottky junction is provided in the n-type semiconductor region and an ohmic junction is provided in the p-type semiconductor region. This document discusses the use of SiC as a semiconductor substrate, and the fact that the interface is unstable when a NiAl alloy is Schottky-junctioned onto the n-type semiconductor region. It also discusses the need to form the Schottky junction layer in the n-type semiconductor region and the ohmic junction layer in the p-type semiconductor region using different materials. Specifically, the document describes the use of an alloy containing aluminum and titanium for the ohmic junction layer, and the use of a metal containing molybdenum as the main component for the Schottky junction layer.

[0004] JP 2010-50267 A

[0005] When a semiconductor layer made of Si is brought into contact with a metal layer, whether the contact is rectifying or ohmic, operational stability cannot be obtained unless the contact interface is stable. As described above, it has been confirmed that even when a high-melting-point metal such as molybdenum is used, the contact interface becomes wavy and sufficient operational stability cannot be obtained.

[0006] The present invention has been made in consideration of the above-mentioned circumstances, and aims to provide a semiconductor device having a stacked structure in which a metal electrode layer is stacked on a semiconductor layer containing Si, and having high operational stability.

[0007] The inventors of the present application have noticed that, for example, even W, which is a high-melting-point metal, does not form a sufficiently flat interface when bonded to Si, resulting in a lack of operational stability in the semiconductor device, such as rectification and ohmic properties.

[0008] That is, the semiconductor device according to the present invention is a semiconductor device including a stacked structure exhibiting rectifying properties in which a first metal electrode layer is stacked on a p-type semiconductor layer containing p-type Si, and / or a stacked structure exhibiting ohmic properties in which a second metal electrode layer is stacked on an n-type semiconductor layer containing n-type Si, and is characterized in that a layered compound layer made of a layered compound of Sb and / or Bi with Te is interposed between the p-type Si semiconductor layer and the first metal electrode layer and / or between the n-type semiconductor layer and the second metal electrode layer.

[0009] According to this feature, a semiconductor device with high operational stability can be obtained by interposing a layered compound layer that exhibits rectification and ohmic properties between the semiconductor layer and has high interface smoothness.

[0010] In the above-described invention, the layered compound layer may contain an amorphous phase. With this feature, good interface smoothness can be obtained, and a semiconductor device with high operational stability can be obtained.

[0011] In the above invention, the layered compound layer may have a thickness of 1 to 10 nm. With this feature, a semiconductor device with high operational stability can be obtained regardless of the metal type of the metal electrode layer.

[0012] In the above-mentioned invention, the layered compound is (Sb ｘ Bi １－ｘ ) ２ Te ３ (where 0<x<1). With this feature, a semiconductor device can be obtained that exhibits good rectification and ohmic properties, and also provides good interface smoothness, resulting in a highly stable operation.

[0013] The p-type Si may be characterized by containing Si and Ge, and the n-type Si may be characterized by containing Si and C. With these characteristics, a semiconductor device can be obtained that exhibits good rectification and ohmic properties and has high operational stability.

[0014] 1 is a diagram showing a stacked structure in which a metal electrode layer is superimposed on a semiconductor layer according to one embodiment of the present invention; FIG. 2 is a band diagram when a metal electrode layer is connected to an n-type Si semiconductor; FIG. 3 is a band diagram when a layered compound layer is connected to an n-type Si semiconductor; FIG. 4 is a cross-sectional STEM (scanning transmission electron microscope) image of the vicinity of the connection interface when a metal electrode layer is connected to a semiconductor layer; FIG. 5 is a cross-sectional STEM image of the vicinity of the connection interface when a layered compound layer is connected to a semiconductor layer; FIG. 6 is a cross-sectional view showing the junction between a semiconductor layer and a layered compound layer according to the present invention; FIG. 7 is a cross-sectional view showing the junction between a Si semiconductor and an Sb ２ Te ３ and Bi ２ Te ３ 1 is a band diagram of n-type Si. 2 is a diagram showing the potential barrier height with respect to n-type Si. 3 is a graph showing the heat treatment temperature and the potential barrier height of a layered compound layer bonded to a p-type Si semiconductor (resistivity: 5 Ωcm). 4 is a diagram showing the junction structure of an n-type Si semiconductor (resistivity: 5 Ωcm) and a metal (W), and ２ Te ３ 1 is a graph showing the relationship between the applied voltage and the current for each of the junction structures formed. ２ Te ３FIG. 1 is a graph showing the relationship between applied voltage and current for each of the junction structures formed with a junction structure. FIG. 2 is a cross-sectional view showing a manufacturing process for a top-gate transistor according to an embodiment of the present invention. FIG. 3 is a cross-sectional view showing a manufacturing process for a top-gate transistor according to an embodiment of the present invention. FIG. 4 is a cross-sectional view showing a manufacturing process for a top-gate transistor according to an embodiment of the present invention. FIG. 5 is a cross-sectional view showing a manufacturing process for a top-gate transistor according to an embodiment of the present invention. FIG. 6 is a cross-sectional view showing a manufacturing process for a top-gate transistor according to an embodiment of the present invention. FIG. 7 is a cross-sectional view showing a manufacturing process for a top-gate transistor according to an embodiment of the present invention. FIG. 8 is a cross-sectional view showing a manufacturing process for a top-gate transistor according to an embodiment of the present invention. FIG. 9 is a cross-sectional view showing a manufacturing process for a top-gate transistor according to an embodiment of the present invention. FIG. 10 is a cross-sectional view showing a manufacturing process for a top-gate transistor according to an embodiment of the present invention.

[0015] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

[0016] First, a method for manufacturing a semiconductor device and the semiconductor device obtained will be described with reference to FIG.

[0017] As shown in FIG. 1 , first, a layered compound layer 4 made of an amorphous film containing Sb and / or Bi and Te is formed on a semiconductor layer 2 formed on an underlayer (insulating film) 5. The semiconductor layer 2 is made of a Si semiconductor. The Si semiconductor is selected from either a p-type semiconductor made of p-type Si (containing p-type Si as a main component) or an n-type semiconductor made of n-type Si (containing n-type Si as a main component). The semiconductor layer 2 may also be made of a Si semiconductor containing C or Ge. For example, a p-type semiconductor may contain Ge together with p-type Si, and an n-type semiconductor may contain C together with n-type Si. Then, a metal electrode layer 3 is provided on the layered compound layer 4. As a result, the layered compound layer 4 made of a layered compound containing Sb and / or Bi and Te is interposed between the semiconductor layer 2 and the metal electrode layer 3.

[0018] The material of the metal electrode layer 3 is not particularly limited, and for example, tungsten (W), cobalt (Co), ruthenium (Ru), etc. can be used.

[0019] The material of the layered compound layer 4 is Sb ｘ Te １－ｘ , Bi ｘ Te １－ｘ , (Sb ｘ Bi １－ｘ ) ２ Te ３ where 0<x<1.

[0020] Next, the amorphous film of the layered compound layer 4 is crystallized by heat treatment. The amorphous film is crystallized by heat treatment at an appropriate temperature to become a layered compound with a crystalline phase. As will be described later, the layered compound layer 4 may contain an amorphous phase and may not be subjected to heat treatment. Alternatively, a crystallized layered compound layer 4 can be obtained by forming the layered compound layer 4 on the semiconductor layer 2 while performing heat treatment.

[0021] The semiconductor device 1 thus obtained includes a laminated structure of a metal electrode layer / semiconductor layer, and can change the height of the potential barrier between the metal electrode layer 3 and the semiconductor layer 2 compared to when the metal electrode layer 3 and the semiconductor layer 2 are directly bonded together. This can reduce the contact resistance between the metal electrode layer 3 and the semiconductor layer 2, or improve the on / off ratio of the diode current, for example.

[0022] FIG. 2A is a band diagram when a metal electrode layer 3 is directly bonded to an n-type Si semiconductor layer 2. FIG. 2B is a band diagram when a layered compound layer is bonded to an n-type Si semiconductor. Referring to FIG. 2A , generally, when an n-type Si semiconductor (n-Si) as the semiconductor layer 2 is bonded to a metal electrode layer 3 (W), a diode junction with a high potential barrier height (BH) is formed due to the difference between the work function of the metal and the work function of the semiconductor layer and Fermi level pinning caused by metal-induced gap states (MIGS). Therefore, bonding a metal electrode layer 3 to a semiconductor layer 2 made of an n-type Si semiconductor increases contact resistance.

[0023] In contrast, as shown in FIG. 2B, according to the structure of the semiconductor device 1 of this embodiment, the semiconductor layer 2 contains Sb. ２ Te ３ When the layered compound layer 4 made of the above is joined, the pinning position of the Fermi level changes, and the potential barrier height (BH) can be lowered. This reduces the contact resistance compared to when a metal electrode layer is directly joined to the semiconductor layer, and makes it possible to form an ohmic junction that exhibits ohmic properties.

[0024] Furthermore, as shown in FIG. 3A, it is generally difficult to obtain a flat bonded interface when bonding a semiconductor layer 2 and a metal electrode layer 3. On the other hand, as shown in FIG. 3B, in the stacked structure of this embodiment, a bonded interface that is flat at the atomic level can be obtained between the semiconductor layer 2 and the layered compound layer 4. The lower limit of the thickness of the layered compound layer 4 is approximately 1 nm, which is the thickness of one layer, the smallest unit of the layered compound. In addition, the layered compound layer 4 is preferably 10 nm or less in thickness so as not to excessively increase the resistance. This upper limit of the thickness is based on the fact that the resistivity in the vertical direction of the layered compound layer 4 is approximately 0.01 Ωcm. For example, if the specific contact resistivity is 10 －８ Ω cm ２ In order to obtain the following, the film thickness can be calculated to be 10 nm or less, assuming that the resistivity in the vertical direction × the film thickness = the specific contact resistivity. In other words, the thickness of the layered compound layer 4 is preferably in the range of 1 to 10 nm.

[0025] 4, by obtaining such an atomically flat bonding surface, it is possible to form an ideal defect-free interface as a bonding surface between the semiconductor layer 2 (Si semiconductor) and the layered compound layer 4 (Te-based layered material), thereby obtaining a semiconductor device with high operational stability.

[0026] Furthermore, as shown in FIG. 5, Si used in the semiconductor layer 2 has the highest electron density in the valence band, E Ｖ , the lowest E of the conduction band Ｃ According to the example in the figure, n-type Si has a band gap between the lowest conduction band E Ｃ The layered compound layer 4 having a work function close to that of Sb is advantageous for reducing the resistance. ２ Te ３ For p-type Si, the highest electron in the valence band, E Ｖ The layered compound layer 4 having a work function close to that of Bi is advantageous for reducing the resistance. ２ Te ３ In this way, the layered compound made of Sb and / or Bi and Te used in the layered compound layer 4 has a characteristic band alignment with respect to a Si semiconductor.

[0027] In particular, (Bi ｘ Sb １－ｘ ) ２ Te ３ In the layered compound, when the composition ratio is changed by changing the value of x within the range of 0 to 1, the work function of the layered compound is ２ Te ３ and the work function of Bi ２ Te ３ That is, the work function of (Bi ｘ Sb １－ｘ ) ２ Te ３ The work function of Si varies depending on the composition ratio of the value of x. Ｃ The uppermost electron in the valence band of Si, E Ｖ Therefore, the electron barrier height due to the contact between the semiconductor layer 2 and the metal electrode layer 3 is not simply changed, but can also be adjusted in accordance with the change in the work function.

[0028] As shown in FIG. 6, the potential barrier height for n-type Si is E ｃ Except for rare earth elements such as lanthanides, no material that approaches the conduction band edge has been found so far. However, the layered compound of Sb and Te used in the layered compound layer 4 of this embodiment has a potential barrier height with Si that is comparable to that of rare earth elements. ｃ As a result, the layered compound layer 4 made of an SbTe-based compound can reduce the contact resistance between the semiconductor layer 2 made of n-type Si and the metal electrode layer 3.

[0029] As shown in FIG. 7, when a metal layer (W) is directly bonded to a semiconductor layer 2 made of a p-type Si semiconductor with a resistivity of 5 Ωcm (W / Si), the Sb ２ Te ３It was found that the potential barrier height (BH) increases when a metal layer (W) is bonded via a layered compound layer formed by the method described above. It was also confirmed that the potential barrier height of the layered compound layer remains almost unchanged when it is as-deposited as an amorphous film and when it is annealed at four different annealing temperatures (100, 200, 300, and 400°C). In other words, it was found that the potential barrier height can be obtained in the amorphous phase as well as in the crystalline phase.

[0030] As shown in FIG. 8, compared to a conventional Schottky barrier diode with a metal junction using an n-type Si semiconductor with a resistivity of 5 Ωcm, the Sb ２ Te ３ In the stacked structure of this embodiment using the above, the current increases when a reverse voltage is applied. There is almost no difference in the current when a forward voltage is applied. In this way, compared to conventional metal junctions, a low on / off ratio can be obtained. In other words, a stacked structure with an ohmic junction having low contact resistance can be obtained.

[0031] On the other hand, as shown in FIG. 9, compared to the conventional Schottky barrier diode with a metal junction using a p-type Si semiconductor with a resistivity of 5 Ωcm, the layered compound layer has an Sb ２ Te ３ In the stacked structure of this embodiment using the above, the current is small when a reverse voltage is applied. There is almost no difference in the current when a forward voltage is applied. In this way, compared to conventional metal junctions, a high on / off ratio characteristic can be obtained. In other words, a stacked structure with a diode junction that has excellent rectification and little leakage current can be obtained.

[0032] That is, compared to the conventional junction between a semiconductor layer and a metal electrode layer, it can be expressed as follows: When an SbTe-based thin film is used for the layered compound layer, the contact resistance can be reduced by using an n-type Si semiconductor for the semiconductor layer, and the current on / off ratio can be increased by using a p-type Si semiconductor for the semiconductor layer.

[0033] 5 again, the following is also clear when compared with a conventional junction between a semiconductor layer and a metal electrode layer: When a BiTe-based thin film is used as the layered compound layer, the contact resistance can be reduced by using a p-type Si semiconductor for the semiconductor layer, and the current on / off ratio can be increased by using an n-type Si semiconductor for the semiconductor layer.

[0034] As described above, according to these embodiments, the height of the potential barrier caused by contact between the semiconductor layer and the metal electrode layer can be changed.

[0035] Next, an example of manufacturing a transistor as the semiconductor device 1 will be described.

[0036] 10A to 10D, 11A to 11C, 12A to 12C, 13A, and 13B show manufacturing steps for a top-gate field effect transistor (FET) as an example of a semiconductor device to which the above-described stacked structure is applied.

[0037] As shown in Fig. 10A, first, an underlayer 5 and a semiconductor layer 7 are formed in this order on a semiconductor substrate 6 by atomic layer deposition (ALD). Next, as shown in Fig. 10B, an insulating film 8 is formed on the semiconductor layer 7 by atomic layer deposition. Si is used as the material for the semiconductor layer 7. Furthermore, as shown in Fig. 10C, a gate electrode layer (metal electrode layer) 9 is formed on the insulating film 8. Then, as shown in Fig. 10D, a gate region is patterned in the gate electrode layer 9 by lithography, and portions other than the gate electrode are removed by dry etching to form the gate electrode.

[0038] 11A, the portion of the insulating film 8 where the layered compound layer 4 is to be formed is etched. Next, as shown in Fig. 11B, the layered compound layer 4, which is an amorphous film made of Sb and / or Bi and Te, is deposited to a thickness of 10 nm or less by, for example, sputtering on the exposed portion of the semiconductor layer 7. Then, as shown in Fig. 11C, the layered compound layer 4 other than the source / drain regions is removed by lithography and dry etching.

[0039] The semiconductor substrate 6 is made of a Si semiconductor.

[0040] The insulating film 8 is made of any material, for example, SiO ２ , Al ２ O ３ , HfO ２ , ZrO ２ , Y ２ O ３ , La ２ O ３ An oxide film such as the above can be used.

[0041] The material of the gate electrode layer 9 is not particularly limited, and for example, tungsten (W), titanium (Ti), nickel (Ni), aluminum (Al), platinum (Pt), gold (Au), titanium nitride (TiN), tantalum nitride (TaN), or an alloy or stacked film containing two or more of these may be used.

[0042] Then, as shown in Fig. 12A, the amorphous film of the layered compound layer 4 is crystallized by heat treatment at an appropriate temperature to form a layered compound in a crystalline phase. That is, the layered compound layer 4, which was an amorphous film, is crystallized by heat treatment at an appropriate temperature to change into the layered compound layer 4 made of a layered compound in a crystalline phase. Thereafter, as shown in Fig. 12B, an interlayer insulating film 10 is formed on the entire surface of the top layer at this stage. Next, as shown in Fig. 12C, etching is performed to form a contact hole 10', exposing a portion of the layered compound layer 4.

[0043] 13A, a metal electrode layer 3 that will become a plug electrode is formed, and as shown in FIG. 13B, a plug electrode is formed from the metal electrode layer 3 by lithography and dry etching. This makes it possible to obtain a FET as a semiconductor device in which the layered compound layer 4 is interposed between the metal electrode layer 3 and the semiconductor layer 7 (semiconductor substrate 6) made of a Si semiconductor. This makes it possible to obtain a top-gate field-effect transistor with reduced contact resistance. The temperature for the heat treatment is preferably set, for example, within the range of 100°C or higher.

[0044] In this way, by interposing the layered compound layer 4 between the semiconductor layer 7 made of a Si semiconductor and the metal electrode layer 3, the contact resistance between the semiconductor layer 7 and the metal electrode layer 3 can be reduced.

[0045] The above-described stacked structure can be applied to semiconductor devices such as any electronic device or optical device that has a junction between a metal electrode layer and a semiconductor layer made of a Si semiconductor, such as a transistor, a Schottky diode, a light-emitting diode, a solar cell, or a thermoelectric conversion element.

[0046] Although the embodiments of the present invention and modifications based thereon have been described above, the present invention is not necessarily limited to these examples. Furthermore, those skilled in the art will be able to find various alternative embodiments and modifications without departing from the spirit of the present invention or the scope of the appended claims.

[0047] REFERENCE SIGNS LIST 1 semiconductor device 2 semiconductor layer 3 metal electrode layer (plug) 4 layered compound layer 5 underlayer 6 semiconductor substrate 7 semiconductor layer 8 insulating film 9 gate electrode layer 10 interlayer insulating film

Claims

1. A semiconductor device including a laminated structure exhibiting rectification properties in which a first metal electrode layer is laminated on a p-type semiconductor layer made of p-type Si, and / or a laminated structure exhibiting ohmic properties in which a second metal electrode layer is laminated on an n-type semiconductor layer made of n-type Si, wherein a layered compound layer made of a layered compound of Sb and / or Bi and Te is interposed between the p-type semiconductor layer and the first metal electrode layer, and / or between the n-type semiconductor layer and the second metal electrode layer.

2. A semiconductor device according to claim 1, wherein said layered compound layer contains an amorphous phase.

3. The semiconductor device according to claim 1 or 2, wherein the layered compound layer has a thickness of 1 to 10 nm.

4. The layered compound is (Sb ｘ Bi １－ｘ ) ２ Te ３ 3. The semiconductor device according to claim 1, wherein x is an integer of 0 to 1, and 0<x<1.

5. A semiconductor device according to claim 4, wherein said p-type Si contains Ge.

6. A semiconductor device according to claim 4, wherein said n-type Si contains C.

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