Back contact solar cell with multiple tunnel junction structures and preparation method thereof

Abstract

This invention relates to a back-contact solar cell with multiple tunnel junction structures and its fabrication method. The solar cell includes an N-type crystalline silicon substrate, whose front surface comprises a lightly doped n+ surface field and a passivation antireflection film, and whose back surface comprises a P-type emitter region, an N-type back surface field region, and a groove structure; the P-type emitter region is located within the groove structure, and the N-type back surface field region is located on top of the groove structure; the N-type back surface field region comprises, from the inside out, tunneled SiO2. X Layer, n+poly layer, oxide layer, n+poly layer, tunneling SiO X Layers, and p+poly layers; SiO X The layer forms c-Si / SiO with the n+poly layer. X The oxide layer and the n+poly layer form an n+poly / Oxide / n+poly tunnel junction, tunneling through SiO₂. X The layer forms an n+poly / SiO with the p+poly layer. X / p+poly tunnel junction; the P-type emitter region, from the inside out, consists of a tunneling SiOx layer and a p+poly layer, SiO... X The layer forms c-Si / SiO with the p+poly layer. X / p+poly tunnel junction; the P-type emitter region is provided with a P-type metal electrode, and the N-type back surface field region is provided with an N-type metal electrode.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, and in particular to a back-contact solar cell with multiple tunnel junction structures and a preparation method thereof. Background Art

[0002] In crystalline silicon solar cells, the efficiency loss of the cell can be divided into two aspects: electrical loss and optical loss. The important components of electrical loss are the recombination loss and resistance loss caused by metal-semiconductor contact, while the important component of optical loss is the shading of the metal grid lines on the light-receiving surface.

[0003] In currently commercialized crystalline silicon solar cells, such as p-type aluminum back field cells, p-type PERC cells or n-type PERT cells, the metal shielding area of ​​the light-receiving surface is about 5% to 5%. Under the condition of ensuring low contact resistivity, the dark saturation current density (J0,metal) of the n+ emission and metal contact area on the front surface of the p-PERC cell is 800 to 1000 fA / cm 2 For n-type cells, the recombination loss is higher, and the dark saturation current density (J0,metal) in the p+ emitter-metal contact region is 1000-2000fA / cm 2 In order to further improve the efficiency of crystalline silicon solar cells, it is particularly important to reduce the following three losses: 1) optical loss caused by metal shading on the light surface, 2) recombination loss of metal-semiconductor contact, and 3) resistance loss of metal-semiconductor contact.

[0004] Research has found that the tunnel oxide passivation metal contact structure has significant electrical properties and can simultaneously achieve low contact resistivity and low surface recombination. This structure consists of an ultra-thin tunnel oxide layer and a doped polysilicon layer. Since the absorption of light by the doped polysilicon layer is "parasitic", that is, it does not contribute to the photocurrent, the tunnel oxide passivation metal contact structure is mostly used on the back of the battery. In 2017, Feldmann et al. of the Fraunhofer Institute for Solar Energy Systems in Germany increased the conversion efficiency of solar cells with tunnel oxide passivation metal contact structures to 25.8%, and the grid lines on the front surface of the battery caused an efficiency loss of ~0.2%. In 2018, the German ISFH Solar Energy Research Institute introduced the tunnel oxide passivation metal contact structure into the back contact (IBC) battery. The front surface of the battery was not blocked by the metal electrode, and a conversion efficiency of 26.1% was achieved.

[0005] Conventional crystalline silicon back contact (IBC) cells: 1) require a multi-step mask process; 2) require precise control of the spacing between the back emitter region and the back field region to prevent leakage; 3) require precise alignment of metallization technology to isolate the P region electrode from the N region electrode; the above reasons lead to many challenges in the large-scale industrialization of IBC cells, such as: more processes, complex processes, low production capacity, and high costs. Introducing the tunneling oxide passivation metal contact structure into IBC cells and preparing IBC cells (POLO-IBC) with both the emitter and the back surface field (BSF) as passivation contact structures has undoubtedly further increased the difficulty of the process. The POLO-IBC cell with an efficiency of 26.1% at the German ISFH Solar Energy Research Institute uses photoresist mask technology to complete the doping of the back emitter and BSF regions. The intrinsic region between the emitter and BSF is also implemented using a photoresist mask to prevent battery leakage. The metallization method of the battery is physical vapor deposition (PVD). First, the passivation film on the emitter and BSF is locally removed by laser film opening, and a 10μm thick metal aluminum is thermally evaporated as an electrode, and then a layer of SiO X Using the laser as a mask, the film is opened again to remove the metal aluminum electrode in the specific area, isolating the metal electrodes above the P area and the N area, and finally completing the metallization of the battery.

[0006] In addition, the most commonly used metallization method in the industrialization of crystalline silicon solar cells is screen printing and sintering. Unlike mild metallization methods such as PVD, the screen printing and sintering process will cause the metal to penetrate the oxide layer / doped polysilicon and directly contact the silicon substrate, resulting in a surge in recombination under the metal area and poor contact. For silver aluminum paste, the phenomenon of metal penetrating the oxide layer / doped polysilicon will be more serious.

[0007] Processes such as photoresist masks and PVD deposition of metal electrodes are laboratory technologies and are not suitable for large-scale mass production. In order to improve the conversion efficiency of solar cells, it is of great significance to combine the excellent optical properties of the IBC structure with the excellent electrical properties of the passivation contact structure to prepare passivation contact IBC cells with fewer mask processes, low battery leakage, and suitable for large-scale mass production. Summary of the invention

[0008] The object of the present invention is to overcome the deficiencies of the prior art and provide a back-contact solar cell with multiple tunnel junction structures.

[0009] The technical solution of a back-contact solar cell with multiple tunnel junction structures of the present invention is as follows:

[0010] (1) A tunneling oxide layer is grown on the back surface of the N-type crystalline silicon substrate, and an intrinsic polysilicon layer is deposited on the tunneling oxide layer to form a c-Si / SiO X / i-poly tunnel junction; depositing an oxide layer on the intrinsic polysilicon layer, and depositing an intrinsic polysilicon layer on the oxide layer to form an i-poly / Oxide / i-poly tunnel junction;

[0011] (2) depositing a mask on the n+ doped region of the front surface, doping the intrinsic polysilicon layer with phosphorus, activating or advancing phosphorus atoms at high temperature, so that the intrinsic polysilicon layer is transformed into a phosphorus-doped polysilicon layer to form a c-Si / SiO X / n+poly tunnel junction and n+poly / Oxide / n+poly tunnel junction, and at the same time forming a phosphorus-containing silicon oxide layer on the outer phosphorus-doped polysilicon layer;

[0012] (3) Remove the local phosphorus-containing silicon oxide layer on the back of the N-type crystalline silicon substrate, c-Si / SiO X / n+poly tunnel junction, and n+poly / Oxide / n+poly tunnel junction;

[0013] (4) placing the N-type crystalline silicon substrate in an alkaline solution for isotropic etching, wherein during the etching process, the area on the N-type crystalline silicon substrate covered by the phosphorus-containing silicon oxide layer is not etched, and the area not covered by the phosphorus-containing silicon oxide layer is etched by the alkaline solution into a sunken groove structure;

[0014] (5) placing the N-type crystalline silicon substrate in an acid solution to remove the mask of the n+ doped region on the front surface of the N-type crystalline silicon substrate and the phosphorus-containing silicon oxide layer on the back surface;

[0015] (6) growing a tunneling oxide layer on the back side of the N-type crystalline silicon substrate, and depositing an in-situ boron-doped polysilicon layer on the tunneling oxide layer to form an n+poly / SiO X / p+poly tunnel junction, forming a c-Si / SiO at the bottom of the groove structure X / p+poly tunnel junction; and performing annealing to transform the in-situ boron-doped polysilicon layer into a boron-doped polysilicon layer.

[0016] The present invention provides a method for preparing a back-contact solar cell having multiple tunnel junction structures, which also includes the following subsidiary technical solutions:

[0017] Before step (1), the method further comprises:

[0018] (1) Selecting an N-type crystalline silicon substrate, cleaning the surface of the N-type crystalline silicon substrate, and making a velvet surface;

[0019] (2) Phosphorus diffusion is performed on the textured surface of the N-type crystalline silicon substrate to form a double-sided n+ doped region;

[0020] (3)', etching the back surface of the N-type crystalline silicon substrate, and performing a polishing process to remove the n+ doped region on the back surface of the N-type crystalline silicon substrate.

[0021] The method further comprises:

[0022] (7) depositing a passivation film on the back side of the N-type crystalline silicon substrate after the treatment in step (6), and depositing an anti-reflection film on the front side of the N-type crystalline silicon substrate;

[0023] (8) A metal gate line having an interdigitated structure is formed on the N-type back surface field region and the P-type emitter region on the back side of the N-type crystalline silicon substrate.

[0024] Wherein, the groove structure is an arc-shaped groove structure, the maximum width of which is 0.9-1.8 mm and the depth of which is 3-10 μm.

[0025] Wherein, the c-Si / SiO X / n+poly tunnel junction, and c-Si / SiO X SiO in p+poly tunnel junction X A tunneling oxide layer having a thickness of 0.5-3.5 nm and grown by thermal oxidation, HNO3 oxidation, O3 oxidation, or atomic layer deposition;

[0026] The Oxide in the n+poly / Oxide / n+poly tunnel junction is an oxide layer with a thickness of 2.0-15 nm, and is grown by PECVD or atomic layer deposition.

[0027] Wherein, the oxide layer includes silicon oxide, aluminum oxide, or titanium dioxide.

[0028] Wherein, the c-Si / SiO X / n+poly tunnel junction, and n+poly / Oxide / n+poly tunnel junction in which n+poly is a phosphorus-doped polysilicon layer with a thickness of 50-300nm, which is formed by deposition or doping; wherein,

[0029] The deposition method includes low-pressure chemical deposition of a polycrystalline silicon layer intrinsically mixed with a microcrystalline silicon phase, with a deposition temperature of 550-650°C;

[0030] Doping methods include ion implantation of phosphorus atoms, phosphorus diffusion, or atmospheric pressure chemical vapor deposition of phosphosilicate glass;

[0031] If the doping method is ion implantation of phosphorus atoms or atmospheric pressure chemical vapor deposition of phosphorus silicon glass, after the doping process is completed, annealing treatment is required, the annealing temperature is 800-950°C, and the annealing time is 5-60 minutes; after annealing, the c-Si / SiO XThe overall square resistance of the / n+poly tunnel junction and the n+poly / Oxide / n+poly tunnel junction is 30~200Ω / sq.

[0032] Among them, in the n+poly / SiO X / p+poly tunnel junction: the p+poly is a boron-doped polysilicon layer, which is deposited by physical vapor deposition of polysilicon in situ doped with boron atoms, and subjected to high-temperature annealing treatment. The annealing temperature is 800-950°C, the annealing time is 5-60min, and the square resistance after annealing is 30-200Ω / sq.

[0033] Among them, in the n+poly / SiO X / p+poly tunnel junction, the doping concentration of n+poly is 2 to 6E+20cm -3 , the doping concentration range of p+poly is 1~4E+20cm -3 .

[0034] The present invention also discloses a back-contact solar cell with multiple tunnel junction structures, including an N-type crystalline silicon substrate,

[0035] The front surface of the N-type crystalline silicon substrate comprises a shallowly doped n+ surface field and a passivation anti-reflection film;

[0036] The back surface of the N-type crystalline silicon substrate comprises a P-type emitter region, an N-type back surface field region, and a groove structure; the P-type emitter region is located in the groove structure, and the N-type back surface field region is located on the groove structure;

[0037] The N-type back surface field region includes tunneling SiO X layer, n+poly layer, oxide layer, n+poly layer, tunneling SiO X layer, and p+poly layer; wherein,

[0038] SiO X The layer and the n+poly layer form a c-Si / SiO X / n+poly tunnel junction, the oxide layer and the n+poly layer form an n+poly / Oxide / n+poly tunnel junction in the N-type back surface field region, tunneling through the SiO X The layer and the p+poly layer form an n+poly / SiO X / p+poly tunnel junction;

[0039] The P-type emitter region includes a tunneling SiOx layer and a p+poly layer from the inside to the outside; XThe layer and the p+poly layer form a c-Si / SiO X / p+poly tunnel junction;

[0040] The P-type emitter region is provided with a P-type metal electrode, and the N-type back surface field region is provided with an N-type metal electrode.

[0041] Wherein, the width of the P-type emitter region is 0.9-1.8 mm, and the width of the N-type back surface field region is 0.6-1.4 mm;

[0042] Wherein, the front surface and the rear surface of the N-type crystalline silicon substrate are both provided with a laminated dielectric film; wherein,

[0043] The front surface of the N-type crystalline silicon substrate is provided with SiO2 / SiN X The thickness of the SiO2 layer is 3-15nm, and the SiN X The thickness of the layer is 60-80 nm;

[0044] The back surface of the N-type crystalline silicon substrate is provided with SiO X 、SiN X , or Al2O3 laminated passivation anti-reflection film of any two kinds; or the back surface of the N-type crystalline silicon substrate is provided with SiO X 、SiN X , and Al2O3 stacked passivation anti-reflection films.

[0045] The implementation of the present invention includes the following technical effects:

[0046] The grid lines of the back-contact battery are all located on the back of the battery, and there is no metal blocking on the front surface, which can significantly reduce optical losses; the tunneling oxide layer passivated metal contact structure has the characteristics of low contact resistivity and low surface recombination, which can significantly reduce recombination losses and resistance losses. Therefore, combining the back-contact battery structure with the tunneling oxide layer passivated metal contact structure can significantly improve the conversion efficiency of the battery. However, the back-contact structure passivated metal contact battery reported in the literature has many technical difficulties: 1) The preparation process (such as photolithography technology, thermal evaporation electrode technology) is a laboratory technology and is suitable for small-sized batteries - 4cm 2 , it is difficult to achieve large-scale batch production on full-size silicon wafers; 2) a multi-step mask process is required; 3) the spacing between the back emitter and the back field needs to be precisely controlled to prevent leakage; 4) precise alignment metallization technology is required.

[0047] The present invention creatively introduces a variety of tunnel junction structures and arc groove structures into back-contact batteries, which can effectively solve the above-mentioned technical difficulties: 1. By utilizing the back contact structure, the front surface can be free of grid line obstruction, significantly reducing optical losses; 2. By utilizing a variety of tunnel junction structures, extremely low surface recombination rates and contact resistivities can be obtained, significantly reducing recombination losses and contact losses in electricity, thereby obtaining higher conversion efficiency and reducing the number of masks; 3. The use of an arc groove structure can not only achieve "self-masking", but also achieve "self-alignment" of the emitter and BSF, which is convenient for precise alignment of screen printing, significantly reducing process steps, reducing the number of masks and the difficulty of the process, and providing a new way to realize the use of passivated metal contact structures in back-contact batteries, which is suitable for large-scale mass production. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 This is a schematic cross-sectional view of a cell structure after step 1 of a method for preparing a back-contact solar cell with multiple tunnel junction structures according to an embodiment of the present invention.

[0049] Figure 2 This is a schematic cross-sectional view of a cell structure after step 2 of a method for preparing a back-contact solar cell with multiple tunnel junction structures according to an embodiment of the present invention.

[0050] Figure 3 This is a schematic cross-sectional view of a cell structure after step three of a method for preparing a back-contact solar cell with multiple tunnel junction structures according to an embodiment of the present invention.

[0051] Figure 4 This is a schematic cross-sectional view of a cell structure after step 4 of a method for preparing a back-contact solar cell with multiple tunnel junction structures according to an embodiment of the present invention.

[0052] Figure 5 This is a schematic cross-sectional view of a cell structure after step five of a method for preparing a back-contact solar cell with multiple tunnel junction structures according to an embodiment of the present invention.

[0053] Figure 6 This is a schematic cross-sectional view of a cell structure after step six of a method for preparing a back-contact solar cell with multiple tunnel junction structures according to an embodiment of the present invention.

[0054] Figure 7 This is a schematic cross-sectional view of a cell structure after step seven of a method for preparing a back-contact solar cell with multiple tunnel junction structures according to an embodiment of the present invention.

[0055] Figure 8 This is a schematic cross-sectional view of a cell structure after step eight of a method for preparing a back-contact solar cell with multiple tunnel junction structures according to an embodiment of the present invention.

[0056] Fig. 9 This is a schematic cross-sectional view of a cell structure after step nine of a method for preparing a back-contact solar cell with multiple tunnel junction structures according to an embodiment of the present invention.

[0057] Fig.10 This is a schematic cross-sectional view of a cell structure after step ten of a method for preparing a back-contact solar cell with multiple tunnel junction structures according to an embodiment of the present invention.

[0058] Fig.11 This is a schematic cross-sectional view of a cell structure after step eleven of a method for preparing a back-contact solar cell with multiple tunnel junction structures according to an embodiment of the present invention.

[0059] Fig.12 This is a schematic cross-sectional view of a cell structure after step twelve of a method for preparing a back-contact solar cell with multiple tunnel junction structures according to an embodiment of the present invention.

[0060] Fig.13 It is a schematic cross-sectional diagram of the cell structure after step thirteen of the method for preparing a back-contact solar cell with multiple tunnel junction structures according to an embodiment of the present invention, that is, a structural diagram of a back-contact solar cell with multiple tunnel junction structures. DETAILED DESCRIPTION

[0061] The present invention is described in detail below with reference to examples.

[0062] The specific embodiments are merely explanations of the present invention, not limitations of the present invention. After reading this specification, those skilled in the art may make modifications to the embodiments without creative contribution as needed, but they are protected as long as they are within the scope of the claims of the present invention.

[0063] The present invention provides a method for preparing a back-contact solar cell having multiple tunnel junction structures, comprising the following steps:

[0064] (1) A tunneling oxide layer is grown on the back surface of the N-type crystalline silicon substrate, and an intrinsic polysilicon layer is deposited on the tunneling oxide layer to form a c-Si / SiO X / i-poly tunnel junction; depositing an oxide layer on the intrinsic polysilicon layer, and depositing an intrinsic polysilicon layer on the oxide layer to form an i-poly / Oxide / i-poly tunnel junction;

[0065] (2) first depositing a mask on the n+ doped region of the front surface; then doping the intrinsic polysilicon layer with phosphorus, activating or advancing the phosphorus atoms at high temperature, so that the intrinsic polysilicon layer is transformed into a phosphorus-doped polysilicon layer to form a c-Si / SiO X / n+poly tunnel junction and n+poly / Oxide / n+poly tunnel junction, and at the same time forming a phosphorus-containing silicon oxide layer on the outer phosphorus-doped polysilicon layer;

[0066] (3) Remove the local phosphorus-containing silicon oxide layer on the back of the N-type crystalline silicon substrate, c-Si / SiO X / n+poly tunnel junction, and n+poly / Oxide / n+poly tunnel junction;

[0067] (4) placing the N-type crystalline silicon substrate in an alkaline solution for isotropic etching, wherein during the etching process, the area on the N-type crystalline silicon substrate covered by the phosphorus-containing silicon oxide layer is not etched, and the area not covered by the phosphorus-containing silicon oxide layer is etched by the alkaline solution into a sunken groove structure;

[0068] (5) placing the N-type crystalline silicon substrate in an acid solution to remove the mask of the n+ doped region on the front surface of the N-type crystalline silicon substrate and the phosphorus-containing silicon oxide layer on the back surface;

[0069] (6) growing a tunneling oxide layer on the back side of the N-type crystalline silicon substrate, and depositing an in-situ boron-doped polysilicon layer on the tunneling oxide layer to form an n+poly / SiO X / p+poly tunnel junction, forming a c-Si / SiO at the bottom of the groove structure X / p+poly tunnel junction; and performing annealing to transform the in-situ boron-doped polysilicon layer into a boron-doped polysilicon layer.

[0070] Preferably, the method further comprises:

[0071] (1) Selecting an N-type crystalline silicon substrate, cleaning the surface of the N-type crystalline silicon substrate, and making a velvet surface;

[0072] (2) Phosphorus diffusion is performed on the textured surface of the N-type crystalline silicon substrate to form a double-sided n+ doped region;

[0073] (3)', etching the back surface of the N-type crystalline silicon substrate, and performing a polishing process to remove the n+ doped region on the back surface of the N-type crystalline silicon substrate.

[0074] Preferably, the method further comprises:

[0075] (7) depositing a passivation film on the back side of the N-type crystalline silicon substrate after the treatment in step (6), and depositing an anti-reflection film on the front side of the N-type crystalline silicon substrate;

[0076] (8) A metal gate line having an interdigitated structure is formed on the N-type back surface field region and the P-type emitter region on the back side of the N-type crystalline silicon substrate.

[0077] Wherein, the groove structure is an arc-shaped groove structure, the maximum width of which is 0.9-1.8 mm and the depth of which is 3-10 μm.

[0078] Preferably, the c-Si / SiO X / n+poly tunnel junction, and c-Si / SiO X SiO in p+poly tunnel junction X A tunneling oxide layer having a thickness of 0.5-3.5 nm and grown by thermal oxidation, HNO3 oxidation, O3 oxidation, or atomic layer deposition;

[0079] The Oxide in the n+poly / Oxide / n+poly tunnel junction is an oxide layer with a thickness of 2.0-15 nm, and is grown by PECVD or atomic layer deposition.

[0080] Wherein, the oxide layer includes silicon oxide, aluminum oxide, or titanium dioxide.

[0081] Preferably, the c-Si / SiO X / n+poly tunnel junction, and n+poly / Oxide / n+poly tunnel junction in which n+poly is a phosphorus-doped polysilicon layer with a thickness of 50-300nm, which is formed by deposition or doping; wherein,

[0082] The deposition method includes low-pressure chemical deposition of a polycrystalline silicon layer intrinsically mixed with a microcrystalline silicon phase, with a deposition temperature of 550-650°C;

[0083] Doping methods include ion implantation of phosphorus atoms, phosphorus diffusion, or atmospheric pressure chemical vapor deposition of phosphosilicate glass;

[0084] If the doping method is ion implantation of phosphorus atoms or atmospheric pressure chemical vapor deposition of phosphorus silicon glass, after the doping process is completed, annealing treatment is required, the annealing temperature is 800-950°C, and the annealing time is 5-60 minutes; after annealing, the c-Si / SiO X The overall square resistance of the / n+poly tunnel junction and the n+poly / Oxide / n+poly tunnel junction is 30~200Ω / sq.

[0085] Preferably, in the n+poly / SiO X / p+poly tunnel junction:

[0086] The p+poly is a boron-doped polysilicon layer, which is deposited by physical vapor deposition of polysilicon in situ doped with boron atoms and subjected to high-temperature annealing treatment. The annealing temperature is 800-950°C, the annealing time is 5-60 minutes, and the square resistance after annealing is 30-200Ω / sq.

[0087] Preferably, in the n+poly / SiO X / p+poly tunnel junction,

[0088] The doping concentration of the n+poly is 2 to 6E+20cm -3 , the doping concentration range of p+poly is 1~4E+20cm -3 .

[0089] The present invention also discloses a back-contact solar cell with multiple tunnel junction structures, including an N-type crystalline silicon substrate,

[0090] The front surface of the N-type crystalline silicon substrate comprises a shallowly doped n+ surface field and a passivation anti-reflection film;

[0091] The back surface of the N-type crystalline silicon substrate comprises a P-type emitter region, an N-type back surface field region, and a groove structure; the P-type emitter region is located in the groove structure, and the N-type back surface field region is located on the groove structure;

[0092] The N-type back surface field region includes tunneling SiO X layer, n+poly layer, oxide layer, n+poly layer, tunneling SiO X layer, and p+poly layer; wherein,

[0093] SiO X The layer and the n+poly layer form a c-Si / SiO X / n+poly tunnel junction, the oxide layer and the n+poly layer form an n+poly / Oxide / n+poly tunnel junction in the N-type back surface field region, tunneling through the SiO X The layer and the p+poly layer form an n+poly / SiO X / p+poly tunnel junction;

[0094] The P-type emitter region includes a tunneling SiOx layer and a p+poly layer from the inside to the outside; X The layer and the p+poly layer form a c-Si / SiO X / p+poly tunnel junction;

[0095] The P-type emitter region is provided with a P-type metal electrode, and the N-type back surface field region is provided with an N-type metal electrode.

[0096] Wherein, the width of the P-type emitter region is 0.1-10 mm, and the width of the N-type back surface field region is 0.1-10 mm; preferably, the width of the P-type emitter region is 0.9-1.8 mm, and the width of the N-type back surface field region is 0.6-1.4 mm;

[0097] Preferably, both the front surface and the rear surface of the N-type crystalline silicon substrate are provided with a laminated dielectric film; wherein,

[0098] The front surface of the N-type crystalline silicon substrate is provided with SiO2 / SiN X The thickness of the SiO2 layer is 3-15nm, and the SiN X The thickness of the layer is 60-80 nm;

[0099] The back surface of the N-type crystalline silicon substrate is provided with SiO X 、SiN X , or Al2O3 laminated passivation anti-reflection film of any two kinds; or the back surface of the N-type crystalline silicon substrate is provided with SiO X 、SiN X , and Al2O3 stacked passivation anti-reflection films.

[0100] The present invention aims at the shortcomings of the existing IBC structured passivated contact cells, such as high technical threshold (photolithography technology), many mask times, and incompatibility with industrialized sintering processes, and provides a passivated metal contact solar cell with multiple tunnel junction structures and a preparation method. The present invention creatively uses multiple tunnel junction structures and arc groove structures. Among them, multiple tunnel junction structures can: 1) regulate the doping distribution of phosphorus atoms in the single crystal silicon substrate to obtain a lower surface recombination rate; 2) avoid the metal electrode penetrating the doped polysilicon layer and directly contacting the silicon substrate during the sintering process, greatly reducing the metal contact recombination; 3) significantly reduce the number of masks, and the preparation of the back structure of the battery can be achieved by "self-masking", and no additional masking process is required on the back.

[0101] The arc-shaped groove structure can: 1) spatially separate the phosphorus-doped polysilicon layer and the boron-doped polysilicon layer in the back contact battery, achieve "self-alignment" of the emitter and BSF, and significantly reduce battery leakage; 2) during screen printing, the height difference caused by the arc-shaped groove will show different contrasts when the alignment camera is imaging, which is convenient for precise alignment of the printer.

[0102] The first of many tunnel junctions: c-Si / SiO X / n+poly or c-Si / SiO X / p+poly is used to passivate the contact interface of n-type crystalline silicon substrate to obtain extremely low surface recombination rate, SiO X / n+poly can achieve less than 5fA / cm in the contact area 2 J0 value, SiO X / p+poly can obtain less than 10fA / cm in the contact area 2 The J0 value can significantly reduce the surface composite loss.

[0103] The second type of tunnel junction n+poly / Oxide / n+poly among the multiple tunnel junctions is used to regulate the doping distribution of phosphorus atoms.

[0104] It should be noted that in the present invention, n+poly needs to undergo two annealing processes: one is to activate the phosphorus atoms in n+poly and completely crystallize it into polysilicon, and the second is to activate the boron atoms in p+poly and completely crystallize it. Therefore, the two annealing processes make it particularly important to control the doping distribution of phosphorus atoms in n+poly and n-type crystalline silicon substrate through the n+poly / Oxide / n+poly structure to obtain a very low surface recombination rate and a very low contact resistivity.

[0105] The oxide layer materials in the present invention, such as silicon oxide, titanium oxide, aluminum oxide, etc., have the following two characteristics: 1) have a lower diffusion coefficient for doping atoms (such as phosphorus atoms) and 2) are more difficult to burn through by metal slurry. By using oxide layer materials of different thicknesses and different types to separate the doped polysilicon layer, when the doping atoms diffuse inward from the surface of the polysilicon layer, the oxide layer of appropriate thickness (such as silicon oxide, titanium oxide, aluminum oxide, etc.) will block most of the doping atoms in the outer layer n+poly, preventing the doping atoms from excessively entering the inner layer (close to the n-Si side) n+poly and the n-type crystalline silicon substrate, so that the band tail of the doping atoms in the silicon substrate is shallower.

[0106] The third tunnel junction among various tunnel junctions is n+poly / SiO X / The function of p+poly is to transmit carriers, which is equivalent to a wire.

[0107] In the present invention, in order to reduce the number of masks and process steps, no additional mask is required on the n+poly during physical vapor deposition of p+poly. Therefore, the same material as the emitter will be deposited on the n+poly, namely: SiO X / p+poly. During the secondary annealing process, the middle SiO XIt will block the diffusion of boron atoms in p+poly into n+poly, making the transition of doping at the contact interface between n+poly and p+poly very "sharp". Both heavily doped n+poly and p+poly are degenerate semiconductors. The Fermi level in p+poly is below the valence band, and the Fermi level in n+poly is above the conduction band. There are many empty "states" in the valence band of p+poly that are not occupied by electrons. The electrons in the conduction band of n+poly can directly tunnel to the holes in p+poly to realize the transmission of carriers, which is equivalent to a wire.

[0108] The following is a detailed description of the method for preparing back-contact solar cells with various tunnel junction structures using specific embodiments.

[0109] Example 1

[0110] (1) The front and back surfaces of the N-type crystalline silicon substrate 1 are cleaned, the damaged layer is removed, and the surface is textured. Figure 1 As shown; wherein, the resistivity of the N-type silicon substrate is 0.3 to 10Ω·cm, and the thickness is 90 to 300μm.

[0111] (2) Double-sided phosphorus diffusion is performed on the textured N-type crystalline silicon substrate 1 to form a double-sided n+ doped region 2, such as Figure 2 As shown; wherein phosphorus oxychloride is used as the phosphorus source, the diffusion temperature is 800-1000°C, and the sheet resistance of the n+ doped region after phosphorus diffusion is 150-400Ω / sq.

[0112] (3) Etching and polishing the back surface of the N-type crystalline silicon substrate 1, such as Figure 3 As shown; using heated TMAH or NaOH solution, the back n+ doped region 2 is removed and polished, and the weight loss of the silicon wafer is 0.1 to 0.5 g.

[0113] (4) An ultra-thin tunneling silicon dioxide layer 3 with a thickness of 1.1 nm is grown on the polished surface of the silicon wafer by thermal oxidation, and then a 50 nm intrinsic polycrystalline silicon layer 41 (containing a microcrystalline silicon phase) is deposited in a low-pressure chemical vapor deposition device to form the first c-Si / SiO X / i-poly tunnel junction; then use atomic layer deposition to deposit a 5nm titanium dioxide layer 5, and then use low-pressure chemical vapor deposition equipment to deposit a 150nm intrinsic polysilicon layer 42 (containing microcrystalline silicon phase) to form a second i-poly / Oxide / i-poly, such as Figure 4 As shown; wherein the deposition temperature of the intrinsic polysilicon 41 and 42 is 550-650°C.

[0114] (5) On the front surface n+ doped region 2, a layer of SiO is deposited by PECVD. XMask 6, such as Figure 5 As shown, the thickness is 200 nm.

[0115] (6) Doping the intrinsic polysilicon layer by ion implantation, such as Figure 6 As shown in the figure, the phosphorus source of the ion implanter is phosphine, and the implantation dose is 6.0E+15cm -2 After the phosphorus atoms are injected, the silicon wafer is activated at high temperature. The annealing temperature is 875°C. Oxygen is introduced during the annealing process. The annealing time is 60 minutes. The intrinsic polysilicon layers 41 and 42 containing microcrystalline silicon phase will be completely transformed into phosphorus-doped polysilicon layers 71 and 72. The peak doping concentration of 71 and 72 is 4E+20cm -3 , forming c-Si / SiO X / n+poly tunnel junction and n+poly / Oxide / n+poly tunnel junction, the overall square resistance of the tunnel junction is 30-200Ω / sq. Due to the introduction of oxygen during the high temperature process, a phosphorus-containing silicon oxide layer 8 with a thickness of 40nm is formed on the surface after annealing.

[0116] (7) A picosecond laser with a laser wavelength of 532 nm is used to locally remove the phosphorus-containing silicon oxide layer, the polysilicon layers 71 and 72, the titanium dioxide layer 5, and the silicon dioxide layer 3 to the N-type silicon substrate 1. The laser energy density is set to 1 J·cm -2 ,like Figure 7 As shown, the laser film opening method is an equidistant array film opening method, the laser film opening width is 1.2mm, and the laser spacing is 1.6mm.

[0117] (8) The silicon wafer is immersed in an alkaline solution with a high selective reaction ratio (Si: phosphorus-containing silicon oxide layer>100:1) for isotropic etching. The area covered by the phosphorus-containing silicon oxide layer is protected, and the area where the phosphorus-containing silicon oxide layer is removed by laser is etched away by the alkaline solution, forming an inwardly concave arc groove structure 9, as shown in FIG. Figure 8 As shown; the depth of the arc-shaped groove structure 9 is 4μm, and the diameter of the inwardly recessed arc-shaped side wall is 4μm.

[0118] (9) Using HF solution to remove the mask 6 of the n+ doped area on the front surface and the phosphorus-containing silicon oxide layer 8 on the back surface, as shown in FIG. Fig. 9 As shown, the volume fraction ratio of the HF solution is 5 to 20%.

[0119] (10) An ultra-thin tunneling silicon dioxide layer 3 with a thickness of 1.7 nm is grown on the back surface of the silicon wafer. Then, a polysilicon layer 10 with a thickness of 200 nm and in-situ boron doping is deposited by physical vapor deposition to form a third tunnel junction n+poly / SiO2 in the area without laser film opening. X / p+poly, c-Si / SiO is formed in the bottom area of ​​the arc-shaped groove structure 9 X / p+poly tunnel junction, passivated metal contact, such as Fig.10 shown.

[0120] (11) Annealing the silicon wafer, such as Fig.11 As shown; the annealing temperature is 915°C and the annealing time is 5 minutes. During the annealing process, the boron atoms in the in-situ boron-doped polysilicon layer 10 can be completely activated to become a boron-doped polysilicon layer 11. The square resistance after annealing is 90Ω / sq, and the peak doping concentration of the boron-doped polysilicon layer 11 is 2E+20cm -3 , the transition of doped atoms at the contact interface between the phosphorus-doped polysilicon layer 72 and the boron-doped polysilicon layer 11 is very sharp.

[0121] (12) Deposition of three layers of SiO2 / Al2O3 / SiN on the back surface X The film 12 is used for surface passivation, such as Fig.12 As shown, the bottom SiO2 layer is 1nm thick, the middle Al2O3 layer is 3nm thick, and the top SiN X The layer thickness is 65nm and the refractive index is 2.2; then SiO2 / SiN is deposited on the front surface X The laminated film 13 is used for anti-reflection and passivation, wherein the thickness of the SiO2 layer is 5nm, and the thickness of the SiN X The layer thickness is 60 nm and the refractive index is 2.05.

[0122] (13) Metal gate lines 14 and 15 with interdigital structures are formed on the N-type back surface field region and the P-type emitter region on the back side of the battery by screen printing and sintering. Fig.13 As shown, the width of the metal gate line 14 is 150 μm, the number of the metal gate line 14 is 98, the width of the metal gate line 15 is 90 μm, the number of the metal gate line 15 is 98, and the height is 10 μm.

[0123] Example 2

[0124] (1) The front and back surfaces of the N-type crystalline silicon substrate 1 are cleaned, the damaged layer is removed, and the surface is textured. Figure 1 As shown; wherein, the resistivity of the N-type silicon substrate is 0.3 to 10Ω·cm, and the thickness is 90 to 300μm.

[0125] (2) Double-sided phosphorus diffusion is performed on the textured N-type crystalline silicon substrate 1 to form a double-sided n+ doped region 2, such as Figure 2 As shown; wherein phosphorus oxychloride is used as the phosphorus source, the diffusion temperature is 800-1000°C, and the sheet resistance of the n+ doped region after phosphorus diffusion is 150-400Ω / sq.

[0126] (3) Etching and polishing the back surface of the N-type crystalline silicon substrate 1, such as Figure 3As shown; using heated TMAH or NaOH solution, the back n+ doped region 2 is removed and polished, and the weight loss of the silicon wafer is 0.1 to 0.5 g.

[0127] (4) An ultra-thin tunneling silicon dioxide layer 3 with a thickness of 1.7 nm is grown on the polished surface of the silicon wafer by thermal oxidation, and then a 50 nm intrinsic polycrystalline silicon layer 41 (containing a microcrystalline silicon phase) is deposited in a low-pressure chemical vapor deposition device to form the first c-Si / SiO X / i-poly tunnel junction; then use PECVD technology to deposit a 5nm aluminum oxide layer 5, and then use low-pressure chemical vapor deposition equipment again to deposit a 150nm intrinsic polysilicon layer 42 (containing microcrystalline silicon phase) to form a second i-poly / Oxide / i-poly, such as Figure 4 As shown; wherein the deposition temperature of the intrinsic polysilicon 41 and 42 is 550-650°C.

[0128] (5) On the front surface n+ doped region 2, a layer of SiO is deposited by PECVD. X Mask 6, such as Figure 5 As shown, thickness ~200 nm.

[0129] (6) Doping the intrinsic polysilicon layer by ion implantation, such as Figure 6 As shown in the figure, the phosphorus source of the ion implanter is phosphine, and the implantation dose is 6.0E+15cm -2 After the phosphorus atoms are injected, the silicon wafer is activated at high temperature. The annealing temperature is 875°C. Oxygen is introduced during the annealing process. The annealing time is 60 minutes. The intrinsic polysilicon layers 41 and 42 containing microcrystalline silicon phase will be completely transformed into phosphorus-doped polysilicon layers 71 and 72. The peak doping concentration of 71 and 72 is 4E+20cm -3 , forming c-Si / SiO X / n+poly tunnel junction and n+poly / Oxide / n+poly tunnel junction, the overall square resistance of the tunnel junction is 30-200Ω / sq. Due to the introduction of oxygen during the high temperature process, a phosphorus-containing silicon oxide layer 8 with a thickness of 40nm is formed on the surface after annealing.

[0130] (7) A picosecond laser with a laser wavelength of 532 nm is used to locally remove the phosphorus-containing silicon oxide layer 8, the polysilicon layers 71 and 72, the aluminum oxide layer 5, and the silicon dioxide layer 3 to the N-type silicon substrate 1. The laser energy density is set to 1 J·cm -2 ,like Figure 7 As shown, the laser film opening method is an equidistant array film opening method, the laser film opening width is 1.2mm, and the laser spacing is 1.6mm.

[0131] (8) The silicon wafer is immersed in an alkaline solution with a high selective reaction ratio (Si: phosphorus-containing silicon oxide layer>100:1) for isotropic etching. The area covered by the phosphorus-containing silicon oxide layer is protected, and the area where the phosphorus-containing silicon oxide layer is removed by laser is etched away by the alkaline solution, forming an inwardly concave arc groove structure 9, as shown in FIG. Figure 8 As shown; the depth of the arc-shaped groove structure 9 is 4μm, and the diameter of the inwardly recessed arc-shaped side wall is 4μm.

[0132] (9) Using HF solution to remove the mask 6 of the n+ doped area on the front surface and the phosphorus-containing silicon oxide layer 8 on the back surface, as shown in FIG. Fig. 9 As shown, the volume fraction ratio of the HF solution is 8 to 16%.

[0133] (10) An ultra-thin tunneling silicon dioxide layer 3 with a thickness of 1.7 nm is grown on the back surface of the silicon wafer. Then, a polysilicon layer 10 with a thickness of 200 nm and in-situ boron doping is deposited by physical vapor deposition to form a third tunnel junction n+poly / SiO2 in the area without laser film opening. X / p+poly, c-Si / SiO is formed in the bottom area of ​​the arc-shaped groove structure 9 X / p+poly tunnel junction, passivated metal contact, such as Fig.10 shown.

[0134] (11) Annealing the silicon wafer, such as Fig.11 As shown; the annealing temperature is 915°C and the annealing time is 5 minutes. During the annealing process, the boron atoms in the in-situ boron-doped polysilicon layer 10 can be completely activated to become a boron-doped polysilicon layer 11. The square resistance after annealing is 90Ω / sq, and the peak doping concentration of the boron-doped polysilicon layer 11 is 2E+20cm -3 , the transition of doped atoms at the contact interface between the phosphorus-doped polysilicon layer 72 and the boron-doped polysilicon layer 11 is very sharp.

[0135] (12) A three-layer SiO2 / Al2O3 film 12 is deposited on the back surface for surface passivation, such as Fig.12 As shown, the bottom SiO2 layer is 5nm thick, the middle Al2O3 layer is 60nm thick, and the refractive index is 2.2; then SiO2 / SiN is deposited on the front surface X The laminated film 13 is used for anti-reflection and passivation, wherein the SiO2 layer has a thickness of 10nm and the SiN X The layer thickness is 80 nm and the refractive index is 2.05.

[0136] (13) Metal gate lines 14 and 15 with interdigital structures are formed on the N-type back surface field region and the P-type emitter region on the back side of the battery by screen printing and sintering. Fig.13As shown; the width of the metal gate line 14 is 150μm, the number of roots is 98, the width of the metal gate line 15 is 90μm, the number of roots is 98, and the height is 30μm.

[0137] Example 3

[0138] (1) The front and back surfaces of the N-type crystalline silicon substrate 1 are cleaned, the damaged layer is removed, and the surface is textured. Figure 1 As shown; wherein, the resistivity of the N-type silicon substrate is 0.3 to 10Ω·cm, and the thickness is 90 to 300μm.

[0139] (2) Double-sided phosphorus diffusion is performed on the textured N-type crystalline silicon substrate 1 to form a double-sided n+ doped region 2, such as Figure 2 As shown; wherein phosphorus oxychloride is used as the phosphorus source, the diffusion temperature is 800-1000°C, and the sheet resistance of the n+ doped region after phosphorus diffusion is 150-400Ω / sq.

[0140] (3) Etching and polishing the back surface of the N-type crystalline silicon substrate 1, such as Figure 3 As shown; using heated TMAH or NaOH solution, the back n+ doped region 2 is removed and polished, and the weight loss of the silicon wafer is 0.1 to 0.5 g.

[0141] (4) An ultra-thin tunneling silicon dioxide layer 3 is grown on the polished surface of the silicon wafer by thermal oxidation, with a thickness of 1.4 nm, and then a 50 nm intrinsic polycrystalline silicon layer 41 (containing a microcrystalline silicon phase) is deposited in a low-pressure chemical vapor deposition device to form the first c-Si / SiO X / i-poly tunnel junction; then use atomic layer deposition to deposit a 5nm aluminum oxide layer 5, and then use low-pressure chemical vapor deposition equipment to deposit a 150nm intrinsic polysilicon layer 42 (containing microcrystalline silicon phase) to form a second i-poly / Oxide / i-poly, such as Figure 4 As shown; wherein the deposition temperature of the intrinsic polysilicon 41 and 42 is 550-650°C.

[0142] (5) On the front surface n+ doped region 2, a layer of SiO is deposited by PECVD. X Mask 6, such as Figure 5 As shown, the thickness is 200 nm.

[0143] (6) Doping the intrinsic polysilicon layer by ion implantation, such as Figure 6 As shown in the figure, the phosphorus source of the ion implanter is phosphine, and the implantation dose is 6.0E+15cm -2After the phosphorus atoms are injected, the silicon wafer is activated at high temperature. The annealing temperature is 875°C. Oxygen is introduced during the annealing process. The annealing time is 60 minutes. The intrinsic polysilicon layers 41 and 42 containing microcrystalline silicon phase will be completely transformed into phosphorus-doped polysilicon layers 71 and 72. The peak doping concentration of 71 and 72 is 4E+20cm -3 , forming c-Si / SiO X / n+poly tunnel junction and n+poly / Oxide / n+poly tunnel junction, the overall square resistance of the tunnel junction is 30-200Ω / sq. Due to the introduction of oxygen during the high temperature process, a phosphorus-containing silicon oxide layer 8 with a thickness of 40nm is formed on the surface after annealing.

[0144] (7) A picosecond laser with a laser wavelength of 532 nm is used to locally remove the phosphorus-containing silicon oxide layer, the polysilicon layers 71 and 72, the aluminum oxide 5, and the silicon dioxide layer 3 to the N-type silicon substrate 1. The laser energy density is set to 1 J·cm -2 ,like Figure 7 As shown, the laser film opening method is an equidistant array film opening method, the laser film opening width is 1.2mm, and the laser spacing is 1.6mm.

[0145] (8) The silicon wafer is immersed in an alkaline solution with a high selective reaction ratio (Si: phosphorus-containing silicon oxide layer>100:1) for isotropic etching. The area covered by the phosphorus-containing silicon oxide layer is protected, and the area where the phosphorus-containing silicon oxide layer is removed by laser is etched away by the alkaline solution, forming an inwardly concave arc groove structure 9, as shown in FIG. Figure 8 As shown; the depth of the arc-shaped groove structure 9 is 4μm, and the diameter of the inwardly recessed arc-shaped side wall is 4μm.

[0146] (9) Using HF solution to remove the mask 6 of the n+ doped area on the front surface and the phosphorus-containing silicon oxide layer 8 on the back surface, as shown in FIG. Fig. 9 As shown, the volume fraction ratio of the HF solution is 15%.

[0147] (10) An ultra-thin tunneling silicon dioxide layer 3 with a thickness of 1.7 nm is grown on the back surface of the silicon wafer. Then, a polysilicon layer 10 with a thickness of 200 nm and in-situ boron doping is deposited by physical vapor deposition to form a third tunnel junction n+poly / SiO2 in the area without laser film opening. X / p+poly, c-Si / SiO is formed in the bottom area of ​​the arc-shaped groove structure 9 X / p+poly tunnel junction, passivated metal contact, such as Fig.10 shown.

[0148] (11) Annealing the silicon wafer, such as Fig.11As shown; the annealing temperature is 915°C and the annealing time is 5 minutes. During the annealing process, the boron atoms in the in-situ boron-doped polysilicon layer 10 can be completely activated to become a boron-doped polysilicon layer 11. The square resistance after annealing is 90Ω / sq, and the peak doping concentration of the boron-doped polysilicon layer 11 is 2E+20cm -3 , the transition of doped atoms at the contact interface between the phosphorus-doped polysilicon layer 72 and the boron-doped polysilicon layer 11 is very sharp.

[0149] (12) Deposition of two layers of Al2O3 / SiN on the back surface X The film 12 is used for surface passivation, such as Fig.12 As shown, the thickness of the bottom layer Al2O3 is 6nm and the top layer SiN X The layer thickness is 45nm and the refractive index is 2.2; then SiO2 / SiN is deposited on the front surface X The laminated film 13 is used for anti-reflection and passivation, wherein the thickness of the SiO2 layer is 8nm, and the thickness of the SiN X The layer thickness is 70 nm and the refractive index is 2.05.

[0150] (13) Metal gate lines 14 and 15 with interdigital structures are formed on the N-type back surface field region and the P-type emitter region on the back side of the battery by screen printing and sintering. Fig.13 As shown, the width of the metal gate line 14 is 150 μm, the number of the metal gate line 14 is 98, the width of the metal gate line 15 is 90 μm, the number of the metal gate line 15 is 98, and the height is 20 μm.

[0151] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention, rather than to limit the scope of protection of the present invention. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the essence and scope of the technical solution of the present invention.

Claims

1. A method for preparing a back-contact solar cell having multiple tunnel junction structures, characterized in that: The following steps are involved: (1) A tunneling oxide layer is grown on the back surface of the N-type crystalline silicon substrate, and an intrinsic polysilicon layer is deposited on the tunneling oxide layer to form a c-Si / SiO X / i-poly tunnel junction; depositing an oxide layer on the intrinsic polysilicon layer, and depositing an intrinsic polysilicon layer on the oxide layer to form an i-poly / Oxide / i-poly tunnel junction; (2) After depositing a mask on the front surface n+ doped region, the intrinsic polysilicon layer is phosphorus doped, and phosphorus atoms are activated or pushed forward at high temperature to transform the intrinsic polysilicon layer into a phosphorus-doped polysilicon layer to form a c-Si / SiO X / n+poly tunnel junction and n+poly / Oxide / n+poly tunnel junction, and at the same time forming a phosphorus-containing silicon oxide layer on the outer phosphorus-doped polysilicon layer; (3) Remove the local phosphorus-containing silicon oxide layer on the back of the N-type crystalline silicon substrate, c-Si / SiO X / n+poly tunnel junction, and n+poly / Oxide / n+poly tunnel junction; (4) placing the N-type crystalline silicon substrate in an alkaline solution for isotropic etching, wherein during the etching process, the area on the N-type crystalline silicon substrate covered by the phosphorus-containing silicon oxide layer is not etched, and the area not covered by the phosphorus-containing silicon oxide layer is etched by the alkaline solution into a sunken groove structure; (5) placing the N-type crystalline silicon substrate in an acid solution to remove the mask of the n+ doped region on the front surface of the N-type crystalline silicon substrate and the phosphorus-containing silicon oxide layer on the back surface; (6) growing a tunneling oxide layer on the back side of the N-type crystalline silicon substrate, and depositing an in-situ boron-doped polysilicon layer on the tunneling oxide layer to form an n+poly / SiO X / p+poly tunnel junction, forming a c-Si / SiO at the bottom of the groove structure X / p+poly tunnel junction; and performing annealing to transform the in-situ boron-doped polysilicon layer into a boron-doped polysilicon layer.

2. The preparation method according to claim 1, characterized in that: Before step (1), the method further comprises: (1) Selecting an N-type crystalline silicon substrate, cleaning the surface of the N-type crystalline silicon substrate, and making a velvet surface; (2) Phosphorus diffusion is performed on the textured surface of the N-type crystalline silicon substrate to form a double-sided n+ doped region; (3)', etching the back surface of the N-type crystalline silicon substrate, and performing a polishing process to remove the n+ doped region on the back surface of the N-type crystalline silicon substrate.

3. The preparation method according to claim 2, characterized in that: The method further comprises: (7) depositing a passivation film on the back side of the N-type crystalline silicon substrate after the treatment in step (6), and depositing an anti-reflection film on the front side of the N-type crystalline silicon substrate; (8) A metal gate line having an interdigitated structure is formed on the N-type back surface field region and the P-type emitter region on the back side of the N-type crystalline silicon substrate.

4. The preparation method according to any one of claims 1 to 3, characterized in that The groove structure is an arc-shaped groove structure, with a maximum width of 0.9 to 1.8 mm and a depth of 3 to 10 μm.

5. The preparation method according to claim 4, characterized in that: The c-Si / SiO X / n+poly tunnel junction, and c-Si / SiO X SiO in p+poly tunnel junction X A tunneling oxide layer having a thickness of 0.5-3.5 nm and grown by thermal oxidation, HNO3 oxidation, O3 oxidation, or atomic layer deposition; The Oxide in the n+poly / Oxide / n+poly tunnel junction is an oxide layer with a thickness of 2.0-15 nm, and is grown by PECVD or atomic layer deposition.

6. The preparation method according to claim 5, characterized in that: The oxide layer includes silicon oxide, aluminum oxide, or titanium dioxide.

7. The preparation method according to claim 4, characterized in that: The c-Si / SiO X / n+poly tunnel junction, and n+poly / Oxide / n+poly tunnel junction in which n+poly is a phosphorus-doped polysilicon layer with a thickness of 50-300nm, formed by deposition or doping; wherein, The deposition method includes low-pressure chemical deposition of a polycrystalline silicon layer intrinsically mixed with a microcrystalline silicon phase, with a deposition temperature of 550-650°C; Doping methods include ion implantation of phosphorus atoms, phosphorus diffusion, or atmospheric pressure chemical vapor deposition of phosphosilicate glass.

8. The preparation method according to claim 7, characterized in that: The doping method is ion implantation of phosphorus atoms or atmospheric pressure chemical vapor deposition of phosphorus silicon glass. After the doping process is completed, annealing treatment is required. The annealing temperature is 800-950°C and the annealing time is 5-60 minutes. After annealing, the c-Si / SiO X The overall square resistance of the / n+poly tunnel junction and the n+poly / Oxide / n+poly tunnel junction is 30~200Ω / sq.

9. The preparation method according to claim 4, characterized in that: In the n+poly / SiO X / p+poly tunnel junction: the p+poly is a boron-doped polysilicon layer, which is deposited by physical vapor deposition of polysilicon in situ doped with boron atoms, and subjected to high-temperature annealing treatment. The annealing temperature is 800-950°C, the annealing time is 5-60min, and the square resistance after annealing is 30-200Ω / sq.

10. The preparation method according to claim 9, characterized in that: In the n+poly / SiO X / p+poly tunnel junction, the doping concentration of the n+poly is 2 to 6E+20cm -3 , the doping concentration range of p+poly is 1~4E+20cm -3 .

11. A back-contact solar cell with multiple tunnel junction structures, comprising an N-type crystalline silicon substrate, characterized in that: The front surface of the N-type crystalline silicon substrate comprises a shallowly doped n+ surface field and a passivation anti-reflection film; The back surface of the N-type crystalline silicon substrate comprises a P-type emitter region, an N-type back surface field region, and a groove structure; the P-type emitter region is located in the groove structure, and the N-type back surface field region is located on the groove structure; The N-type back surface field region includes tunneling SiO X layer, n+poly layer, oxide layer, n+poly layer, tunneling SiO X layer, and p+poly layer; wherein, The SiO X The layer and the n+poly layer form a c-Si / SiO X / n+poly tunnel junction, the oxide layer and the n+poly layer form an n+poly / Oxide / n+poly tunnel junction in the N-type back surface field region, tunneling through the SiO X The layer and the p+poly layer form an n+poly / SiO X / p+poly tunnel junction; The P-type emitter region includes tunneling SiO X layer and p+poly layer; the SiO X The layer and the p+poly layer form a c-Si / SiO X / p+poly tunnel junction; The P-type emitter region is provided with a P-type metal electrode, and the N-type back surface field region is provided with an N-type metal electrode; The oxide layer is silicon oxide, aluminum oxide, or titanium dioxide.

12. The back contact solar cell according to claim 11, characterized in that: The width of the P-type emitter region is 0.9-1.8 mm, and the width of the N-type back surface field region is 0.6-1.4 mm.

13. The back contact solar cell according to claim 11, characterized in that: The front surface and the rear surface of the N-type crystalline silicon substrate are both provided with a laminated dielectric film; wherein, The front surface of the N-type crystalline silicon substrate is provided with SiO2 / SiN X The thickness of the SiO2 layer is 3-15nm, and the SiN X The thickness of the layer is 60-80 nm; The back surface of the N-type crystalline silicon substrate is provided with SiO X 、SiN X , or Al2O3 laminated passivation anti-reflection film of any two kinds; or the back surface of the N-type crystalline silicon substrate is provided with SiO X 、SiN X , and Al2O3 three kinds of stacked passivation anti-reflection films.

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