A semiconductor structure and a method for manufacturing the same
By forming an insulating structure in the semiconductor memory and precisely controlling the size of the capacitor contact node, the problem of low yield of the capacitor contact node in the prior art is solved, and the reliability and conductivity of the memory chip are improved.
Patent Information
- Application Number
- CN201811160228.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2018-09-30
- Publication Date
- 2024-12-06
- Estimated Expiration
- 2038-09-30
AI Technical Summary
In the prior art, the semiconductor memory capacitor contact node has poor yield due to graphical transfer deviation, especially in small feature sizes, the capacitor contact electrode is prone to be disconnected or shorted, affecting the reliability of the memory chip.
A plurality of bit line structures and dielectric walls are formed on the substrate, the upper surface of the dielectric wall is higher than the bit line structure, covering its overlapping parts, forming an insulating structure to separate the capacitor storage node window, and then depositing a layer of conductive material therein, Etching forms a capacitive contact node structure, avoids short circuits through an insulating structure, and precisely controls the size of the contact nodes through dry etching and I-shaped mask structure.
The production yield of capacitor contact nodes is improved, short circuit and circuit breaker problems are avoided, process difficulty is reduced, parasitic capacitors are reduced, and the conductive characteristics of the circuit are enhanced.
Smart Images
Figure CN110970436B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor memory, and in particular to a semiconductor structure and a manufacturing method thereof. Background Art
[0002] Dynamic random access memory (DRAM) is a widely used semiconductor product, whose basic storage unit includes an access transistor and a capacitor. As the feature size of semiconductors continues to decrease, the area of capacitor contact nodes is getting smaller and smaller, and the manufacturing difficulty is getting greater and greater. The alignment deviation of the photolithography process and the increase in the difficulty of the etching process seriously affect the electrical reliability of the memory capacitor contact node, causing the capacitor contact electrode to be disconnected or short-circuited with the adjacent contact electrode, reducing the yield of the memory chip. Summary of the invention
[0003] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a semiconductor structure and a manufacturing method thereof, so as to solve the problem of poor yield of memory capacitor contact nodes caused by pattern transfer deviation in the prior art.
[0004] To achieve the above-mentioned object and other related objects, the present invention provides a method for manufacturing a semiconductor structure, the method at least comprising:
[0005] forming a plurality of bit line structures on a substrate;
[0006] forming a plurality of dielectric walls on the substrate, wherein the upper surfaces of the dielectric walls are higher than the upper surfaces of the bit line structures, and the dielectric walls extend to cover the portions overlapping with the bit line structures;
[0007] Making an insulating structure in the capacitor storage node window surrounded by the bit line structure and the dielectric wall to form a separated capacitor storage node window;
[0008] depositing a conductive material layer in the separated capacitor storage node window;
[0009] The conductive material layer is etched back to form capacitor contact node structures on both sides of the insulating structure.
[0010] In one implementation of the present invention, the step of manufacturing an insulating structure in a capacitor storage node window surrounded by the bit line structure and the dielectric wall includes:
[0011] forming an insulating sidewall of the dielectric wall;
[0012] Depositing a sacrificial layer to cover the capacitor storage node window, the bit line structure and the dielectric wall;
[0013] Etching the sacrificial layer to form a first trench in the capacitor storage node window;
[0014] Depositing a first interlayer dielectric in the first trench, and etching back a portion of the first interlayer dielectric to form an I-shaped mask structure composed of the first interlayer dielectric in the capacitor storage node window;
[0015] Using the first interlayer dielectric as a mask, etching the sacrificial layer in the capacitor storage node window to form the insulating structure;
[0016] The insulating structure includes: a first interlayer dielectric deposited in the first trench and a sacrificial layer from below the I-shaped mask structure to above the substrate.
[0017] In one implementation of the present invention, the step of etching the sacrificial layer to form a first trench in the capacitor storage node window includes:
[0018] The sacrificial layer is dry-etched to form a first trench in the capacitor storage node window.
[0019] In one implementation of the present invention, the step of etching the sacrificial layer to form the first groove in the capacitor storage node window includes:
[0020] Depositing the sacrificial layer to cover the capacitor storage node window, the bit line structure and the dielectric wall, forming a second trench in the capacitor storage node window, wherein the size of the second trench is 20% to 60% of the spacing between two adjacent bit lines. ;
[0021] The bottom of the second trench, the top of the bit line structure and the sacrificial layer on the top of the dielectric wall are etched to form the first trench in the capacitor storage node window.
[0022] In one implementation of the present invention, the step of forming a plurality of bit line structures on a substrate includes:
[0023] A shallow trench isolation structure is formed in the substrate to isolate a plurality of active areas arranged at intervals;
[0024] A plurality of buried gate structures are formed in the active area, wherein a first doping region and a second doping region are formed on both sides of the buried gate structure;
[0025] A plurality of bit line structures are formed above the first doped region.
[0026] In one implementation of the present invention, the step of forming a plurality of dielectric walls on the substrate includes:
[0027] Depositing a second interlayer dielectric on the substrate and the bit line structure, wherein the upper surface of the second interlayer dielectric is higher than the height of the bit line structure;
[0028] Depositing a mask material layer on the second interlayer dielectric, patterning the mask material layer, and etching the second interlayer dielectric using the mask material layer;
[0029] Wherein, the dielectric wall intersects with the bit line structure.
[0030] In one implementation of the present invention, the step of etching back the conductive material layer to form capacitor contact node structures on both sides of the insulating structure includes:
[0031] The conductive material layer is etched back to keep the thickness of the conductive material layer at 30%-60% of the bit line height to form a capacitor contact node structure on both sides of the insulating structure, and the capacitor contact node structure is electrically connected to the second doped region.
[0032] In an implementation of the present invention, the second interlayer dielectric is silicon oxide, and the mask material layer is silicon nitride.
[0033] In one implementation of the present invention, in the step of depositing a sacrificial layer to cover the capacitor storage node window, the bit line structure and the dielectric wall, the thickness of the sacrificial material layer is 20%-40% of the distance between two adjacent bit lines.
[0034] In addition, in order to solve the problems of the prior art, the present invention also discloses a semiconductor structure, comprising:
[0035] Semiconductor substrate;
[0036] A shallow trench isolation structure is located in the semiconductor substrate to isolate a plurality of active areas arranged at intervals;
[0037] A plurality of buried gate structures are located in the active area, wherein the buried gate structures have a first doped region and a second doped region;
[0038] A bit line structure located above the first doped region;
[0039] A capacitor contact node structure, located above the second doped region;
[0040] The insulating structure is located above the shallow trench isolation structure and is used to isolate the adjacent capacitor contact node structures.
[0041] In one implementation of the present invention, the insulating structure includes a first interlayer dielectric layer and a sacrificial layer, the first interlayer dielectric layer has a T-shaped cross-section, the bottom of which is in contact with the shallow trench isolation structure, and the upper part extends to cover the bit line structure, and the sacrificial layer fills both sides of the T-shape to completely isolate the adjacent capacitor contact node structure.
[0042] In an implementation of the present invention, the height of the capacitor contact node structure is 30% to 60% of the height of the bit line structure.
[0043] As described above, in a semiconductor structure and a manufacturing method thereof of the present invention, multiple bit line structures and multiple dielectric walls are formed on a substrate, and the upper surface of the dielectric wall is higher than the upper surface of the bit line structure, and the dielectric wall extends to cover the part overlapping with the bit line structure to form a bit line structure that overlaps higher than the adjacent one, and an insulating structure is made in the capacitor storage node window surrounded by the bit line structure and the dielectric wall, so as to achieve the purpose of forming a separated capacitor storage node window; then a conductive material layer is deposited in the separated capacitor storage node window; and the conductive material layer is etched back to form a capacitor contact node structure. The insulating structure can directly avoid the problem of conductive material layer deposition such as short circuit between adjacent capacitor contact nodes, improve the yield of capacitor contact node structure manufacturing, thereby avoiding the problem of etching a thicker polysilicon layer between storage nodes in the prior art, which causes the etched pattern to easily produce deviations, thereby affecting the conductive characteristics of the circuit.
[0044] In addition, by depositing a sacrificial layer to cover the capacitor storage node window, the dielectric wall, and the adjacent bit line structure, and then etching the sacrificial layer to form a first groove in the capacitor storage node window, the size of the first groove and the size of the I-shaped mask can be controlled by controlling the thickness of the deposited sacrificial layer, thereby precisely controlling the size of the capacitor contact node structure.
[0045] Furthermore, mutually independent first trenches for storage contact nodes are formed by self-aligned dry etching and then filled with conductive material, thereby avoiding the NCS etching step of the prior art. Therefore, the problem of NCS etching is avoided and the difficulty of the process is reduced.
[0046] Furthermore, the mask structure formed by the adjacent bit line structures constitutes an I-shaped structure of silicon nitride and silicon oxide, which is beneficial to reducing the generation of parasitic capacitance. BRIEF DESCRIPTION OF THE DRAWINGS
[0047] Figure 1 It is a schematic flow chart of the semiconductor structure manufacturing method of the present invention.
[0048] Figure 2-1 A schematic top view of an embodiment of the present invention.
[0049] Figure 2-2 for Figure 2-1 AA surface cross-section shown.
[0050] Figure 2-3 for Figure 2-1 BB surface cross-section shown.
[0051] Figure 2-4 for Figure 2-1 The CC surface cross-section is shown.
[0052] Figure 3-1 A schematic top view of an embodiment of the present invention.
[0053] Figure 3-2 for Figure 3-1 AA surface cross-section shown.
[0054] Figure 3-3 for Figure 3-1 The CC surface cross-section is shown.
[0055] Figure 4 A schematic diagram of an embodiment of the present invention.
[0056] Figure 5 A schematic diagram of an embodiment of the present invention.
[0057] Figure 6 A schematic diagram of an embodiment of the present invention.
[0058] Figure 7-1 A schematic top view of an embodiment of the present invention.
[0059] Figure 7-2 for Figure 7-1 AA surface cross-section shown.
[0060] Figure 8-1 A schematic top view of an embodiment of the present invention.
[0061] Figure 8-2 for Figure 8-1 AA surface cross-section shown.
[0062] Figure 8-3 for Figure 8-1 BB surface cross-section shown.
[0063] Figure 8-4 for Figure 8-1 The CC surface cross-section is shown.
[0064] Figure 9-1 for Figure 8-1 The structure shown is a cross-sectional view of the AA plane after etching the sacrificial layer.
[0065] Figure 9-2 This is the BB cross-section corresponding to 9-A.
[0066] Figure 9-3 It is the CC cross-section corresponding to Figure 9-A.
[0067] Figure 10-1 A schematic top view of an embodiment of the present invention.
[0068] Figure 10-2 for Figure 10-1 AA surface cross-section shown.
[0069] Figure 10-3 for Figure 10-1 BB surface cross-section shown.
[0070] Figure 10-4 for Figure 10-1 The CC surface cross-section is shown.
[0071] Figure 11-1 It is a cross-sectional view of the BB surface corresponding to FIG10-A.
[0072] Figure 11-2 It is a cross-sectional view of the BB surface corresponding to FIG10-B.
[0073] Figure 11-3 It is a cross-sectional view of the CC surface corresponding to Figure 10-C.
[0074] Fig.12 A schematic top view of an embodiment of the present invention.
[0075] Fig.13 A schematic top view of an embodiment of the present invention.
[0076] Figure 14-1 for Fig.13 The AA surface section effect is shown.
[0077] Figure 14-2 for Fig.13 The BB surface cross-section effect is shown.
[0078] Figure 14-3 for Fig.13 The CC surface cross-section effect is shown.
[0079] Figure 15-1 for Fig.12 The AA surface section effect is shown.
[0080] Figure 15-2 for Fig.12 The BB surface cross-section effect is shown.
[0081] Figure 15-3 for Fig.12 The CC surface cross-section effect is shown.
[0082] Fig.16 The figure is a schematic diagram of the structure of an embodiment of the present invention.
[0083] Fig.17 The figure is a schematic diagram of the structure of an embodiment of the present invention. DETAILED DESCRIPTION
[0084] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.
[0085] See also Figure 1-Figure 17 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0086] It should be noted that as the geometric dimensions continue to decrease according to Moore's Law, the line width of the wire is getting shorter and shorter. In the process of making capacitor connection lines, due to factors such as the size of the through hole, the offset of the stacking (Overlay) between the photolithography mask and the substrate, and the improvement of the aspect ratio, the capacitor contact node formed after the etching step is prone to short circuits and open circuits after the subsequent conductive material is filled due to the transfer deviation of the pattern, which reduces the device yield. Based on this, an embodiment of the present invention provides a semiconductor structure and a method for making the same, which is used to improve the problems caused by the capacitor contact node structure in the semiconductor during the manufacturing process.
[0087] like Figure 1 As shown, an embodiment of the present invention provides a method for manufacturing a semiconductor structure, the method at least comprising:
[0088] S101, forming a plurality of bit line structures on a substrate.
[0089] It should be noted that the substrate includes a storage unit area, including a plurality of capacitor storage nodes, ie, capacitors for storing charge, and charge storage is achieved by connecting a circuit consisting of transistors and storage capacitors.
[0090] like Figure 2-1 As shown, it is a structural diagram of a storage unit area, where: Figure 2-2 for Figure 2-1 The cross-section along the AA direction is shown in Figure 2. Figure 2-3 for Figure 2-1 The cross-section along the BB direction is shown in Fig. Figure 2-4 for Figure 2-1 Cross-section along CC direction.
[0091] Specifically, Figure 2-1As shown, a plurality of bit line structures 220 in the horizontal direction and a plurality of word line structures 210 in the vertical direction are arranged alternately to form a plurality of capacitor storage node windows (not shown); Figure 2-2 In the cross-sectional view, for example, two bit line structures 220 (a first bit line structure 21 and a second bit line structure 22) are included; similarly, in Figure 2-3 In the cross-sectional view, for example, three bit line structures 220 are included. Figure 2-4 , which is a specific schematic diagram of each layer structure of the bit line structure from a CC perspective, for example, includes an insulating layer 230 , a bit line contact structure 250 , and a bit line metal structure 260 .
[0092] It is worth noting that in Figure 2-1 , Figure 2-2 , Figure 2-3 , Figure 2-4 The number of units (eg, bit line structures) in FIG. 1 is for illustration only and is not intended to limit the present invention.
[0093] For example, Figure 2-2 As shown, taking the first bit line structure 21 as an example, its storage node is two symmetrical transistor structures, the structures at both ends are the same, and the adjacent second bit line structure 22 has the same structure as the first bit line structure 21, and the embodiment of the present invention will not be described here.
[0094] like Figure 2-1 As shown, multiple bit line structures 220 and multiple word line structures 210 are interlaced to form multiple capacitor storage node windows (not shown). Specifically, a space region, i.e., a capacitor storage node window, can be formed (defined) between two adjacent bit line structures 220 and their corresponding two word line structures 210. The purpose of the present invention is to form a capacitor contact node structure in the space region to achieve data storage.
[0095] It is understandable that if Figure 2-2 As shown, a first bit line structure 21 is grown on the substrate 100, and the first bit line structure 21 may include: an insulating layer 230, a sidewall insulating layer 240, a bit line contact structure 250, and a bit line metal structure 260. The bit line contact structure 250 is formed on the substrate 100, the bit line metal structure 260 is formed on the bit line contact structure 250, the insulating layer 230 is formed on the bit line metal structure 260, and the sidewall insulating layer 240 is formed on the first bit line structure 21 ( Figure 2-1 220 in the bit line structure). Figure 2-2 The structure of the second bit line structure 22 is the same as that of the first bit line structure 21 , and the embodiment of the present invention will not be described in detail here.
[0096] Again, if Figure 2-2As shown, the substrate 100 may include: a shallow trench isolation structure 110, a buried word line structure 120 (ie, Figure 2-1 The shallow trench isolation structure 110 is used to isolate two identical storage node contact regions.
[0097] In the embodiment of the present invention, Figure 2-2 As shown, a specific method for forming a plurality of bit line structures 220 (a first bit line structure 21 and a second bit line structure 22) on a substrate 100 may include: forming a shallow trench isolation structure 110 in the substrate 100 to isolate a plurality of active regions 101 arranged at intervals; forming a plurality of buried gate structures 110 in the active region 101, wherein a first doping region 102 and a second doping region 103 are formed on both sides of the buried gate structure 110; forming a plurality of bit line structures above the first doping region 102, and the structure after formation is as shown in FIG. Figure 2-2 shown.
[0098] Step S102 , forming a plurality of dielectric walls on the substrate, wherein the upper surfaces of the dielectric walls are higher than the upper surfaces of the bit line structures, and the dielectric walls extend to cover the portions overlapping with the bit line structures.
[0099] Specifically, Figure 3-1 As shown in the top view, Figure 2-2 The two word line structures 210 of the shallow trench isolation structure 110 shown in the figure correspond to the upper deposited dielectric to form a first dielectric wall 301 and a second dielectric wall 302. The AA direction view is as shown in FIG. Figure 3-2 As shown, the CC direction view is as follows Figure 3-3 shown.
[0100] like Figure 3-1 and Figure 3-2 As shown, in which, in the top view Figure 3-1 The height of the two adjacent bit line structures 220 is lower than the height of the first dielectric wall 301 and the second dielectric wall 302, and the first dielectric wall 301 and the second dielectric wall 302 are cross-arranged with the bit line structure 220, so the materials on the first dielectric wall 301 and the second dielectric wall 302 can be formed on the top of the bit line structure 220.
[0101] S103, manufacturing an insulating structure in the capacitor storage node window surrounded by the bit line structure and the dielectric wall to form a separated capacitor storage node window.
[0102] like Figure 3-1 , Figure 3-2As shown, two adjacent bit line structures 220 and the first dielectric wall 301 and the second dielectric wall 302 above the corresponding word line can form a space region surrounded by four walls, which is a capacitor storage node window 400 as shown in the figure.
[0103] In an embodiment of the present invention, an insulating structure 203 is formed in the capacitor storage node window 400, such as Figure 4 As shown, when the subsequent capacitor contact node structure is manufactured, the capacitor storage node window 400 can be divided into two by the insulating structure 203 to form separate capacitor storage node windows 400 .
[0104] S104, depositing a conductive material layer in the separated capacitor storage node window.
[0105] like Figure 5 As shown, a conductive material layer 207 is deposited in the separated capacitor storage node windows 400 on both sides of the insulating structure 203. Specifically, for example, PECVD or other process technology is used to deposit the conductive material to avoid voids during filling. The material composition is, for example, polysilicon.
[0106] S105, etching back the conductive material layer to form capacitor contact node structures on both sides of the insulating structure.
[0107] Specifically, Figure 6 The figure shows a view after etching back the conductive material layer 207 along the AA direction, and the capacitor contact node structure 204 of the memory can be obtained by etching back the conductive material layer 207. In one implementation of the present invention, the etching gas used for etching back the conductive material layer is, for example, HBr / Cl2, and the thickness of the retained conductive material layer is 30%-60% of the height of the bit line structure 220.
[0108] Further explanation, the embodiment of the present invention also provides a specific step of manufacturing the insulating structure 203, which may include: forming a first insulating sidewall 410 of the first dielectric wall 301 and a second insulating sidewall 420 of the second dielectric wall; depositing a sacrificial layer 350 to cover the capacitor storage node window 400, the first bit line structure 21, the second bit line structure 22 and the first dielectric wall 301 and the second dielectric wall 302; etching the sacrificial layer 350 to form a first groove 440 in the capacitor storage node window 400; depositing a first dielectric wall 420 in the first groove 440; The interlayer dielectric 205 is formed by etching back a portion of the first interlayer dielectric 205 to form an I-shaped mask structure 206 composed of the first interlayer dielectric 205 in the capacitor storage node window 400; the sacrificial layer 350 in the capacitor storage node window 400 is etched using the first interlayer dielectric 205 as a mask to form the insulating structure 203; wherein the insulating structure 203 includes: the first interlayer dielectric 205 deposited in the first groove and the sacrificial layer 350 from below the I-shaped mask structure 206 to above the substrate.
[0109] Specifically, Figure 7-1 As shown, a first insulating side wall 410 is formed on both sides of the first dielectric wall 301, and a second insulating side wall 420 is formed on both sides of the second dielectric wall 302. The view along the AA direction is as shown in FIG. Figure 7-2 A first insulating sidewall 410 is made on both sides of the first dielectric wall 301, and a sacrificial layer 350 is deposited in the capacitor storage node window 400 formed by the second dielectric wall 302 and the corresponding two bit line structures 220. The effect after deposition is as shown in FIG. Figure 8-1 The top view shown, Figure 8-2 for Figure 8-1 The cross-section along the AA direction, Figure 8-3 for Figure 8-1 The cross-section along the BB direction, Figure 8-4 for Figure 8-1 Cross-section along the CC direction.
[0110] And understandably, Figure 8-1 What is shown is only the effect of depositing the sacrificial layer 350 in one of the capacitor storage node windows 400 . In actual process, the sacrificial layer 350 will be deposited in any capacitor storage node window 400 , and the deposited sacrificial layer 350 will extend and grow upward from the bottom of the capacitor storage node window 400 .
[0111] It should be noted that Figure 9-1 , Figure 9-2 , Figure 9-3 The diagrams shown are after etching and before etching. Figure 8-2 , Figure 8-3 , Figure 8-4Corresponding. First, a sacrificial layer 350 is deposited to cover the capacitor storage node window 400 and the first bit line structure 21 and the second bit line structure 22; then, the sacrificial layer 350 is etched to form a second groove 430 in the capacitor storage node window 400; and then the sacrificial layer 350 is etched, specifically, the sacrificial layer 350 at the bottom of the second groove 430, the top of each bit line structure and the top of each dielectric wall is etched to form the first groove 440 in the capacitor storage node window 400. In addition, the size of the second groove 430 is 20% to 60% of the spacing between two adjacent bit lines.
[0112] Then, if Figure 10-1 As shown, a first interlayer dielectric layer 205 is deposited in the first trench 440; and the sacrificial layer 350 in the capacitor storage node window 400 is completely etched. Figure 10-1 is a top view after the first interlayer dielectric layer 205 is deposited, and the view along the AA direction is as follows: Figure 10-2 As shown, a sacrificial layer 350 is deposited, such as Figure 10-1 The top view shown, Figure 10-2 for Figure 10-1 The cross-section along the AA direction, Figure 10-3 for Figure 10-1 The cross-section along the BB direction, Figure 10-4 for Figure 10-1 Cross-section along the CC direction.
[0113] It can be understood by those skilled in the art that after the first interlayer dielectric 205 is deposited in the first trench 440, the top view thereof is as follows: Figure 10-1 As shown, 10-2, Figure 10-3 , Figure 10-4 The schematic diagrams shown are 9-1, Figure 9-2 , Figure 9-3 The corresponding view after the first interlayer dielectric 205 is deposited and the corresponding attached layer is formed after etching. Figure 11-1 , Figure 11-2 , Figure 11-3 .
[0114] It can be understood that since the heights of the first bit line structure 21 and the second bit line structure 22 are lower than the first dielectric wall 301 and the second dielectric wall 302, and part of the first interlayer dielectric 205 is etched back, an I-shaped mask structure 206 composed of the first interlayer dielectric 205 is formed, wherein the I-shaped mask structure 206 is a top view of the upper half of the insulating structure 203.
[0115] As if looking down Fig.12As shown, the I-shaped mask structure 206 is then used as a mask to etch the sacrificial layer 350 in the capacitor storage node window 400 to form the insulating structure 203; therefore, from the above process, it can be obtained that the insulating structure 203 includes: the first interlayer dielectric 205 deposited in the first trench 440 and the sacrificial layer 350 from below the I-shaped mask structure 206 to above the substrate. Therefore, in the cross-sectional view of the insulating structure 203, the first interlayer dielectric 205 is a T-shaped structure, and the two lower half regions of the T are the materials corresponding to the sacrificial layer 350.
[0116] like Fig.13 The structure shown in FIG. 1 is formed after etching away the sacrificial layer 350, and then implanting a conductive material layer 207 along both sides of the insulating structure 203 to form a structure as shown in FIG. Figure 14-1 , Figure 14-2 , Figure 14-3 The structure shown in FIG. 1 is then etched back to retain the conductive material layer 207. Figure 6 Specifically, during the process of etching back the conductive material layer 207 , the thickness of the conductive material layer 207 is retained to be 30%-60% of the bit line height, so as to form the capacitor contact node structure 204 on both sides of the insulating structure 203 , and the capacitor contact node structure 204 is electrically connected to the storage node contact region 130 of the second doping region 103 .
[0117] Specifically, in the area formed by the deposited sacrificial layer 350 covering the capacitor storage node window 400, the adjacent bit line structure and the adjacent dielectric wall, the thickness of the sacrificial layer 350 on one side is 20%-40% of the distance between two adjacent bit lines, then the size of the formed first groove 440 is 20%-60% of the distance between two adjacent bit lines.
[0118] To form Fig.16 The dielectric wall structure shown in the figure, in one implementation of the present invention, comprises the following steps: depositing a second interlayer dielectric 310 on the substrate 100 and the bit line structure, wherein the upper surface of the second interlayer dielectric 310 is higher than the height of the bit line structure; depositing a mask material layer 320 on the second interlayer dielectric 310, and laying a layer of photoresist 330, such as Figure 15-1 , 15-2 As shown in FIG. 15-3, the mask material layer 320 is patterned through the photoresist 330, and the second interlayer dielectric 310 is etched using the mask material layer 320 to obtain Fig.16 The results are shown in Figure 1. Each bit line structure intersects with a dielectric wall, such as Fig.16In the embodiment, the second interlayer dielectric 310 is deposited on the sidewalls and top of the first bit line structure 21, and the mask material layer 320 is also deposited on the second interlayer dielectric 310 on the top of the first bit line structure 21. Therefore, for the first dielectric wall 301 or the second dielectric wall 302, it is composed of the second interlayer dielectric 310 and the mask material layer 320.
[0119] The material of the first interlayer dielectric 205 may be, for example, Si3N4, the second interlayer dielectric 310 may be SiO2, the mask material layer 320 may be Si3N4, and the sacrificial layer may be an oxide Oxi, specifically SiO2.
[0120] In addition, if Fig.17 As shown, an embodiment of the present invention further provides a semiconductor structure, including:
[0121] A semiconductor substrate 100;
[0122] A shallow trench isolation structure 110 is located in the semiconductor substrate 100 to isolate a plurality of active regions 101 arranged at intervals;
[0123] A plurality of buried gate structures 120 are located in the active area 100 , wherein the buried gate structures have a first doping region 102 and a second doping region 103 ;
[0124] A bit line structure located above the first doped region 102;
[0125] A capacitor contact node structure 204 is located above the second doped region 103. Specifically, the second doped region 103 is formed with a storage node contact region 130;
[0126] The insulating structure 203 is located above the shallow trench isolation structure 110 and is used to isolate the adjacent capacitor contact node structures 204 .
[0127] In one implementation, the insulating structure 203 includes a first interlayer dielectric layer 205 and a sacrificial layer 350. The first interlayer dielectric layer 205 has a T-shaped cross-section, with the bottom in contact with the shallow trench isolation structure 110 and the upper part extending to cover the bit line structure. The sacrificial layer fills both sides of the T-shape to completely isolate the adjacent capacitor contact node structure 204.
[0128] In one implementation, the height of the capacitor contact node structure 204 is 30% to 60% of the height of the bit line structure.
[0129] In a semiconductor structure and a manufacturing method thereof of the present invention, multiple bit line structures and multiple dielectric walls are formed on a substrate, and the upper surface of the dielectric wall is higher than the upper surface of the bit line structure, and the dielectric wall extends to cover the part overlapping with the bit line structure to form a bit line structure that overlaps higher than the adjacent one, and an insulating structure is made in the capacitor storage node window surrounded by the bit line structure and the dielectric wall to achieve the purpose of forming a separated capacitor storage node window; then a conductive material layer is deposited in the separated capacitor storage node window; and the conductive material layer is etched back to form a capacitor contact node structure. The insulating structure can directly avoid the problem of conductive material layer deposition such as short circuit between adjacent capacitor contact nodes, improve the yield of capacitor contact node structure manufacturing, and thus avoid the problem of etching a thicker polysilicon layer between storage nodes in the prior art, which causes the etched pattern to easily produce deviations, thereby affecting the conductive characteristics of the circuit.
[0130] In addition, by depositing a sacrificial layer to cover the capacitor storage node window, the dielectric wall, and the adjacent bit line structure, and then etching the sacrificial layer to form a first groove in the capacitor storage node window, the size of the first groove and the size of the I-shaped mask can be controlled by controlling the thickness of the deposited sacrificial layer, thereby precisely controlling the size of the capacitor contact node structure.
[0131] Furthermore, mutually independent first trenches for storage contact nodes are formed by self-aligned dry etching and then filled with conductive material, thereby avoiding the NCS etching step of the prior art. Therefore, the problem of NCS etching is avoided and the difficulty of the process is reduced.
[0132] Furthermore, the mask structure formed by the adjacent bit line structures constitutes an I-shaped structure of silicon nitride and silicon oxide, which is beneficial to reducing the generation of parasitic capacitance.
[0133] In summary, the semiconductor structure and the manufacturing method thereof provided by the present invention effectively overcome various shortcomings of the prior art and have high industrial utilization value.
[0134] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.
Claims
1. A method for manufacturing a semiconductor structure, characterized in that: The method at least comprises: forming a plurality of bit line structures on a substrate; forming a plurality of dielectric walls on the substrate, wherein the upper surface of the dielectric wall is higher than the upper surface of the bit line structure, and the dielectric wall extends to cover the portion overlapping with the bit line structure; Making an insulating structure in the capacitor storage node window surrounded by the bit line structure and the dielectric wall to form a separated capacitor storage node window; depositing a conductive material layer in the separated capacitor storage node window; The conductive material layer is etched back to form capacitor contact node structures on both sides of the insulating structure.
2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The step of making an insulating structure in the capacitor storage node window surrounded by the bit line structure and the dielectric wall includes: forming an insulating sidewall of the dielectric wall; Depositing a sacrificial layer to cover the capacitor storage node window, the bit line structure and the dielectric wall; Etching the sacrificial layer to form a first trench in the capacitor storage node window; Depositing a first interlayer dielectric in the first trench, and etching back a portion of the first interlayer dielectric to form an I-shaped mask structure composed of the first interlayer dielectric in the capacitor storage node window; Using the first interlayer dielectric as a mask, etching the sacrificial layer in the capacitor storage node window to form the insulating structure; The insulating structure includes: a first interlayer dielectric deposited in the first trench and a sacrificial layer from below the I-shaped mask structure to above the substrate.
3. The method for manufacturing a semiconductor structure according to claim 2, characterized in that: The step of etching the sacrificial layer to form a first trench in the capacitor storage node window comprises: The sacrificial layer is dry-etched to form a first trench in the capacitor storage node window.
4. The method for manufacturing a semiconductor structure according to claim 2, wherein: The step of etching the sacrificial layer to form the first trench in the capacitor storage node window comprises: Depositing the sacrificial layer to cover the capacitor storage node window, the bit line structure and the dielectric wall, and forming a second trench in the capacitor storage node window, wherein the size of the second trench is 20% to 60% of the spacing between two adjacent bit lines; The bottom of the second trench, the top of the bit line structure and the sacrificial layer on the top of the dielectric wall are etched to form the first trench in the capacitor storage node window.
5. The method for manufacturing a semiconductor structure according to claim 1, wherein: The step of forming a plurality of bit line structures on the substrate comprises: A shallow trench isolation structure is formed in the substrate to isolate a plurality of active areas arranged at intervals; A plurality of buried gate structures are formed in the active area, wherein a first doping region and a second doping region are formed on both sides of the buried gate structure; A plurality of bit line structures are formed above the first doped region.
6. The method for manufacturing a semiconductor structure according to claim 2, characterized in that: The step of forming a plurality of dielectric walls on the substrate comprises: Depositing a second interlayer dielectric on the substrate and the bit line structure, wherein the upper surface of the second interlayer dielectric is higher than the height of the bit line structure; Depositing a mask material layer on the second interlayer dielectric, patterning the mask material layer, and etching the second interlayer dielectric using the mask material layer; Wherein, the dielectric wall intersects with the bit line structure.
7. The method for manufacturing a semiconductor structure according to claim 1, wherein: The step of etching back the conductive material layer to form capacitor contact node structures on both sides of the insulating structure includes: The conductive material layer is etched back to keep the thickness of the conductive material layer at 30%-60% of the bit line height to form a capacitor contact node structure on both sides of the insulating structure, and the capacitor contact node structure is electrically connected to the second doped region.
8. The method for manufacturing a semiconductor structure according to claim 6, wherein: The second interlayer dielectric is silicon oxide, and the mask material layer is silicon nitride.
9. The method for manufacturing a semiconductor structure according to claim 2, wherein: In the step of depositing a sacrificial layer to cover the capacitor storage node window, the bit line structure and the dielectric wall, the thickness of the sacrificial material layer is 20%-40% of the distance between two adjacent bit lines.
10. A semiconductor structure, characterized in that: include: Semiconductor substrate; A shallow trench isolation structure is located in the semiconductor substrate to isolate a plurality of active areas arranged at intervals; A plurality of buried gate structures are located in the active area, wherein the buried gate structures have a first doped region and a second doped region; A bit line structure is located above the first doped region; the bit line structure comprises an insulating layer, a bit line contact structure and a bit line metal structure, the bit line contact structure is located on the substrate, the bit line metal structure is located on the bit line contact structure, and the insulating layer is located on the bit line metal structure; A capacitor contact node structure, located above the second doped region; The insulating structure is located above the shallow trench isolation structure and is used to isolate the adjacent capacitor contact node structures.
11. The semiconductor structure according to claim 10, characterized in that: The insulating structure includes a first interlayer dielectric layer and a sacrificial layer. The first interlayer dielectric layer has a T-shaped cross-section, the bottom of which is in contact with the shallow trench isolation structure, and the upper part extends to cover the bit line structure. The sacrificial layer fills both sides of the T-shape to completely isolate the adjacent capacitor contact node structure.
12. The semiconductor structure according to any one of claims 10 to 11, characterized in that: The height of the capacitor contact node structure is 30% to 60% of the height of the bit line structure.