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dma controller with cache management

A DMA controller and management function technology, applied in memory systems, instruments, electrical digital data processing, etc., can solve problems such as difficulty in meeting diversification, unusable CPU, and small product range

Active Publication Date: 2022-06-28
深圳市龙信信息技术有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

During this time, the CPU is unavailable for other work
[0003] Most of the DMA controllers in the prior art are customized settings, the applicable product range is small, and it is difficult to meet the diverse needs

Method used

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  • dma controller with cache management
  • dma controller with cache management

Examples

Experimental program
Comparison scheme
Effect test

Embodiment

[0041] A DMA controller with cache management capabilities, see figure 1 ,

[0042] The DMA controller is provided with several independent channels; the channels include a receiving channel and a sending channel, wherein the receiving channel is used to receive data on the application side and send it to the host side; the sending channel is used for receiving The data on the host side is sent to the application side;

[0043] The DMA controller is also used for the user to configure the number of channels enabled;

[0044] The channel is also connected to different peripherals, and the DMA controller is also used for the user to configure the burst length and data bit width of a single PCIE read and write access of the channel according to the peripherals connected to the channel.

[0045] Specifically, the data bit width can be set to 64 / 128 / 256 / 512 byte mode. The DMA controller provided in this embodiment supports multiple receive channels and transmit channels, for exa...

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PUM

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Abstract

In the DMA controller with cache management function provided by the present invention, the DMA controller is provided with several independent channels; the channels include a receiving channel and a sending channel, wherein the receiving channel is used to receive data from the application side , and send it to the host side; the sending channel is used to receive data from the host side and send it to the application side; the DMA controller is also used to configure the number of channels enabled by the user; the channel is also connected to different peripherals, DMA The controller is also used for the user to configure the burst length of a single PCIE read and write access of the channel according to the peripherals connected to the channel. The DMA controller is applicable to a wide range of products and has diversified functions.

Description

technical field [0001] The invention belongs to the technical field of DMA, in particular to a DMA controller with a cache management function. Background technique [0002] DMA (Direct Memory Access, Direct Memory Access) is an important feature of all modern computers, which allows hardware devices of different speeds to communicate without relying on the CPU's heavy interrupt load. Otherwise, the CPU needs to copy each piece of data from the source to the scratchpad, and then write them back to the new place again. During this time, the CPU is unavailable for other work. [0003] Most of the DMA controllers in the prior art are customized settings, the applicable product range is small, and it is difficult to meet diversified demands. SUMMARY OF THE INVENTION [0004] In view of the defects in the prior art, the present invention provides a DMA controller with a cache management function, which is applicable to a wide range of products and has diversified functions. ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F13/28G06F12/0866G06F8/65
CPCG06F13/28G06F12/0866G06F8/65
Inventor 王斌
Owner 深圳市龙信信息技术有限公司
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