Gate structure of transistor, semiconductor device and method for forming the same

Abstract

The semiconductor device includes a channel component of a transistor and a gate component disposed above the channel component. The gate component includes: a dielectric layer, a first work function metal layer disposed above the dielectric layer, a filling metal layer disposed above the first work function metal layer, and a second work function metal layer disposed above the filling metal layer. Embodiments of the present invention also relate to a gate structure of a transistor and a method for forming a semiconductor device.

Description

Technical Field

[0001] Embodiments of the present invention relate to a gate structure of a transistor, a semiconductor device and a method for forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced multiple generations of ICs, each with smaller and more complex circuits than the previous generation. In the course of IC development, functional density (i.e., the number of interconnected devices per chip area) has increased, while geometry size (i.e., the smallest component (or line) that can be produced using a manufacturing process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs. This scaling down also increases the complexity of processing and manufacturing ICs.

[0003] For example, as the process of device scaling down continues, resistance may become a greater problem. In conventional IC devices, it may be difficult to reduce gate contact resistance. Therefore, the performance of conventional IC devices has not been optimized. Summary of the invention

[0004] Some embodiments of the present invention provide a semiconductor device, comprising: a channel component of a transistor; and a gate component disposed above the channel component, wherein the gate component comprises: a dielectric layer; a first work function metal layer disposed above the dielectric layer; a filling metal layer disposed above the first work function metal layer; and a second work function metal layer disposed above the filling metal layer.

[0005] Still other embodiments of the present invention provide a gate structure of a transistor, comprising: a gate dielectric layer; a first work function metal layer located above the gate dielectric layer; a filling metal layer located above the first work function metal layer, wherein the filling metal layer includes a U-shaped groove; and a second work function metal layer located in the U-shaped groove; wherein the upper surface of the filling metal layer is higher than the first work function metal layer and the second work function metal layer.

[0006] Still other embodiments of the present invention provide a method for forming a semiconductor device, comprising: forming a gate dielectric layer; depositing a first work function metal layer over the gate dielectric layer; depositing a filling metal layer over the first work function metal layer, wherein the filling metal layer defines a concave groove; depositing a second work function metal layer in the concave groove; forming a dielectric material over the first work function metal layer, the filling metal layer, and the second work function metal layer; etching an opening through the dielectric material, wherein the opening exposes the upper surface and side surfaces of multiple segments of the filling metal layer; and filling the opening with a conductive gate contact, wherein the multiple segments of the filling metal layer protrude vertically into the conductive gate contact. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustration purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 is a perspective view of a FinFET device according to various aspects of the present invention.

[0009] Figures 2 to 4 is a schematic three-dimensional perspective view of a portion of a semiconductor device at various stages of fabrication in accordance with various aspects of the present invention.

[0010] Figures 5 to 17 are schematic cross-sectional side views of a portion of a semiconductor device at various stages of fabrication in accordance with various aspects of the present invention.

[0011] Fig.18 is a flow chart of a method of manufacturing a semiconductor device according to various aspects of the present invention. DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0013] In addition, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not in itself indicate the relationship between the various embodiments and / or configurations discussed. In addition, in the following present invention, forming a component on another component, connecting to and / or coupling to another component may include embodiments in which the components are formed in a direct contact manner, and may also include embodiments in which additional components are inserted between components so that the components may not be in direct contact. In addition, spatial relative terms, such as, "lower", "upper", "horizontal", "vertical", "above", "above", "below", "below", "under", "up", "down", "top", "bottom", etc. and their derivatives (e.g., "horizontally", "downwardly", "upwardly", etc.) are used to facilitate the description of the relationship between one component of the present invention and another component. Spatial relative terms are intended to cover different orientations of devices including components. Further, when "about", "approximately", etc. are used to describe a numerical value or a numerical range, the term is intended to cover a numerical value within a reasonable range including the described numerical value, such as within + / -10% of the described numerical value or other values ​​understood by those skilled in the art. For example, the term "about 5 nm" encompasses a size range from 4.5 nm to 5.5 nm.

[0014] Certain aspects of the present invention generally relate to semiconductor devices, and more specifically to field effect transistors (FETs), such as planar FETs or three-dimensional fin-line FETs (FinFETs). FinFETs are used as examples to illustrate an embodiment of the present invention, but it is understood that the present invention is also applicable to non-FinFET planar devices unless otherwise explicitly required.

[0015] refer to Figure 1 , a perspective view of an exemplary FinFET device 10 is shown. The FinFET device structure 10 includes an N-type FinFET device structure (NMOS) 15 and a P-type FinFET device structure (PMOS) 25. The FinFET device structure 10 includes a substrate 102. The substrate 102 may be made of silicon or other semiconductor materials. Alternatively or additionally, the substrate 102 may include other elemental semiconductor materials such as germanium. In some embodiments, the substrate 102 is made of a compound semiconductor such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide. In some embodiments, the substrate 102 is made of an alloy semiconductor such as silicon germanium, silicon germanium carbide, gallium arsenide phosphide, or gallium indium phosphide. In some embodiments, the substrate 102 includes an epitaxial layer. For example, the substrate 102 may include an epitaxial layer located above the bulk semiconductor.

[0016] The FinFET device structure 10 also includes one or more fin structures 104 (e.g., Si fins) extending from the substrate 102 in the Z direction and surrounded by a spacer 105 in the Y direction. The fin structure 104 is elongated in the X direction and may optionally include germanium (Ge). The fin structure 104 may be formed using appropriate processes such as photolithography and etching processes. In some embodiments, the fin structure 104 is etched from the substrate 102 using a dry etch or plasma process. In some other embodiments, the fin structure 104 may be formed by a plurality of patterning lithography processes, such as a double patterning lithography (DPL) process. DPL is a method of constructing a pattern on a substrate by dividing the pattern into two staggered patterns. DPL allows for enhanced density of components (e.g., fins). The fin structure 104 also includes an epitaxially grown material 12, which may be used (together with a portion of the fin structure 104) as a source / drain of the FinFET device structure 10.

[0017] An isolation structure 108, such as a shallow trench isolation (STI) structure, is formed to surround the fin structure 104. In some embodiments, a lower portion of the fin structure 104 is surrounded by the isolation structure 108, and an upper portion of the fin structure 104 protrudes from the isolation structure 108, such as Figure 1 In other words, a portion of the fin structure 104 is embedded in the isolation structure 108. The isolation structure 108 prevents electrical interference or crosstalk.

[0018] The FinFET device structure 10 also includes a gate stack structure including a gate electrode 110 and a gate dielectric layer (not shown) located below the gate electrode 110. The gate electrode 110 may include polysilicon or a metal. The metal includes tantalum nitride (TaN), nickel silicon (NiSi), cobalt silicon (CoSi), molybdenum (Mo), copper (Cu), tungsten (W), aluminum (Al), cobalt (Co), zirconium (Zr), platinum (Pt) or other applicable materials. The gate electrode 110 may be formed in a gate-last process (or a gate replacement process). Hard mask layers 112 and 114 may be used to define the gate electrode 110. One or more dielectric layers 115 may also be formed on the sidewalls of the gate electrode 110 and above the hard mask layers 112 and 114. In at least one embodiment, the dielectric layer 115 may be in direct contact with the gate electrode 110. One or more dielectric layers 115 may be patterned to form gate spacers.

[0019] The gate dielectric layer (not shown) may include a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, a dielectric material having a high dielectric constant (high-k), or a combination thereof. Examples of high-k dielectric materials include hafnium oxide, zirconium oxide, aluminum oxide, hafnium dioxide-aluminum oxide aluminum alloy, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, or the like, or a combination thereof.

[0020] In some embodiments, the gate stack structure includes additional layers, such as an interface layer, a capping layer, a diffusion / barrier layer, or other applicable layers. In some embodiments, the gate stack structure is formed over a central portion of the fin structure 104. In some other embodiments, multiple gate stack structures are formed over the fin structure 104. In some other embodiments, the gate stack structure includes a dummy gate stack and is later replaced by a metal gate (MG) after performing a pre-high thermal budget process.

[0021] The gate stack structure is formed by a deposition process, a photolithography process and an etching process. The deposition process includes chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma CVD (HDPCVD), metal organic CVD (MOCVD), remote plasma CVD (RPCVD), plasma enhanced CVD (PECVD), plating, other suitable methods and / or combinations thereof. The photolithography process includes photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, developing photoresist, rinsing, drying (e.g., hard baking). The etching process includes a dry etching process or a wet etching process. Optionally, the photolithography process can be implemented or replaced by other suitable methods such as maskless lithography, electron beam writing and ion beam writing.

[0022] Figures 2 to 4 2 is a schematic partial three-dimensional perspective view of a portion of a semiconductor device 200 at various stages of manufacture. In some embodiments, the semiconductor device 200 may be implemented as described above with reference to Figure 1 The FinFET device 10 discussed is a FinFET device. Figure 2 , the semiconductor device 200 may include a PMOS region 210 and an NMOS region 220 located away from the PMOS region 210. Both the PMOS region 210 and the NMOS region 220 are formed over a substrate 230, which may be Figure 1 In some embodiments, the substrate 230 includes a silicon substrate. The PMOS region 210 and the NMOS region 220 also include an isolation structure 240 formed above the substrate 230. The isolation structure 240 may be Figure 1 In some embodiments, the isolation structure 240 may include shallow trench isolation (STI).

[0023] The fin structure 250 may protrude vertically upward from the substrate 230 in the Z direction. The fin structure 250 may be Figure 1 In some embodiments, the fin structure 250 may include a silicon material. An epitaxial layer 270 is grown on the fin structure 250. The epitaxial layer 270 may be Figure 1 2. In some embodiments, the epitaxial layer 270 in the PMOS region 210 may include SiGe, while the epitaxial layer in the NMOS region 220 may include Si. Layers 280 and 290 may also be formed over the epitaxial layer 270. As non-limiting examples, the layers 280 and 290 may include layers such as silicide layers, etch stop layers, passivation layers, etc.

[0024] The dummy gate structure 300 is formed to wrap around the fin structure 250, for example in a manner similar to that in which the gate electrode 110 wraps around the fin structure 104. The dummy gate structure 300 may include a dummy gate electrode, such as a polysilicon gate electrode. Gate spacers 310 are formed on the sidewalls of each dummy gate structure 300. In some embodiments, the gate spacers 310 may include one or more dielectric materials, such as silicon nitride, silicon nitride carbon (SiCN), silicon oxynitride carbon (SiCON), or a suitable low-k dielectric material. An interlayer dielectric (ILD) 350 is formed over the isolation structure 240. In some embodiments, the ILD 350 includes a low-k dielectric material, such as a dielectric material having a dielectric constant of less than about 4. Portions of the ILD 350 are disposed between (or provide electrical isolation between) the dummy gate structures 300.

[0025] Reference now Figure 3 , a dummy gate removal process 370 is performed on the semiconductor device 200 to remove the dummy gate structure 300. In some embodiments, the dummy gate removal process 370 includes one or more etching processes configured to have etching selectivity between the dummy gate structure 300 and other components of the semiconductor device 200. For example, one or more etching processes can be configured to have a greater polysilicon etching rate than other materials, so that the polysilicon material of the dummy gate structure 300 can be removed without substantially removing other components of the semiconductor device 200. Due to the implementation of the dummy gate removal process 370, an opening 380 is formed at the location of the removed dummy gate structure 300.

[0026] Reference now Figure 4, one or more layers 400 are formed over the ILD 350 and in the opening 380. The one or more layers 400 may be formed by one or more deposition processes, such as CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, or a combination thereof. In some embodiments, the one or more layers 400 may include an interfacial layer (IL) and a gate dielectric layer formed over the IL. In some embodiments, the IL may include silicon oxide, and the gate dielectric layer may include a high-k dielectric material (e.g., a material having a dielectric constant greater than about 4). In other embodiments, the IL or the gate dielectric layer may include an oxide material including Si, Hf, Zr, Pb, Sb, or La, or a nitride material including Si, Hf, Zr, Pb, Sb, or La.

[0027] Figures 5 to 15 and Fig.17 is a schematic partial cross-sectional side view of a portion of a semiconductor device 200 along an XZ plane to illustrate various process steps implemented to form a gate electrode according to various aspects of the present invention. Figure 4 The cross-sectional cut is taken at the position of the cutting line AA' shown, which is aligned with the channel region of the transistor of the semiconductor device 200. Since the cutting line AA' extends in the X direction, Figures 5 to 15 and Fig.17 It may also be called an X-cut diagram. For reasons of consistency and clarity, Figure 4 Similar components appear in Figures 5 to 15 and Fig.17 It should also be understood that for simplicity reasons, Figures 5 to 15 and Fig.17 The process steps for forming the gate structure of a PMOS transistor are shown. However, the process steps for forming the gate structure of an NMOS transistor may be substantially similar, except that p-type metal is formed in the PMOS transistor and n-type metal is formed in the NMOS transistor, or vice versa, as discussed in more detail below.

[0028] exist Figure 5 At the manufacturing stage shown, one or more layers 400 are formed in the opening 380. Sides of the one or more layers 400 are formed on the sidewalls of the gate spacer 310. The bottom of the one or more layers 400 is formed over the isolation structure 240 and over the channel region 250A (e.g., a portion of the fin structure 250). Figure 5 The X-cut is taken at the channel region 250A, so Figure 5 The bottom of one or more layers 400 formed above the channel region 250A is shown. Figure 5 X-cut, then Figure 5The bottom of one or more layers 400 disposed over isolation structure 240 will be shown.

[0029] Reference now Figure 6 , a deposition process 420 is performed to form a metal layer 430 over one or more layers 400 in the opening 380. The metal layer 430 may be a p-type work function metal for adjusting the threshold voltage (Vt) of the metal gate electrode. In some embodiments, the metal layer 430 includes TiN. In other embodiments, the metal layer 430 may include a nitride material of Ti, Ta, Cr, Ni, Mo, Cu, Zr, Zn, Fe, or Sn, or an oxide material of Ti, Ta, Cr, Ni, Mo, Cu, Zr, Zn, Fe, and / or Sn. The process parameters of the deposition process 420 are also configured to control the thickness 440 of the deposited metal layer 430. In some embodiments, the thickness 440 is in a range between about 0 angstroms and about 30 angstroms. Such a thickness range allows the metal layer 430 to fully adjust the threshold voltage without occupying too much space / spacing of the gate electrode.

[0030] Reference now Figure 7 , a deposition process 450 is performed to form a metal layer 460 (also referred to as a fill metal) over the metal layer 430 in the opening 380. The metal layer 460 may include a metal material and will be used as the main conductive portion of the metal gate electrode. In some embodiments, the metal layer 460 includes W. In other embodiments, the metal layer 460 may include Cu, Co, or Al. The process parameters of the deposition process 450 are also configured to control the thickness 470 of the deposited metal layer 460. For example, since the metal layer 460 will be used as the main conductive portion of the metal gate electrode, the thickness 470 is configured to be significantly greater than the thickness 440 of the metal layer 430 (e.g., at least several times greater). In some embodiments, the thickness 470 is in a range between about 50 angstroms and about 300 angstroms. Such a thickness range allows the metal layer 460 to be fully used as the main conductive portion of the gate electrode, and it still saves some space for forming other work function metal layers.

[0031] Note that metal layer 460 has a concave cross-sectional profile. In some embodiments, the concave cross-sectional profile may resemble the letter "U". Such a "U-shaped" cross-sectional profile is obtained because the filling metal layer 460 is not formed to completely fill the opening 380. For example, the bottom of the filling metal layer 460 is formed above the upper surface of the metal layer 430, and the side of the filling metal layer 460 is formed on the sidewall of the metal layer 430, and the opening 380 is located between the side of the filling metal layer 460. Therefore, a concave groove is defined by the bottom and side of the metal layer 460.

[0032] Due to the unique manufacturing process flow of the present invention, the "U-shaped" cross-sectional profile of the fill metal layer 460 is different from the conventional fill metal layer of the gate electrode. For example, in conventional semiconductor devices, the fill metal layer does not define a concave groove, but can present an "I"-shaped cross-sectional profile, and in conventional devices, no additional work function metal layer is formed above the fill metal layer. Compared with conventional devices, the "U"-shaped cross-sectional profile of the fill metal layer 460 reduces the contact resistance because the "U-shape" effectively allows a larger surface contact area with the conductive gate contact to be formed above the side of the fill metal layer 460. In other words, although the "I"-shaped profile of conventional devices allows a single protruding member of the fill metal layer to contact the gate contact, the "U-shaped" profile of the fill metal layer 460 here allows multiple (e.g., two) protruding members to contact the gate contact, which effectively increases the surface contact area and thus reduces the gate contact resistance.

[0033] In addition, compared with conventional devices, the filling metal layer 460 here has improved gap filling performance, because Figure 7 During this manufacturing stage shown (which is already in the conventional manufacturing process flow), the gap (opening 380) that is filled is wider. In other words, since all the work function metal layers have been formed before the filling metal is deposited, the last step in a conventional device is to form the filling metal. Therefore, the filling metal will have to fill a relatively small / narrow opening, which places strict requirements on the gap filling performance of the filling metal. In contrast, the filling metal layer 460 here is formed as an intermediate step and before some work function metal is deposited. Therefore, the requirements for the gap filling of the filling metal layer 460 are not as strict because the opening 380 is still relatively wide at this manufacturing stage.

[0034] Reference now Figure 8, a deposition process 490 is performed to form a metal layer 500 over the metal layer 460 in the opening 380. The metal layer 500 may be another p-type work function metal for adjusting the threshold voltage (Vt) of the metal gate electrode. In some embodiments, the metal layer 500 includes TiN. In other embodiments, the metal layer 500 may include a nitride material of Ti, Ta, Cr, Ni, Mo, Cu, Zr, Zn, Fe, or Sn, or an oxide material of Ti, Ta, Cr, Ni, Mo, Cu, Zr, Zn, Fe, and / or Sn. The process parameters of the deposition process 490 are also configured to control the thickness 510 of the deposited metal layer 500. In some embodiments, the thickness 510 is in a range between about 0 angstroms and about 30 angstroms. In some embodiments, the ratio between the thickness 440, the thickness 470, and the thickness 510 is in a range between about 0:1:0 and about 1:10:1. This thickness range of metal layer 500 and ratio range of thicknesses 440 / 470 / 510 are configured to allow metal layers 430 and 500 to adequately adjust the threshold voltage without occupying too much space / space of the gate electrode.

[0035] Reference now Fig. 9 , a deposition process 530 is performed to form a metal layer 540 above the metal layer 500 in the opening 380. The metal layer 540 may be an n-type work function metal for adjusting the threshold voltage (Vt) of the metal gate electrode. In some embodiments, the metal layer 540 includes TiAl. In other embodiments, the metal layer 540 may include an alloy material made of Ti, Al, Ta, Zr and / or Zn. The process parameters of the deposition process 530 are also configured to control the thickness 550 of the deposited metal layer 540. In some embodiments, the thickness 550 is in the range between about 0 angstroms and about 30 angstroms. Such a thickness range allows the metal layer 540 to fully adjust the threshold voltage without occupying too much space / spacing of the gate electrode. It should be understood that in some embodiments, the formation of the metal layer 540 is optional, which means that it can be omitted without substantially affecting the performance of the semiconductor device 200.

[0036] Reference now Fig.10, a deposition process 560 is performed to form a metal layer 570 over the metal layer 540 in the opening 380. The metal layer 570 may be another p-type work function metal for adjusting the threshold voltage (Vt) of the metal gate electrode. In some embodiments, the metal layer 570 includes TiN. In other embodiments, the metal layer 570 may include a nitride material of Ti, Ta, Cr, Ni, Mo, Cu, Zr, Zn, Fe, or Sn, or an oxide material of Ti, Ta, Cr, Ni, Mo, Cu, Zr, Zn, Fe, and / or Sn. The metal layer 570 may substantially fill the opening 380. It should be understood that one or more planarization processes (e.g., chemical mechanical polishing (CMP)) may be performed on the semiconductor device 200 to planarize or level the upper surfaces of the various layers 400, 430, 460, 500, 540, and 570.

[0037] In the above-described embodiment, a p-type work function metal layer (e.g., metal layer 430) is formed before the fill metal layer 460, and two other p-type work function metal layers (e.g., metal layers 500 and 570) and an n-type work function metal layer (e.g., metal layer 540) are formed after the fill metal layer 460. However, this is only a non-limiting example. In other embodiments, other configurations may be adopted. For example, two p-type work function metal layers (instead of one) may be formed before the fill metal layer 460. As another example, the fill metal layer 460 may be formed before all the work function metal layers. As yet another example, a plurality of fill metal layers may be formed, wherein one or more work function metal layers are formed between the plurality of fill metal layers. The material composition of the work function metal layers (even if they are of the same type, e.g., all p-type metal layers) may also be configured to be different from one another. Advantageously, since the threshold voltage may vary as a function of the material composition of the work function metal layer or the distance of the work function metal layer from the channel, these different types of configurations may flexibly adjust the threshold voltage.

[0038] It should also be understood that although the embodiments discussed above show the formation of a gate structure for PMOS, similar process steps can be implemented to form a gate structure for NMOS, but the type of work function metal layer is flipped. For example, although the work function metal layers 430, 500 and 570 are p-type work function metal layers for PMOS, they can be n-type work function metal layers for NMOS.

[0039] Reference now Fig.11, one or more etching processes 600 are performed on the semiconductor device 200. The one or more etching processes 600 may include an etch back process, wherein there may be an etching selectivity between the gate spacer 310, the one or more layers 400, and the metal layers 430, 460, 500, 540, and 570. For example, the metal layers 430, 500, and 540 may have a much greater etching rate than the one or more layers 400, the filling metal layer 460, and the gate spacer 310. In some embodiments, for the gate spacer 310, the etching rate is the slowest, the etching rate of the metal layer 460 is greater than the etching rate of the gate spacer 310, the etching rate of the one or more layers 400 is greater than the etching rate of the metal layer 460, and the etching rate of the metal layers 430, 500, 540, and 570 is greater than the etching rate of the one or more layers 400. Due to the different etching rates, the various layers at this manufacturing stage have different heights, for example, the height of the filling metal layer 460 is significantly greater than the height of the metal layers 430, 500, 540, and 570. Reference will be made to Fig.15 Also due to the one or more etching processes 600, openings 620 are formed. One or more layers 400 may serve as a gate dielectric (and optionally IL) of a gate structure, and metal layers 430, 460, 500, 540, and 570 may collectively serve as a metal gate electrode of the gate structure.

[0040] Reference now Fig.12 , a deposition process 640 is performed on the semiconductor device 200 to fill the opening 620 with a layer 650. The layer 650 may also be referred to as a self-aligned contact (SAC) layer. In some embodiments, the layer 650 includes a dielectric material such as SiN, silicon carbide (SiC), SiOCN, or a metal oxide material. A planarization process such as a CMP process may be performed after the deposition process 640 to planarize the upper surface of the layer 650.

[0041] Reference now Fig.13 , a gate contact etching process 670 is performed on the semiconductor device 200 to partially remove the layer 650, thereby forming an opening 680 at the location of the removed portion of the layer 650. The gate contact etching process 670 may include one or more photolithography processes that form a patterned photomask (or a patterned hard mask formed using a patterned photomask) that defines the location and size of the opening 680. At this stage of manufacturing, the upper surfaces of the metal layers 430, 460, 500, 540, and 570 are exposed by the opening 680. The side surfaces of the metal layer 460 are also partially exposed by the opening 680.

[0042] Reference now Fig.14, a gate contact deposition process 690 is performed on the semiconductor device 200 to form a conductive gate contact 700 in the opening 680. In some embodiments, the gate contact deposition process 690 deposits one or more metal materials or alloys thereof as the conductive gate contact 700. The conductive gate contact 700 provides an electrical connection to a metal gate electrode (e.g., including metal layers 430, 460, 500, 540, and 570).

[0043] As described above, one of the unique physical characteristics of the present invention is the "U" shaped cross-sectional profile defined by the fill metal layer 460. This profile is achieved due to the fact that the fill metal layer 460 is formed earlier in the manufacturing process flow of the present invention than in conventional devices. For example, while conventional devices may form the fill metal layer after all work function metal layers have been formed, the present invention forms the fill metal layer 460 after forming the work function metal layer 430 but before forming the work function metal layers 500, 540 and 570. Therefore, the work function metal layers 500, 540 and 570 are formed within the concave grooves defined by the fill metal layer 460.

[0044] Likewise Fig.14 As shown, the side portions 460A and 460B of the fill metal layer 460 protrude vertically above the work function metal layers 430, 500, 540 and 570. In other words, the uppermost surface of the fill metal layer 460 is located above the uppermost surface of the work function metal layers 430, 500, 540 and 570 (in the Z direction). The conductive gate contact 700 is in physical contact with multiple side portions 460A and 460B, rather than with only one protruding portion of the fill metal layer in a conventional device. Due to the larger surface contact area (e.g., the side portions 460A and 460B here relative to a single portion of the fill metal layer in a conventional device), the gate structure of the present invention provides reduced contact resistance, which helps to improve device performance.

[0045] Fig.15Dimensions of various layers of the semiconductor device 200 are shown. For example, the conductive gate contact 700 has a vertical dimension or height 810 measured from its uppermost surface to its lowermost surface in the Z direction. The metal layer 430 has a vertical dimension or height 820 measured from its uppermost surface to the lowermost surface of one or more layers 400 in the Z direction. One or more layers 400 have a vertical dimension or height 830 measured from its uppermost surface to its lowermost surface in the Z direction. The metal layer 460 has a vertical dimension or height 840 measured from its uppermost surface to the lowermost surface of one or more layers 400 in the Z direction. The gate spacer 310 has a vertical dimension or height 850 measured from its uppermost surface to its lowermost surface in the Z direction. According to an embodiment of the present invention, height 850>height 840>=height 830>height 820>height 810. In other words, each of the gate spacers 310 and the layer 650 has a higher upper surface (e.g., higher in the Z direction) than the fill metal layer 460, and the fill metal layer 460 has a higher upper surface than the metal layers 430, 500, 540, and 570. The relative heights of the various layers herein allow the fill metal layer 460 to protrude vertically into the conductive gate contact 700, which helps to reduce gate contact resistance as described above.

[0046] Meanwhile, metal layer 460 has a lateral dimension or width 860 measured from its "leftmost" surface to its "rightmost" surface in the X direction. Conductive gate contact 700 has a lateral dimension or width 870 measured from its "leftmost" surface to its "rightmost" surface in the X direction. One or more layers 400 have a lateral dimension or width 880 measured from its "leftmost" surface to its "rightmost" surface in the X direction. According to an embodiment of the present invention, width 880>width 870>=width 860. The relative widths of the various layers herein are a natural result of the manufacturing process implemented herein.

[0047] although Fig.15 The XZ plane (eg, along Figure 4 The cross-sectional view of the semiconductor device 200 is shown in FIG. Fig.16 The YZ plane (eg, along Figure 4 FIG. 2 is a cross-sectional view of the semiconductor device 200 taken along a plane BB' cut as shown in FIG. Fig.16As shown, the channel region 250A of the fin structure 250 protrudes vertically upward in the Z direction, and various layers 400, 430, 460, 500, 540 and 570 are formed over the fin structure 250 and wrap the fin structure 250. A conductive gate contact 700 is formed over the metal layer 570. Furthermore, one or more layers 400 may serve as the IL and the gate dielectric of the gate structure, and the metal layers 430, 460, 500, 540 and 570 may collectively serve as the metal gate electrode of the gate structure.

[0048] although Figures 14 to 16 A "long channel" embodiment of semiconductor device 200 is shown, but Fig.17 A "short channel" embodiment of the semiconductor device 200 is shown. For the "short channel" embodiment, the semiconductor device 200 has a shortened channel 250B in the X direction compared to the "long channel" embodiment. Due to the shortened channel 250B, the gate spacer 310 is formed to have a "wide top and narrow bottom" profile, which means that the opening it defines is wider at the top and narrower at the bottom. One or more layers 400 and a metal layer 430 are subsequently formed to partially fill such an opening, but the "wide top and narrow bottom" profile is mostly retained. When a fill metal layer 460 is formed in the opening, the narrower bottom of the opening causes the fill metal layer 460 to substantially fill the bottom of the opening, but not the top. Therefore, the bottom 460C of the fill metal layer 460 has an "I" shape. In other words, the shape of the bottom 460C is similar to a vertical protruding bar.

[0049] At the same time, the top of fill metal layer 460 is shaped like the letter "U" in which vertically extending segments 460A and 460B are connected together by horizontally extending segment 460D. In other words, the shape of fill metal layer 460 is similar to a fork or goal post in an American football. The top of fill metal layer 460 (including segments 460A, 460B, and 460D) defines an opening in which metal layers 500, 540, and 570 are formed. Since the top of fill metal layer 460 still has multiple "fingers" (e.g., segments 460A-460B) that are in physical contact with conductive gate contact 700, Fig.17 The "short channel" embodiment shown still achieves reduced gate contact resistance.

[0050] Fig.18 9 is a flow chart showing a method 900 for manufacturing a semiconductor device according to another embodiment of the present invention. The method 900 includes a step 910 of forming a gate dielectric layer.

[0051] The method 900 includes a step 920 of depositing a first work function metal layer over the gate dielectric layer.

[0052] The method 900 includes depositing a fill metal layer over the first work function metal layer 930. The fill metal layer defines a concave groove.

[0053] The method 900 includes a step 940 of depositing a second work function metal layer in the concave recess.

[0054] The method 900 includes a step 950 of forming a dielectric material over the first work function metal layer, the fill metal layer, and the second work function metal layer.

[0055] The method 900 includes etching an opening through the dielectric material 960. The opening exposes the upper surface and side surfaces of the plurality of segments of the fill metal layer.

[0056] The method 900 includes a step 970 of filling the opening with a conductive gate contact. A plurality of segments of the fill metal layer protrude vertically into the conductive gate contact.

[0057] In some embodiments, depositing a first work function metal layer and depositing a second work function metal layer include: depositing a p-type work function metal layer as the first work function metal layer, and depositing an n-type work function metal layer as the second work function metal layer; or depositing an n-type work function metal layer as the first work function metal layer, and depositing a p-type work function metal layer as the second work function metal layer.

[0058] In some embodiments, depositing the fill metal layer is performed such that at least a portion of the fill metal layer has a U-shaped cross-sectional profile.

[0059] It should be understood that additional steps may still be implemented before, during, or after the above steps 910-970. For example, method 900 may include the following steps: after depositing the second work function metal layer and before forming the dielectric material: etching the first work function metal layer, the filling metal layer, and the second work function metal layer, wherein the filling metal layer is etched at a slower etching rate than the first work function metal layer and the second work function metal layer, so that multiple segments of the filling metal layer protrude above the first work function metal layer and the second work function metal layer. As another example, method 900 may include the following steps: depositing a third work function metal layer above the filling metal layer, wherein the second work function metal layer is deposited above the third work function metal layer; and depositing a fourth work function metal layer above the second work function metal layer; wherein the second work function metal layer and the third work function metal layer partially fill the concave groove defined by the filling metal layer, and wherein the fourth work function metal layer completely fills the concave groove defined by the filling metal layer. As another example, method 900 may include the following steps: before forming a gate dielectric layer: forming a fin structure comprising a semiconductor material; forming a dummy gate structure wrapping the fin structure, wherein the dummy gate structure includes a dummy gate electrode and a gate spacer formed on the sidewall of the dummy gate electrode; and removing the dummy gate electrode to form a trench at least partially defined by the gate spacer, wherein the gate dielectric layer is formed to partially fill the trench.

[0060] Based on the above discussion, the present invention introduces a novel scheme for forming a metal gate electrode. The present invention forms a work function metal layer before at least some work function metal layers, rather than forming all work function metal layers before the fill metal layer. Due to the novel manufacturing scheme, the fill metal layer of the present invention has a "U-shaped" cross-sectional profile. For example, the fill metal layer can have a plurality of vertically protruding "fingers" that protrude into the conductive gate contact.

[0061] The gate electrode of the present invention provides several advantages over conventional gate electrodes. However, it should be understood that not all advantages have been discussed here, different embodiments may provide different advantages, and no particular advantage is required for any embodiment. One advantage is improved performance. For example, the plurality of vertically protruding fingers of the filler metal of this article effectively increase the surface contact area between the gate electrode and the conductive gate contact, which in turn reduces the gate contact resistance. Therefore, the device performance is improved due to the reduced gate contact resistance. Another advantage is to improve the gap filling performance of the filler metal. For example, the conventional gate electrode formation process usually forms the filler metal after all the work function metal layers have been formed. At that time, the trench to be filled by the filler metal may be very narrow, so the filler metal needs to have good gap filling properties to fill the trench without generating large gaps or bubbles therein. On the contrary, since the present invention forms the filler metal before at least some of the work function metal layers, the trench to be filled by the filler metal in this article is much wider than that in conventional devices. Therefore, the filler metal of this article does not need to have rigorous / strict requirements for its gap filling properties. The resulting device is also unlikely to capture bubbles or gaps in the metal gate electrode, thereby improving the device yield. In addition, since the gap filling no longer has strict requirements on the filling metal layer, materials other than tungsten (W) can be used to implement the filling metal, for example, Cu, Co or Al can all be suitable candidates for implementing the filling metal layer of this article. Other advantages may include compatibility with existing manufacturing processes and simplicity and low cost of implementation.

[0062] The advanced lithography processes, methods and materials described above can be used in many applications, including fin field effect transistors (FinFETs). For example, fins can be patterned to produce relatively tight spacing between components, and the above disclosure is well suited for these spacings. In addition, spacers for forming fins (also called mandrels) of FinFETs can be processed according to the above disclosure.

[0063] One aspect of the present invention relates to a semiconductor device. The semiconductor device includes a channel component of a transistor and a gate component disposed above the channel component. The gate component includes: a dielectric layer; a first work function metal layer disposed above the dielectric layer; a filling metal layer disposed above the first work function metal layer; and a second work function metal layer disposed above the filling metal layer.

[0064] Another aspect of the present invention relates to a gate structure of a transistor. The gate structure includes: a gate dielectric layer; a first work function metal layer located above the gate dielectric layer; a filling metal layer located above the first work function metal layer, wherein the filling metal layer includes a U-shaped groove; and a second work function metal layer located in the U-shaped groove. The filling metal layer has a higher upper surface than the first work function metal layer and the second work function metal layer.

[0065] Another aspect of the present invention relates to a method for manufacturing a semiconductor device. The method includes: forming a gate dielectric layer; depositing a first work function metal layer over the gate dielectric layer; depositing a fill metal layer over the first work function metal layer, wherein the fill metal layer defines a concave groove; depositing a second work function metal layer in the concave groove; forming a dielectric material over the first work function metal layer, the fill metal layer, and the second work function metal layer; etching an opening through the dielectric material, wherein the opening exposes the upper surface and side surfaces of multiple segments of the fill metal layer; filling the opening with a conductive gate contact, wherein the multiple segments of the fill metal layer protrude vertically into the conductive gate contact.

[0066] Some embodiments of the present invention provide a semiconductor device, comprising: a channel component of a transistor; and a gate component disposed above the channel component, wherein the gate component comprises: a dielectric layer; a first work function metal layer disposed above the dielectric layer; a fill metal layer disposed above the first work function metal layer; and a second work function metal layer disposed above the fill metal layer. In some embodiments, at least a portion of the fill metal layer has a concave profile in a cross-sectional view. In some embodiments, an upper portion of the fill metal layer has a U-shaped cross-sectional profile; and a lower portion of the fill metal layer has an "I"-shaped cross-sectional profile. In some embodiments, the concave profile in the cross-sectional view is at least partially defined by a plurality of vertically protruding side portions of the fill metal layer, wherein the semiconductor device further comprises a gate contact disposed above the fill metal layer, and wherein a portion of the gate contact is disposed between the vertically protruding side portions of the fill metal layer. In some embodiments, the gate contact is in physical contact with the first work function metal layer and the second work function metal layer. In some embodiments, the uppermost surface of the fill metal layer is disposed above the uppermost surface of the first work function metal layer and above the uppermost surface of the second work function metal layer. In some embodiments, the first work function metal layer includes a first type of work function metal. The second work function metal layer includes a second type of work function metal; and the first type of work function metal is a p-type work function metal and the second type of work function metal is an n-type work function metal, or vice versa. In some embodiments, the gate assembly further includes a third work function metal layer disposed above the fill metal layer but below the second work function metal layer; and the third work function metal layer includes the first type of work function metal. In some embodiments, the gate assembly further includes a fourth work function metal layer disposed above the second work function metal layer; and the fourth work function metal layer includes the first type of work function metal. In some embodiments, the dielectric layer includes an interface layer and a high-k dielectric layer disposed above the interface layer.

[0067] Some embodiments of the present invention provide a gate structure of a transistor, comprising: a gate dielectric layer; a first work function metal layer located above the gate dielectric layer; a filling metal layer located above the first work function metal layer, wherein the filling metal layer includes a U-shaped groove; and a second work function metal layer located in the U-shaped groove; wherein the upper surface of the filling metal layer is higher than the first work function metal layer and the second work function metal layer. In some embodiments, the upper portion of the filling metal layer defines the U-shaped groove; and the lower portion of the filling metal layer is located below the U-shaped groove and has a vertical strip shape. In some embodiments, the gate structure further comprises: a third work function metal layer located above the filling metal layer but below the second work function metal layer; and a fourth work function metal layer located above the second work function metal layer. In some embodiments, the first work function metal layer, the third work function metal layer, and the fourth work function metal layer all contain a first type of work function metal; and the second work function metal layer contains a second type of work function metal different from the first type of work function metal.

[0068] Some embodiments of the present invention provide a method for forming a semiconductor device, comprising: forming a gate dielectric layer; depositing a first work function metal layer over the gate dielectric layer; depositing a fill metal layer over the first work function metal layer, wherein the fill metal layer defines a concave groove; depositing a second work function metal layer in the concave groove; forming a dielectric material over the first work function metal layer, the fill metal layer, and the second work function metal layer; etching an opening through the dielectric material, wherein the opening exposes the upper surface and side surfaces of multiple segments of the fill metal layer; and filling the opening with a conductive gate contact, wherein the multiple segments of the fill metal layer protrude vertically into the conductive gate contact. In some embodiments, the method further comprises, after the depositing of the second work function metal layer and before the forming of the dielectric material: etching the first work function metal layer, the fill metal layer, and the second work function metal layer, wherein the fill metal layer is etched at a slower etching rate than the first work function metal layer and the second work function metal layer, so that the multiple segments of the fill metal layer protrude above the first work function metal layer and the second work function metal layer. In some embodiments, depositing the first work function metal layer and depositing the second work function metal layer include: depositing a p-type work function metal layer as the first work function metal layer, and depositing an n-type work function metal layer as the second work function metal layer; or depositing an n-type work function metal layer as the first work function metal layer, and depositing a p-type work function metal layer as the second work function metal layer. In some embodiments, the method further includes: depositing a third work function metal layer over the filling metal layer, wherein the second work function metal layer is deposited over the third work function metal layer; and depositing a fourth work function metal layer on the second work function metal layer; wherein the second work function metal layer and the third work function metal layer partially fill the concave groove defined by the filling metal layer, and wherein the fourth work function metal layer completely fills the concave groove defined by the filling metal layer. In some embodiments, the method further comprises, before forming the gate dielectric layer: forming a fin structure comprising a semiconductor material; forming a dummy gate structure encapsulating the fin structure, wherein the dummy gate structure comprises a dummy gate electrode and a gate spacer formed on a sidewall of the dummy gate electrode; and removing the dummy gate electrode to form a trench at least partially defined by the gate spacer, wherein the gate dielectric layer is formed to partially fill the trench. In some embodiments, depositing the fill metal layer is implemented so that at least a portion of the fill metal layer has a U-shaped cross-sectional profile.

[0069] The features of several embodiments are summarized above so that those of ordinary skill in the art can better understand aspects of the present invention. Those of ordinary skill in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those of ordinary skill in the art should also be aware that such equivalent constructions do not deviate from the spirit and scope of the present invention, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device, comprising: a channel component of a transistor; as well as A gate component is disposed above the channel component, wherein the gate component comprises: Dielectric layer; A first work function metal layer is disposed above the dielectric layer; a filling metal layer, disposed above the first work function metal layer; and A second work function metal layer is disposed above the filling metal layer, The uppermost surface of the filling metal layer is vertically higher than the uppermost surface of the first work function metal layer or the uppermost surface of the second work function metal layer.

2. The semiconductor device according to claim 1, wherein At least a portion of the fill metal layer has a concave profile in a cross-sectional view.

3. The semiconductor device according to claim 2, wherein: The upper portion of the filling metal layer has a U-shaped cross-sectional profile; and The lower portion of the filling metal layer has an "I" shaped cross-sectional profile.

4. The semiconductor device according to claim 2, wherein: The concave profile in the cross-sectional view is at least partially defined by a plurality of vertically protruding side portions of the fill metal layer, wherein the semiconductor device further comprises a gate contact disposed above the fill metal layer, and wherein a portion of the gate contact is disposed between the vertically protruding side portions of the fill metal layer.

5. The semiconductor device according to claim 4, wherein: The gate contact is in physical contact with the first work function metal layer and the second work function metal layer.

6. The semiconductor device according to claim 1, wherein The fill metal layer protrudes vertically into the gate contact.

7. The semiconductor device according to claim 1, wherein: The first work function metal layer includes a first type work function metal; The second work function metal layer includes a second type work function metal; and The first type work function metal is a p-type work function metal, and the second type work function metal is an n-type work function metal, or vice versa.

8. The semiconductor device according to claim 7, wherein: The gate assembly further includes a third work function metal layer disposed above the fill metal layer but below the second work function metal layer; and The third work function metal layer includes the first type work function metal.

9. The semiconductor device according to claim 8, wherein: The gate assembly further includes a fourth work function metal layer disposed above the second work function metal layer; and The fourth work function metal layer includes the first type work function metal.

10. The semiconductor device according to claim 1, wherein The dielectric layer includes an interface layer and a high-k dielectric layer disposed above the interface layer.

11. A gate structure of a transistor, comprising: a gate dielectric layer; A first work function metal layer, located above the gate dielectric layer; a filling metal layer, located above the first work function metal layer, wherein the filling metal layer comprises a U-shaped groove; and A second work function metal layer is located in the U-shaped groove; The uppermost surface of the filling metal layer is more vertically higher than the uppermost surface of the first work function metal layer and the uppermost surface of the second work function metal layer.

12. The gate structure according to claim 11, wherein: The upper portion of the fill metal layer defines the U-shaped groove; and The lower portion of the filling metal layer is located below the U-shaped groove and has a vertical bar shape.

13. The gate structure according to claim 11, further comprising: a third work function metal layer, located above the filling metal layer but below the second work function metal layer; as well as The fourth work function metal layer is located above the second work function metal layer.

14. The gate structure according to claim 13, wherein: The first work function metal layer, the third work function metal layer and the fourth work function metal layer all contain a first type of work function metal; and The second work function metal layer includes a second type work function metal different from the first type work function metal.

15. A method of forming a semiconductor device, comprising: forming a gate dielectric layer; depositing a first work function metal layer over the gate dielectric layer; depositing a fill metal layer over the first work function metal layer, wherein the fill metal layer defines a concave groove; depositing a second work function metal layer in the concave groove; forming a dielectric material over the first work function metal layer, the fill metal layer, and the second work function metal layer; etching openings through the dielectric material, wherein the openings expose upper surfaces and sides of the plurality of segments of the fill metal layer; and The opening is filled with a conductive gate contact, wherein the plurality of segments of the fill metal layer protrude vertically into the conductive gate contact.

16. The method according to claim 15, further comprising, after depositing the second work function metal layer and before forming the dielectric material: etching the first work function metal layer, the filling metal layer and the second work function metal layer, wherein The fill metal layer is etched at a slower etching rate than the first work function metal layer and the second work function metal layer, so that the plurality of segments of the fill metal layer protrude above the first work function metal layer and the second work function metal layer.

17. The method according to claim 15, wherein: Depositing the first work function metal layer and depositing the second work function metal layer comprises: depositing a p-type work function metal layer as the first work function metal layer, and depositing an n-type work function metal layer as the second work function metal layer; or An n-type work function metal layer is deposited as the first work function metal layer, and a p-type work function metal layer is deposited as the second work function metal layer.

18. The method according to claim 15, further comprising: depositing a third work function metal layer on the filling metal layer, wherein the second work function metal layer is deposited on the third work function metal layer; and depositing a fourth work function metal layer on the second work function metal layer; The second work function metal layer and the third work function metal layer partially fill the concave groove defined by the filling metal layer, and the fourth work function metal layer completely fills the concave groove defined by the filling metal layer.

19. The method according to claim 15, further comprising, before forming the gate dielectric layer: forming a fin structure comprising a semiconductor material; forming a dummy gate structure wrapping the fin structure, wherein the dummy gate structure comprises a dummy gate electrode and a gate spacer formed on a sidewall of the dummy gate electrode; and The dummy gate electrode is removed to form a trench at least partially defined by the gate spacer, wherein the gate dielectric layer is formed to partially fill the trench.

20. The method according to claim 15, wherein: Depositing the fill metal layer is performed such that at least a portion of the fill metal layer has a U-shaped cross-sectional profile.

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