A MOSFET gate negative feedback active drive circuit

Abstract

The present invention provides a MOSFET gate negative feedback active drive circuit, which is used for high-speed driving of wide bandgap semiconductor devices such as SiC and GaN in bridge arm circuits. Based on the negative feedback control principle, the gate-source voltage interference is automatically suppressed without sacrificing the switching speed, so as to achieve gate voltage stability under high-speed switching. The circuit includes: a driving push-pull circuit, a driving resistor, an auxiliary capacitor and an auxiliary MOSFET. The driving push-pull circuit is an ordinary MOSFET driving chip, the driving resistor is a resistor R, the auxiliary capacitor is a capacitor C, and the auxiliary MOSFET is a P-channel MOSFET Q p The MOSFET gate negative feedback active drive circuit has a simple structure and is easy to implement. It can automatically suppress gate-source voltage interference and achieve gate voltage stability under high-speed switching without sacrificing the switching speed of wide-bandgap semiconductor devices such as SiC and GaN.

Description

Technical Field

[0001] The invention relates to a MOSFET grid negative feedback active driving circuit. Background Art

[0002] The high switching speed of MOSFET based on wide bandgap materials such as silicon carbide (SiC) and gallium nitride (GaN) enables converters to gain efficiency and power density advantages, and is an important technical guarantee in the field of high-performance power electronic conversion. However, higher switching speeds bring greater interference, which has become one of the main bottlenecks that restrict SiC / GaN MOSFET from fully utilizing its fast characteristics.

[0003] Scholars at home and abroad have conducted research on gate voltage interference suppression methods, which can be roughly summarized into passive suppression methods and active suppression methods.

[0004] Passive methods use passive components to suppress gate parasitic oscillations, mainly including: adding auxiliary capacitors between the gate and source, using negative turn-off voltage for gate drive, etc., see references [1-3]. Although adding auxiliary capacitors between the gate and source can share the interference current from the Miller capacitor and prevent it from flowing into the gate, thus suppressing gate interference, the additional auxiliary capacitors will slow down the switching speed, increase the switching loss, and lead to poor switching performance. The method of using negative turn-off voltage for gate drive effectively prevents gate interference from triggering false turn-on due to the increase of negative bias of the gate voltage, but at the cost of worsening the negative stress of the gate voltage.

[0005] In order to achieve better MOSFET gate voltage interference suppression effect, researchers introduced gate feedforward control and studied a variety of active suppression technologies. Reference [4] introduced an auxiliary circuit composed of four switching tubes to form a multi-level active gate driver (Multi-level AGD). The FPGA (field programmable gate arrays) controller detects the interference signal of the device and predicts the oscillation trend based on the device parameter model to avoid interference. The measured waveform in the reference shows that when dv / dt = 5V / ns, the Multi-level AGD technology can effectively suppress gate interference. However, considering that the switching time and gate interference oscillation period of SiC / GaN MOSFET are as short as tens of nanoseconds, the propagation delay of the sampling may be comparable to the switching time and oscillation period, or even longer, and the propagation delay of the detection signal is a challenge. References [2,3,5] studied the active Miller clamp technology (Active Miller Clamp, AMC), whose working principle is to actively enable the auxiliary transistor between the gate source after detecting that the gate voltage is higher than the clamping threshold, and directly clamp the gate to the negative bias voltage. However, in the fast switching transient process, the anti-interference problem of the detection signal is a challenge. This is because a larger dv / dt triggers a higher frequency gate interference oscillation. Due to the interference of the common source inductance and the stray inductance of the detection loop, the detected signal is prone to large deviations. Reference [2] shows that AMC technology can significantly improve gate interference oscillation when dv / dt is lower than 20V / ns. However, in the case of higher dv / dt, the mitigation effect on gate interference oscillation, especially negative oscillation, is limited. Reference [6] proposed two methods for suppressing Miller capacitor coupling oscillation: one is the gate impedance regulation technology (GIR), which is composed of an auxiliary circuit consisting of a switch tube and a capacitor. It predicts the gate oscillation trend according to the driving signal law, controls the auxiliary switch tube through a logic signal generator, reduces the gate impedance during the switching transient process, thereby clamping the gate voltage and suppressing gate interference. The dv / dt can reach 24.4V / ns; the other is the gate voltage control technology (GVC), which is composed of an auxiliary circuit consisting of two switch tubes and a diode. It predicts the gate oscillation trend according to the driving signal law, controls the auxiliary switch tube through a logic signal generator, and pre-charges the gate-source capacitor before the switching transient, thereby reversely offsetting the interference oscillation trend. The dv / dt can reach 24.9V / ns.In subsequent research, reference [7] proposed an intelligent gate drive (IGD), which is an auxiliary circuit consisting of two switching tubes and two diodes. Under different switching transients, the gate oscillation trend is predicted according to the driving signal law, and the auxiliary switching tube is controlled by a logic signal generator. The gate interference is suppressed by changing the gate voltage and gate impedance of the power device. The measured waveform shows that when dv / dt = 40V / ns, the IGD technology can effectively suppress the gate interference. However, under different working conditions, the voltage and current MOSFET bears are different, and the gate interference oscillation amplitude and frequency are also different. When the operating conditions of the MOSFET change, predicting the gate interference oscillation trend according to a fixed law is prone to over-compensation or under-compensation, affecting the accuracy of feedforward control. The method of suppressing interference by feedforward control of gate voltage generally detects the gate voltage or interference source, predicts the oscillation trend according to the driving signal law or according to the MOSFET parameter model, and takes measures in advance to avoid parasitic oscillation. However, high-speed switching interference makes the gate parasitic oscillation have high-frequency characteristics. Therefore, the detection signal is susceptible to interference and has obvious errors. The oscillation trend is affected by the working environment of the MOSFET and is difficult to predict accurately, which can easily cause inaccurate feedforward control.

[0006] In summary, due to the high frequency characteristics of gate interference and the accuracy limitation of feedforward control, the voltage change rate (dv / dt) that MOSFET can withstand under typical gate feedforward control is limited. Therefore, actively suppressing gate parasitic oscillation by controlling the gate voltage is still a very challenging task. The gate interference phenomenon is therefore more significant, becoming one of the main bottlenecks for fully utilizing the fast characteristics of SiC / GaN MOSFET.

[0007] References are as follows:

[0008] [1]ZENG Z,LI

[0009] [2]STMicroelectronics AN-5355.Mitigation Technique of the SiC MOSFETGate Voltage Glitches with Miller Clamp[EB / OL].Available online at https: / / www.st.com(accessed on 18March,2020).

[0010] [3]Avago Technologies AN-5314.Active Miller Clamp[EB / OL].Availableonline at http: / / www.avagotech.com(accessed on 18March,2020).

[0011] [4]ZHAO S,DEARIEN A,WU Y,et al.Adaptive Multi-Level Active GateDrivers for SiC Power Devices[J].IEEE Transactions on Power Electronics,2020,35(2):1882-1898.

[0012] [5]CHEN Z,DANILOVIC M,BOROYEVICH D,et al.Modularized DesignConsideration of a General-Purpose,High-Speed Phase-Leg PEBB Based on SiCMOSFETs:Proceedings ofthe 201114th European Conference on Power ElectronicsandApplications[C].Birmingham,UK:30Aug.-1Sept.2011.

[0013] [6]ZHANG Z,WANG F,TOLBERT LM,et al.Active Gate Driver for CrosstalkSuppression of SiC Devices in a Phase-Leg Configuration[J].IEEE Transactionson Power Electronics,2014,29(4):1986-1997.

[0014] [7]ZHANG Z,DIX J,WANG F,et al.Intelligent Gate Drive for FastSwitching and Crosstalk Suppression of SiC Devices[J].IEEE Transactions onPower Electronics,2017,32(12):9319-9332. Summary of the invention

[0015] The technical problem to be solved by the present invention is to provide a MOSFET gate negative feedback active drive circuit, which can automatically suppress gate-source voltage interference without sacrificing MOSFET switching speed and increasing circuit complexity.

[0016] The present invention is implemented as follows: a MOSFET gate negative feedback active drive circuit, used to connect a drive signal to control the on and off of a controlled MOSFET, comprising:

[0017] An auxiliary MOSFET, wherein the auxiliary MOSFET is a P-channel MOSFET, wherein the source of the auxiliary MOSFET is connected to the gate of the controlled MOSFET to construct a negative feedback regulation mechanism, and the drain of the auxiliary MOSFET is connected to a driving voltage; the driving voltage is the voltage of the driving chip after being filtered by a passive network.

[0018] Furthermore, it also includes: a first node, a second node and a third node;

[0019] A driving push-pull circuit, used for providing a driving current to drive the controlled MOSFET, wherein the driving signal is connected to the driving push-pull circuit, and the driving push-pull circuit is connected in series with the third node;

[0020] A driving resistor R, one end of which is connected in series with the driving push-pull circuit, and the other end of which is connected to the first node, for limiting the charging and discharging current of the driving push-pull circuit on the auxiliary capacitor C, and the voltage difference between the first node and the source of the controlled MOSFET is the driving voltage;

[0021] An auxiliary capacitor C, one end of which is connected to the first node, and the other end of which is connected to the source of the controlled MOSFET through the third node, and forms a passive network with the driving resistor R for adjusting the switching speed of the controlled MOSFET;

[0022] The drain and gate of the auxiliary MOSFET are connected in series with the driving resistor R through a second node, and the source of the auxiliary MOSFET is connected to the gate of the controlled MOSFET, so as to construct a negative feedback regulation mechanism.

[0023] Furthermore, the driving push-pull circuit includes a MOSFET driving chip, a turn-on bias voltage V CC and the shutdown bias voltage V EE The MOSFET driver chip output power positive port is connected to the turn-on bias voltage V CC The positive terminal of the MOSFET driver chip output power negative port is connected to the shutdown bias voltage V EE The negative electrode of the MOSFET driver chip, the drive output port of the MOSFET driver chip is connected to one end of the drive resistor R, and the drive input port of the driver chip is connected to the drive signal; the turn-on bias voltage V CC The negative pole and the off bias voltage V EE The positive electrodes of the MOSFETs are connected to the third node; in terms of driving capability, the output current of the MOSFET driver chip should be no less than (V CC -V EE ) / R g , where R g is the gate parasitic resistance of the controlled MOSFET.

[0024] Furthermore, the drain-source breakdown voltage of the auxiliary MOSFET is not less than V CC -V EE , and the continuous drain current is not less than (V CC -V EE ) / R g .

[0025] The advantages of the present invention are: a MOSFET gate negative feedback active drive circuit, which has a simple structure, is easy to implement, does not rely on additional circuits, and can be implemented by only using a common MOSFET drive chip, a drive resistor, an auxiliary MOSFET, and an auxiliary capacitor. Functionally, the MOSFET gate negative feedback active drive circuit can automatically suppress gate-source voltage interference without sacrificing the MOSFET switching speed, and achieve gate voltage stability under high-speed switching. In subsequent examples, compared with traditional passive suppression schemes, the MOSFET gate negative feedback active drive circuit can achieve a larger gate-source voltage oscillation suppression, and will not sacrifice the switching speed, and the switching speed is still improved to a certain extent. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The present invention will be further described below in conjunction with embodiments with reference to the accompanying drawings.

[0027] Figure 1 It is a structural schematic diagram of a MOSFET gate negative feedback active drive circuit according to the present invention;

[0028] Figure 2 It is a control block diagram of a MOSFET gate negative feedback active drive circuit described in the present invention;

[0029] Figure 3 A gate negative feedback active drive in a bridge arm structure according to an embodiment of the present invention;

[0030] Figure 4a is the gate negative feedback active drive Q according to the embodiment of the present invention. H Principle waveform of the turn-on process;

[0031] Figure 4b is the gate negative feedback active drive Q according to the embodiment of the present invention. H Principle waveform of the shutdown process;

[0032] Figure 5a It is an experimental circuit diagram without any suppression measures for comparison of a MOSFET gate negative feedback active drive circuit according to an embodiment of the present invention;

[0033] Figure 5b It is an experimental circuit diagram of a MOSFET gate negative feedback active drive circuit according to an embodiment of the present invention and using passive suppression measures;

[0034] Figure 5c It is an experimental circuit diagram of negative feedback active driving for comparison with a MOSFET gate negative feedback active driving circuit according to an embodiment of the present invention;

[0035] Figure 6ais an experimental waveform within one switching cycle in a conventional driving circuit without interference suppression according to an embodiment of the present invention;

[0036] Figure 6b is a conventional driving circuit without interference suppression according to an embodiment of the present invention. DS2 Experimental waveform with the rising edge magnified;

[0037] Figure 6c is a conventional driving circuit without interference suppression according to an embodiment of the present invention. DS2 Experimental waveform with the falling edge enlarged;

[0038] Figure 7a is an experimental waveform within a switching cycle of a driving circuit using a passive suppression method according to an embodiment of the present invention;

[0039] Figure 7b is a driving circuit using a passive suppression method according to an embodiment of the present invention. DS2 Experimental waveform with the rising edge magnified;

[0040] Figure 7c is a driving circuit using a passive suppression method according to an embodiment of the present invention. DS2 Experimental waveform with the falling edge enlarged;

[0041] Figure 8a is an experimental waveform within a switching cycle of a MOSFET gate negative feedback active drive circuit according to an embodiment of the present invention;

[0042] Figure 8b The embodiment of the present invention adopts the MOSFET gate negative feedback active drive circuit v DS2 Experimental waveform with the rising edge magnified;

[0043] Figure 8c The embodiment of the present invention adopts the MOSFET gate negative feedback active drive circuit v DS2 Experimental waveform with the falling edge enlarged. DETAILED DESCRIPTION

[0044] One implementation mode of the present invention:

[0045] like Figure 1 As shown, the MOSFET gate negative feedback active drive circuit is used to drive the MOSFET Q N If the controlled MOSFET Q N It is the active tube in the bridge arm circuit. At the start of conduction, the PWM signal S changes from low level to high level, and the output end of the driver chip is connected to the conduction bias voltage V CC , the driver chip charges the auxiliary capacitor C through the driving resistor R, and the driving voltage v GS*Increases gradually from V EE Rising to V CC At the initial moment, due to the controlled MOSFET Q N The gate-source voltage v GS Still at the off bias voltage V EE , which makes D P The potential is higher than S P When the potential difference exceeds the threshold voltage, Q P The parasitic diode is forward-conducting, and the driver chip is connected through Q P The parasitic body diode is Q N The input capacitance C iss Charging, Q N The gate-source voltage v GS Increase; if v GS Too large makes S P The potential is higher than D P When the potential difference reaches Q P When the turn-on threshold voltage is P Channel conduction, Q N Input capacitance C iss Discharge, v GS will decrease accordingly; due to the existence of this negative feedback mechanism, during the conduction process, Q N The gate-source voltage v GS will closely follow the drive voltage v GS *Change. Similarly, at the start of shutdown, the PWM signal S changes from high level to low level, and the output of the driver chip is connected to the shutdown bias voltage V EE , the driver chip discharges the auxiliary capacitor C, and the driving voltage v GS *Decrease gradually from V CC Drop to V EE At the initial moment, due to the controlled MOSFET Q N The gate-source voltage v GS Still at the on-bias voltage V CC , which makes S P The potential is higher than D P When the potential difference exceeds the threshold voltage, Q P The channel is turned on, and the driver chip passes Q P The channel is Q N The input capacitance C iss Discharge, Q N The gate-source voltage v GS decrease; if v GS Too small to make D P The potential is higher than S P When the potential difference is higher than the threshold voltage, Q P The parasitic body diode is turned on, Q NInput capacitance C iss Charging, v GS will increase accordingly; due to the existence of this negative feedback mechanism, during the shutdown process, Q N The gate-source voltage v GS will closely follow the drive voltage v GS *change.

[0046] If the controlled MOSFET Q N For passive transistors in the bridge arm circuit, the clamp needs to be turned off to resist external interference. At this time, the PWM signal S is always at a low level, and the output voltage of the gate driver chip is the turn-off bias voltage V EE , driving voltage v GS *=V EE .Q N The gate-source voltage v GS In steady state, it is equal to the off bias voltage V EE ; When Q N The gate-source voltage v GS When disturbed and fluctuates, the negative feedback mechanism is triggered. N The gate-source voltage v GS When the interference increases, S P The potential is higher than D P When the potential difference exceeds the threshold voltage, Q P The channel is turned on, and the driver chip passes Q P The channel is Q N The input capacitance C iss Discharge, Q N The gate-source voltage v GS Decrease; if Q N The gate-source voltage v GS The interference is reduced when D P The potential is higher than S P When the potential difference exceeds the threshold voltage, Q P The parasitic body diode is turned on, Q N Input capacitance C iss Charging, v GS will increase accordingly. Due to the existence of this negative feedback mechanism, Q N The gate-source voltage v GS When disturbed and fluctuates, Q N The gate-source voltage v GS The clamp is placed tightly at the drive voltage v GS *=V EE .

[0047] like Figure 2As shown in FIG. 1 , it is a negative feedback regulation mechanism unique to the circuit of the present invention. The driving circuit of the present invention shields the interference of pulse voltage and pulse current through this mechanism, and realizes gate voltage stability under high-speed switching. The driving voltage v GS *As the reference signal of the gate source, it is input into the gate negative feedback control loop. The reference signal is related to the gate source voltage v of the controlled MOSFET. GS The difference between the two is the transconductance gain g of the auxiliary MOSFET. m , controls the input capacitance C of the controlled MOSFET iss , Gate internal resistance R g Considering the external pulse voltage and pulse current interference n(s), the displacement current is generally generated through the Miller capacitor, which affects the C of the controlled MOSFET. iss Charging and discharging interfere with the gate-source voltage. GS Increase (or decrease), then the reference value v GS *The difference increases, and after the transconductance gain of the driver tube is adjusted, the input capacitor C iss Discharge (or charge), the gate-source voltage v of the controlled MOSFET GS The goal of gate negative feedback control is to make the gate-source voltage v of the controlled MOSFET GS Tracking drive signal v GS *changes and shields the interference of pulse voltage and pulse current n(s). Without sacrificing the switching speed, it automatically suppresses the interference of gate-source voltage and achieves gate voltage stability under high-speed switching.

[0048] like Figure 3 As shown, this embodiment shows a negative feedback active drive circuit for a bridge arm structure. H and bridge arm lower tube Q L They are all expressed in the form of junction capacitance to help users understand the working principle of the MOSFET gate negative feedback active drive circuit. Figure 3 To distinguish the upper tube from the lower tube, add the subscripts "1" and "2" respectively, or add the subscripts "L" and "H" respectively. 1 and R 2 Represents the driving resistance of the upper tube and the lower tube respectively, C 1 and C 2 Represents the auxiliary capacitors of the upper tube and the lower tube, Q p1 and Q p2 Represents the auxiliary MOSFET of the upper and lower tubes respectively. H As an active tube, the pulse control signal S 1 Under the control of, open and close; bridge arm lower tube Q L As a passive tube, its control signal S 2 Always at low level, QL The channel is turned off, and only its parasitic body diode is used for freewheeling.

[0049] Miller capacitance C of MOSFET gdH and C gdL As the drain-source voltage increases, C gdH and C gdL The value of C gd1 ; When the drain-source voltage is less than the gate-source voltage, C gdH and C gdL The value of C gd2 The output current at the midpoint of the bridge arm is approximately constant during a switching cycle, so it is represented by a constant current source as I L At the same time, the DC voltage on the bridge arm is recorded as V DC .

[0050] like Figure 4a and Figure 4b As shown, they respectively show Figure 3 The Q of the circuit shown H The theoretical waveforms of the turn-on and turn-off dynamic processes are represented by S 1 The moment when S changes from low level to high level, 1 The moment when the high level changes to the low level is the initial moment. The two dynamic processes have four main modes, which are described as follows:

[0051] 1. If Figure 4a As shown, Q H Opening process

[0052] Opening mode 1: Opening delay phase t d(on) At time 0, S 1 From low level to high level, the driver chip passes R 1 is the auxiliary capacitor C 1 Charging, driving voltage v GS1 *Increases gradually from V EE1 Rising to V CC1 Due to the negative feedback mechanism, Q H The gate-source voltage v GS1 Follow v GS1 * changes, and gradually increases, but due to Figure 1 The gate negative feedback active drive is an I-type system, which has a ramp signal v GS1 * has a certain tracking error, but because the open-loop gain is large enough, the tracking error will not affect the normal operation of the drive circuit. GS1 Still less than the threshold voltage V GS,th , QH The channel is in the off state, i D1 =0. DS1 At V DC unchanged, when v GS1 Rising to V GS,th , the mode ends.

[0053] Opening mode 2: Current rising stage t ri .v GS1 From the threshold voltage V GS,th Start, increase to V GS,IL , indicating that the channel current can be maintained at I L V GS1 Value. DS1 At V DC No change. H The current i D1 From 0 to I L In this process, due to the passive tube current i D2 The reduction of Q L The gate-source voltage v GS2 Produces a slight rise, but not enough to trigger Q P2 Ignoring Q L Under the condition of reverse recovery of the parasitic body diode, this mode occurs when the current rises to I L The moment is over.

[0054] Opening mode 3: Voltage drop stage t fv1 In the case of a normal drive circuit, it will enter the Miller platform, and the gate-source voltage will be maintained at V gs,IL However, for MOSFETs that use gate negative feedback active drive, Figure 1 The existence of the negative feedback mechanism described in the embodiment, Q H The gate-source voltage v GS1 Still following v GS1 * rise together and will not remain at V gs,IL In this mode, v DS1 From V DC starts to decrease. Since the drain-source voltage is still greater than the gate-source voltage, C gdH The value is still relatively small (C gd1 ), this stage v DS1 The falling speed is relatively fast. In this mode, Q L The drain-source voltage v DS2 rises rapidly, so Q L The gate-source voltage v GS2 Produce a significant increase; due to Figure 1 The existence of the negative feedback mechanism described in the embodiment, when S P2 The potential is higher than D P2potential, and the potential difference exceeds the threshold voltage V th When P2 The channel is turned on, and the driver chip passes Q P2 The channel is Q L The input capacitance C issL Discharge, Q L The gate-source voltage v GS2 Reduced, interference is suppressed, v GS2 Back to V EE2 When v DS1 Down to v GS1 When they are numerically equal, the mode ends.

[0055] Opening mode 4: Voltage drop stage t fv2 .because Figure 1 The existence of the negative feedback mechanism described in the embodiment, Q H The gate-source voltage v GS1 Still following v GS1 * rise together and will not remain at V gs,IL No change. DS1 Continue to decrease, because the drain-source voltage is less than the gate-source voltage, C gdH The value is relatively large (C gd2 ), this stage v DS1 The falling speed is relatively slow. DS1 Drop to V DS(on) , the mode ends.

[0056] After mode 4 is turned on, due to the existence of the negative feedback mechanism mentioned above, Q H The gate-source voltage v GS1 Still following v GS1 * Raise to high level V CC1 , and finally complete the opening process.

[0057] 2. If Figure 4b As shown, Q H Shutdown process

[0058] Shutdown mode 1: Shutdown delay phase t d(off) At time 0, S 1 From high level to high level, the driver chip passes R 1 is the auxiliary capacitor C 1 Discharge, driving voltage v GS1 *Decrease gradually from V CC1 Drop to V EE1 .because Figure 1 In the embodiment, negative feedback mechanism, Q H The gate-source voltage v GS1 Follow v GS1 * changes, and gradually decreases, but due to Figure 1The gate negative feedback active drive shown is a type I system, which has a ramp signal v GS1 *There is a certain error in tracking, but since the open-loop gain is large enough, the tracking error will not affect the normal operation of the drive circuit. Since the gate-source voltage is still greater than the threshold voltage V GS,th , Q H The channel is in the on state, so there is still i D1 =I L , v DS1 Still at V DS(on) unchanged. When v GS1 Falling to V GS,IL , the mode ends.

[0059] Shutdown mode 2: Voltage rise phase t rv1 In the case of a normal drive circuit, it will enter the Miller platform, and the gate-source voltage will be maintained at V GS,IL However, for MOSFETs that use gate negative feedback active drive, Figure 1 The existence of the negative feedback mechanism described in the embodiment, Q H The gate-source voltage v GS1 Still following v GS1 * decrease together and will not maintain at V GS,IL In this mode, v DS1 From V DS(on) Since the drain-source voltage is still lower than the gate-source voltage, C gdH The value is still relatively large (C gd2 ), this stage v DS1 The rising speed is relatively slow. DS1 Rise to v GS1 When they are numerically equal, the mode ends.

[0060] Shutdown mode 3: Voltage rise phase t rv2 .because Figure 1 The existence of negative feedback mechanism, Q H The gate-source voltage v GS1 Still following v GS1 * decrease together. In this mode, v DS1 Continue to rise. Since the drain-source voltage is greater than the gate-source voltage, C gdH The value is relatively small (C gd1 ), this stage v DS1 The rising speed is relatively fast. L The drain-source voltage v DS2 decreases rapidly, so Q L The gate-source voltage v GS2 Produced a significant decline; due to Figure 1 The existence of negative feedback mechanism is shown. P2The potential is higher than S P2 potential, and the potential difference exceeds the threshold voltage V th When P2 The parasitic diode is turned on, and the driver chip is powered by Q P2 The parasitic body diode is Q L The input capacitance C issL Charging, Q L The gate-source voltage v GS2 increases, the interference is suppressed, v GS2 Back to V EE2 When v DS1 Rising to V DC , the mode ends.

[0061] Shutdown mode 4: Current decline phase t fi .because Figure 1 The existence of negative feedback mechanism, Q H The gate-source voltage v GS1 Still following v GS1 * decrease together until it reaches the threshold voltage V GS,th In this process, due to the passive tube current i D2 The increase of Q L The gate-source voltage v GS2 A slight drop occurs, but not enough to trigger Q P2 The parasitic body diode is turned on. In this mode, v DS1 At V DC No change, Q H The current i D1 From I L It starts to decrease to 0 and the mode ends.

[0062] After shutting down mode 4, due to Figure 1 The existence of negative feedback mechanism shown in the embodiment, Q H The gate-source voltage v GS1 Still following v GS1 * together, from the threshold voltage V GS,th Until it drops to a low level V EE1 , and finally complete the shutdown process.

[0063] The design principles of the parameters of the gate negative feedback active drive circuit of the present invention are described as follows.

[0064] (1) Principles for selecting controlled MOSFET

[0065] When the gate negative feedback active drive of the present invention is used, it is necessary to first determine the controlled MOSFET as the switching device for the main power electric energy conversion according to the working environment of the power conversion device. It is consistent with the selection principle of the power switch device of the power conversion device under the traditional driving mode. Generally, under the rated working state of the power conversion device, the maximum working voltage and working current of the device are calculated to ensure that the MOSFET is in the safe working area, and the maximum drain-source voltage and maximum drain current allowed by the device are referred to to determine the MOSFET model. In this implementation example, a device with a high degree of commercialization and a relatively typical device in the field of high-power electric energy conversion is selected as the controlled MOSFET to demonstrate the technical feasibility of the proposed method. The maximum drain-source voltage of the MOSFET is 1200V, the maximum drain current is 56A, and the model is IMZ120R030M1H.

[0066] (2) Driver chip selection and peripheral circuit design principles

[0067] Since the threshold voltage of the controlled MOSFET is low (about 2-4V), although the gate negative feedback active drive circuit has the function of stabilizing the gate-source voltage and shielding the interference of pulse voltage and pulse current, it does not completely eliminate the instability of the gate. Therefore, negative voltage shutdown of the driver is very necessary. It is recommended to turn on the bias voltage V CC =18~22V, turn-off bias voltage V EE =-2.5~-5V. The QA01C series of Jinshengyang drive power modules (or similar alternative products) can be used to realize the turn-on and turn-off bias voltages. Based on the above considerations, in the design of this implementation example, the turn-on voltage V CC =20V, turn-off voltage V EE =-5V.

[0068] The recommended common mode transient immunity CMTI is ≥ 100V / ns (over the full temperature range). In terms of driving capability, the chip output current should be no less than (V CC -V EE ) / R g , where R g is the gate parasitic resistance of the controlled MOSFET. For example, the gate internal resistance R g =3Ω, so the chip output current should be no less than 8.3A. In this implementation example, the driver chip 1ED3124MU12H is used, and the output current can reach 14A.

[0069] (3) Auxiliary MOSFET selection principles

[0070] The auxiliary MOSFET needs to be implemented by selecting a device that is dual to the channel characteristics of the controlled MOSFET. Generally, the controlled MOSFET is an N-channel MOSFET, so the auxiliary MOSFET should be a P-channel MOSFET. At the same time, to ensure control accuracy, the transconductance gain of the auxiliary MOSFET is much greater than 1 (S). In addition, since the auxiliary MOSFET needs to withstand a certain voltage and current during the turn-on and turn-off process of the controlled MOSFET, in order to ensure the safe operation of the auxiliary MOSFET, the turn-on bias voltage V designed according to the driver chip needs to be set. CC Shutdown bias voltage V EE , and the gate characteristics of the controlled MOSFET, select the voltage and current levels of the auxiliary MOSFET, and recommend that the drain-source breakdown voltage is not less than V CC -V EE , and the continuous drain current it can withstand is not less than (V CC -V EE ) / R g Based on the above analysis, this implementation example uses FDS9435A as a P-channel auxiliary MOSFET, whose drain-source breakdown voltage is 30 (V), the sustainable continuous drain current is 25 (A), and the transconductance gain is 10 (S).

[0071] (4) Design principles of auxiliary capacitor and drive resistor

[0072] The auxiliary capacitor and driving resistor (such as Figure 1 C and R in the , together affecting v GS Rise and fall speed. In general, the input capacitance of the controlled MOSFET is about nF level, and the transconductance gain of the auxiliary MOSFET is much greater than 1 (S). Therefore, the open-loop gain of the gate negative feedback active drive circuit is large enough. When v GS Tracking the ramp up (down) of v GS *, the deviation between the two is very small, v GS * and v GS Have approximately equal ascent and descent speeds.

[0073] The auxiliary capacitor C also has a decoupling function, shortening the "electrical circumference" of the loop formed by the output end of the driver chip, the auxiliary MOSFET and the gate source of the controlled MOSFET. It is recommended that the auxiliary capacitor C has an impedance of no more than 0.2Ω at the undamped self-oscillation frequency of the power loop of the bridge arm circuit, that is:

[0074] In this embodiment, the output capacitance C of the controlled MOSFET (IMZ120R030M1H) oss =116pF, stray inductance L of the power circuit oIt is estimated to be 50nH. Therefore, according to the above formula, the auxiliary capacitor C should not be less than 12nF. In engineering, the auxiliary capacitor C=20nF is selected to ensure that its impedance at the undamped self-oscillation frequency of the power circuit is small enough.

[0075] After the auxiliary capacitor C is selected, the drive resistor R can be designed. The product of the drive resistor R and the auxiliary capacitor C, τ = RC, is the charge and discharge time constant of the RC circuit. The charge and discharge time constant τ is inversely proportional to the rise and fall slope of the gate-source voltage, that is, a larger charge and discharge time constant τ will lead to a slower gate-source voltage rise and fall time, so the switching speed of the controlled MOSFET will also slow down. Conversely, if the switching speed of the controlled MOSFET needs to be accelerated, such as when it is necessary to reduce losses and improve efficiency, a smaller charge and discharge time constant τ can be used to obtain a faster switching speed. However, the drive resistor R also needs to take into account the current limiting and protection of the driver chip in terms of function. At the beginning of the switching action, the driver chip charges and discharges the auxiliary capacitor C through the drive resistor R to a peak value (V CC -V EE ) / R. In order to maximize the load capacity of the driver chip selected in this embodiment and allow the MOSFET to obtain a relatively fast switching speed, this embodiment designs the charge and discharge current peak value (V CC -V EE ) / R. Turn-on voltage V CC =20V, turn-off voltage V EE =-5V, 70% of the maximum output current of 1ED3124MU12H is about 10A, so the drive resistance R = 2.5Ω, and the corresponding charge and discharge time constant τ = 50nS. It should be noted that the design of the drive resistance R here is only for demonstration purposes. In industrial applications, the drive resistance can be flexibly adjusted and selected based on the comprehensive requirements of efficiency, loss, electromagnetic compatibility, etc., combined with the value of the auxiliary capacitor.

[0076] (5) PCB design of driving circuit

[0077] In order to ensure the reliability of the hardware design, it is necessary to reduce the parasitic inductance in the power circuit in the main power part, and reduce the drain-source voltage oscillation and spike of the power tube MOSFET. This embodiment adopts the method of copper plating on both the upper and lower layers and connecting vias in the middle. In the drive circuit, in order to make the parasitic inductance of the loop as small as possible, the length of the drive circuit is shortened as much as possible, and the main components are placed as close to the power tube MOSFET as possible while meeting safety regulations. At the same time, the drive circuit is shortened by plating copper over a large area to ensure that the auxiliary MOSFET can work effectively and is not affected by the stray parameters of the leads.

[0078] like Figure 5a , 5bAs shown in Figure 5c, it is an experimental circuit of the present embodiment in the double pulse circuit, including an experimental circuit without any suppression measures for comparison of a MOSFET gate negative feedback active driving circuit, an experimental circuit using passive suppression measures for comparison of a MOSFET gate negative feedback active driving circuit, and an experimental circuit using negative feedback active driving for comparison of a MOSFET gate negative feedback active driving circuit; each circuit is provided with a driving pulse to drive the active MOSFET Q H , set a negative voltage bias to turn off the passive MOSFET Q L In this example, the passive tube Q of three cases is compared. L Gate-source voltage v GS2 The interference situation is used to verify the effectiveness of using MOSFET gate negative feedback active drive circuit to stabilize the gate-source voltage.

[0079] like Figures 6a to 6c As shown, the experimental waveform of the conventional driving circuit without interference suppression according to the embodiment of the present invention, the active tube Q H And the passive tube Q L The driver only has the driving resistor, and the corresponding driving resistor is 10Ω. Figure 6a As shown, the passive tube Q L Gate-source voltage v GS2 The interference caused a large oscillation, with the positive interference amplitude up to 7.9V and the negative interference amplitude up to 7V. Figure 6b As shown, the passive tube Q L The drain-source voltage v DS2 During the rising process, the rising slope of 100V-800V is about 43.7V / ns. Figure 6c As shown, the passive tube Q L The drain-source voltage v DS2 During the decline, the decline slope of 800V-100V is about 51.25V / ns. L The drain-source voltage v DS2 The rising and falling speeds are fast, causing Q L Gate-source voltage v GS2 obvious instability.

[0080] like Figures 7a to 7c As shown in the figure, the experimental waveform of the driving circuit using the passive suppression method in this embodiment, the active tube Q H And the passive tube Q L The driving circuit adopts the method of parallel gate-source auxiliary capacitor. The driving resistor R 1 , R 2 The gate-source parallel auxiliary capacitor C a1 , C a2 is 2nF. Figure 7a As shown, the passive tube QL Gate-source voltage v GS2 The interference oscillation is alleviated to a certain extent, the positive interference amplitude is about 4V, and the negative interference amplitude is also about 4V. Figure 7b As shown, the passive tube Q L The drain-source voltage v DS2 During the rising process, the rising slope of 100V-800V is about 42.5V / ns. Figure 7c As shown, the passive tube Q L The drain-source voltage v DS2 During the decline process, the decline slope of 800V-100V is about 39.6V / ns. Figures 6a to 6c The switching speed in the embodiment is greatly reduced. It can be seen that the passive gate oscillation suppression method using a gate-source parallel auxiliary capacitor effectively suppresses the oscillation of the gate-source, but at the expense of switching speed.

[0081] like Figures 8a to 8c As shown in FIG. 1 , the experimental waveform of the MOSFET gate negative feedback active drive circuit in this embodiment is used. H And the passive tube Q L The driving circuits of all adopt active negative feedback drive. Figure 8a As shown, the passive tube Q L Gate-source voltage v GS2 The interference oscillation is alleviated to a greater extent, the positive interference amplitude is about 3V, and the negative interference amplitude is also about 3V. Figure 8b As shown, the passive tube Q L The drain-source voltage v DS2 During the rising process, the rising slope of 100V-800V is about 50V / ns. Figure 8c As shown, the passive tube Q L The drain-source voltage v DS2 During the decline process, the decline slope of 800V-100V is about 50V / ns. Figures 7a to 7c Compared with the passive suppression scheme in the embodiment, the gate negative feedback active suppression circuit proposed in the present invention can achieve a larger gate-source voltage oscillation suppression, and will not sacrifice the switching speed. Figures 6a to 6c The switching speed of the embodiment is still improved to a certain extent.

[0082] Another specific implementation of the present invention:

[0083] like Figure 1 As shown, a MOSFET gate negative feedback active drive circuit is used to connect a drive signal to control the on and off of a controlled MOSFET, comprising:

[0084] The drive push-pull circuit is used to generate the drive voltage v to control wide bandgap semiconductor devices such as MOSFET GS *; that is, providing a driving current to drive the controlled MOSFET, the driving signal is connected to the driving push-pull circuit, and the driving push-pull circuit is connected in series with the third node;

[0085] A driving resistor R, one end of which is connected in series with the driving push-pull circuit, and the other end of which is connected to the first node, for limiting the charging and discharging current of the driving push-pull circuit on the auxiliary capacitor C, and playing the role of current limiting and protection; the voltage difference between the first node and the source of the controlled MOSFET is the driving voltage;

[0086] An auxiliary capacitor C, one end of which is connected to the first node, and the other end of which is connected to the source electrode S of the controlled MOSFET through the third node, and forms a passive network with the driving resistor R for adjusting the switching speed of the controlled MOSFET;

[0087] Auxiliary MOSFET, the auxiliary MOSFET is a P-channel MOSFET, the auxiliary MOSFET source is connected to the gate of the controlled MOSFET, and is used to construct a negative feedback regulation mechanism, and the auxiliary MOSFET drain is connected to a driving voltage; the driving voltage is the voltage of the driving chip after being filtered by a passive network; the P-channel MOSFET drain D p and gate G p The source S is connected in series with the driving resistor R through the second node. p Connected to the gate G of the controlled MOSFET to construct a negative feedback regulation mechanism to achieve self-stabilization of the gate voltage;

[0088] The driving push-pull circuit includes a MOSFET driving chip, a turn-on bias voltage V CC and the shutdown bias voltage V EE The MOSFET driver chip output power positive port is connected to the turn-on bias voltage V CC The positive terminal of the MOSFET driver chip output power negative port is connected to the shutdown bias voltage V EE The negative electrode of the MOSFET driver chip, the drive output port of the MOSFET driver chip is connected to one end of the drive resistor R, and the drive input port of the driver chip is connected to the drive signal; the turn-on bias voltage V CC The negative pole and the off bias voltage V EE The positive electrodes of the transistors are connected to the third node; the push-pull driving circuit only needs to use a common MOSFET driving chip, V CC To turn on the bias voltage, the recommended bias voltage is 18~22V, V EETo turn off the bias voltage, the recommended turn-off bias voltage value is -2.5 to -5V. The recommended common mode transient immunity (CMTI) of the driver chip is ≥100V / ns (over the full temperature range). In terms of driving capability, the chip output current should not be less than (V CC -V EE ) / R g , where R g is the gate parasitic resistance of the controlled MOSFET.

[0089] The P-channel MOSFET needs to withstand a certain voltage and current during the turn-on and turn-off process of the controlled MOSFET. Therefore, in order to ensure its safe operation, the turn-on bias voltage V CC Shutdown bias voltage V EE , and the gate characteristics of the controlled MOSFET, select the voltage and current levels of the auxiliary MOSFET, and recommend that the drain-source breakdown voltage is not less than V CC -V EE , and the continuous drain current it can withstand is not less than (V CC -V EE ) / R g At the same time, in order to ensure control accuracy, the transconductance gain of the P-channel MOSFET should be much larger than 1 (S).

[0090] The auxiliary capacitor C can not only adjust the switching speed of the controlled MOSFET, but also reduce the loop area composed of the driver chip, the auxiliary MOSFET, and the gate-source of the controlled MOSFET, thereby achieving high-frequency decoupling of the drive loop.

[0091] Although the specific implementation modes of the present invention are described above, those skilled in the art should understand that the specific implementation modes described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. A MOSFET gate negative feedback active drive circuit, used to connect a drive signal to control the on and off of a controlled MOSFET, characterized in that: include: an auxiliary MOSFET, wherein the auxiliary MOSFET is a P-channel MOSFET, the source of the auxiliary MOSFET is connected to the gate of the controlled MOSFET to construct a negative feedback regulation mechanism, and the drain of the auxiliary MOSFET is connected to a driving voltage; The driving voltage is the voltage of the driving chip after being filtered by the passive network; Also includes: a first node, a second node and a third node; A driving push-pull circuit, used for providing a driving current to drive the controlled MOSFET, wherein the driving signal is connected to the driving push-pull circuit, and the driving push-pull circuit is connected in series with the third node; Drive resistance R , the driving resistance R One end is connected in series with the driving push-pull circuit, and the other end is connected to the first node, which is used to limit the driving push-pull circuit to the auxiliary capacitor C The charge and discharge current of the first node is the driving voltage. Auxiliary capacitor C , the auxiliary capacitor C One end is connected to the first node, and the other end is connected to the source of the controlled MOSFET through the third node, forming a passive network with the driving resistor R, which is used to adjust the switching speed of the controlled MOSFET; The drain and gate of the auxiliary MOSFET are connected to the driving resistor via a second node. R The auxiliary MOSFET source is connected in series with the gate of the controlled MOSFET to construct a negative feedback regulation mechanism; The driving push-pull circuit includes a MOSFET driving chip, a bias voltage V CC and the shutdown bias voltage V EE ; The MOSFET driver chip output power positive port is connected to the turn-on bias voltage V CC The positive terminal of the MOSFET driver chip output power negative port is connected to the shutdown bias voltage V EE The negative electrode of the MOSFET driver chip is connected to the drive output port of the drive resistor R The driving input port of the driving chip is connected to the driving signal; the turn-on bias voltage V CC The negative pole and the off bias voltage V EE The positive electrodes of the MOSFETs are connected to the third node; in terms of driving capability, the output current of the MOSFET driver chip should be no less than ( V CC - V EE ) / R g ,That R g is the gate parasitic resistance of the controlled MOSFET.

2. A MOSFET gate negative feedback active drive circuit according to claim 1, characterized in that: The drain-source breakdown voltage of the auxiliary MOSFET is not less than V CC - V EE , and the continuous drain current is not less than ( V CC - V EE ) / R g .

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