A semiconductor epitaxial structure and its manufacturing method, and LED chip

Abstract

The present invention provides a semiconductor epitaxial structure and a manufacturing method thereof, and an LED chip, comprising stacking an N-type semiconductor layer, a gate-eliminating layer, an active layer, and a P-type semiconductor layer in sequence on the surface of the substrate, and releasing excess electrons through epitaxial structure design, effectively improving electron concentration, increasing the probability of electron tunneling, improving crystal quality, and reducing the operating voltage of the LED, thereby improving the antistatic ability of the LED.

Description

Technical Field

[0001] The invention relates to the field of light emitting diodes, and in particular to a semiconductor epitaxial structure and a manufacturing method thereof, and an LED chip. Background Art

[0002] Light Emitting Diode (LED) is a semiconductor electronic component that can emit light. LED has the advantages of high efficiency, long life, small size, low power consumption, etc. It can be used in indoor and outdoor white light lighting, screen display, backlight and other fields. In the development of LED industry, gallium nitride (GaN)-based materials are typical representatives of V-III group compound semiconductors. Improving the optoelectronic performance of GaN-based LEDs has become the key to the semiconductor lighting industry.

[0003] Epitaxial wafers are the primary finished products in the LED manufacturing process. Existing GaN-based LED epitaxial wafers include substrates, N-type semiconductor layers, active layers, and P-type semiconductor layers. The substrate is used to provide a growth surface for the epitaxial material, the N-type semiconductor layer is used to provide electrons for compound luminescence, the P-type semiconductor layer is used to provide holes for compound luminescence, and the active layer is used for radiative compound luminescence of electrons and holes.

[0004] However, on the one hand, due to the uneven thickness of the functional layer during the crystal stacking process, the N-type semiconductor layer and the P-type semiconductor layer are intertwined, which will form a thyristor; on the other hand, during the doping process of each functional layer, the low temperature and high doping content can easily cause the thyristor effect. The appearance of the thyristor will increase the conduction voltage of the light-emitting diode (i.e., the dead zone voltage), making it difficult for the light-emitting diode to be lit.

[0005] In view of this, the inventor specially designed a semiconductor epitaxial structure and a manufacturing method thereof, and an LED chip, and this case was thus generated. Summary of the invention

[0006] The object of the present invention is to provide a semiconductor epitaxial structure and a manufacturing method thereof, and an LED chip, so as to solve the problems caused by the thyristor effect in the LED chip.

[0007] In order to achieve the above object, the technical solution adopted by the present invention is as follows:

[0008] A semiconductor epitaxial structure, comprising:

[0009] substrate;

[0010] An N-type semiconductor layer, a gate-eliminating layer, an active layer, and a P-type semiconductor layer are sequentially stacked on the surface of the substrate; the gate-eliminating layer comprises an n-type doped semiconductor layer.

[0011] Preferably, the brake elimination layer comprises a non-uniform n-type doped semiconductor layer.

[0012] Preferably, the n-type doping concentration of the elimination brake layer gradually increases or decreases or changes in a gradient along a first direction; and the highest doping concentration of the elimination brake layer along the first direction is greater than the n-type doping concentration of the N-type semiconductor layer; the first direction is perpendicular to the substrate and points from the substrate to the N-type semiconductor layer.

[0013] Preferably, a shallow well layer is provided between the gate elimination layer and the active layer, and the shallow well layer comprises a plurality of sub-shallow well layers stacked in sequence along the first direction.

[0014] Preferably, the lattice constant of each of the sub-shallow well layers increases along the first direction, and the lattice constant of the sub-shallow well layer adjacent to the active layer is lower than the lattice constant of the active layer; the energy band of each of the sub-shallow well layers decreases along the first direction, and the energy band of the sub-shallow well layer adjacent to the active layer is higher than the energy band of the active layer.

[0015] Preferably, the sub-shallow well layer is composed of alternating potential barriers and potential wells, and the lattice constant of the elimination layer is smaller than the lattice constant of the potential well of the first sub-shallow well layer along the first direction, and the energy band of the elimination layer is larger than the energy band of the potential well of the first sub-shallow well layer along the first direction.

[0016] Preferably, the active layer is formed by alternately cyclic barrier layers and potential well layers, and the band gap energy of the potential well layer is lower than the band gap energy of the barrier layer.

[0017] Preferably, the n-type doping concentration of the gate elimination layer is 1×10 17 ~1x10 20 cm -3 .

[0018] Preferably, the brake elimination layer comprises an n-type doped GaN layer, an AlGaN layer, an AlGaInN layer, a GaInN layer, or an AlInN layer.

[0019] Preferably, the number of layers of the sub-shallow well layer is 1-20, including endpoint values.

[0020] Preferably, the thickness of the brake elimination layer does not exceed 100 nm.

[0021] Preferably, at least a buffer layer and an unintentionally doped layer are sequentially provided between the substrate and the N-type semiconductor layer along the first direction.

[0022] Preferably, an electron blocking layer is further provided between the active layer and the P-type semiconductor layer.

[0023] The present invention also provides a method for manufacturing a semiconductor epitaxial structure, the method comprising the following steps:

[0024] Step S01, providing a substrate;

[0025] Step S02, sequentially growing an N-type semiconductor layer, a gate-eliminating layer, a shallow well layer, an active layer, and a P-type semiconductor layer on the surface of the substrate; the gate-eliminating layer includes an n-type doped semiconductor layer;

[0026] Further, the gate elimination layer comprises a non-uniform n-type doped semiconductor layer;

[0027] The n-type doping concentration of the elimination gate layer increases gradually or decreases gradually or changes in a gradient along a first direction; and the highest doping concentration of the elimination gate layer along the first direction is greater than the n-type doping concentration of the N-type semiconductor layer; the first direction is perpendicular to the substrate and points from the substrate to the N-type semiconductor layer;

[0028] The shallow well layer comprises a plurality of sub-shallow well layers stacked in sequence along the first direction, the lattice constant of each of the sub-shallow well layers increases along the first direction, and the lattice constant of the sub-shallow well layer adjacent to the active layer is lower than the lattice constant of the active layer; the energy band of each of the sub-shallow well layers decreases along the first direction, and the energy band of the sub-shallow well layer adjacent to the active layer is higher than the energy band of the active layer;

[0029] Moreover, each of the sub-shallow well layers is composed of alternating potential barriers and potential wells, and the lattice constant of the elimination layer is smaller than the lattice constant of the potential well of the first sub-shallow well layer along the first direction, and the energy band of the elimination layer is larger than the energy band of the potential well of the first sub-shallow well layer along the first direction.

[0030] The present invention also provides an LED chip, the LED chip comprising:

[0031] The semiconductor epitaxial structure described in any one of the above items;

[0032] An N-type electrode, wherein the N-type electrode forms an ohmic contact with the N-type semiconductor layer;

[0033] A P-type electrode forms an ohmic contact with the P-type semiconductor layer.

[0034] Through the above technical solutions, it can be known that the semiconductor epitaxial structure provided by the present invention has a gate-eliminating layer between the N-type semiconductor layer and the active layer, and the gate-eliminating layer includes an n-type doped semiconductor layer. Furthermore, the gate-eliminating layer includes a non-uniform n-type doped semiconductor layer. Among them, the n-type doping concentration of the gate-eliminating layer gradually increases or decreases or changes in a gradient along the first direction; and the maximum doping concentration of the gate-eliminating layer along the first direction is greater than the n-type doping concentration of the N-type semiconductor layer. Thereby, the excess electrons are released, the electron concentration is effectively increased, the probability of electron tunneling is increased, the crystal quality is improved, and the operating voltage of the LED is reduced, thereby improving the antistatic ability of the LED.

[0035] Further, by setting: a shallow well layer is provided between the gate elimination layer and the active layer, the shallow well layer includes a plurality of sub-shallow well layers stacked in sequence along the first direction; the lattice constant of each sub-shallow well layer increases along the first direction, and the lattice constant of the sub-shallow well layer adjacent to the active layer is lower than the lattice constant of the active layer; the energy band of each sub-shallow well layer decreases along the first direction, and the energy band of the sub-shallow well layer adjacent to the active layer is higher than the energy band of the active layer. At the same time, each sub-shallow well layer is composed of alternately cyclic potential barriers and potential wells, and the lattice constant of the gate elimination layer is smaller than the lattice constant of the potential well of the first sub-shallow well layer along the first direction, and the energy band of the gate elimination layer is larger than the energy band of the potential well of the first sub-shallow well layer along the first direction. The V-Pits structure in the active layer can be effectively opened. On the one hand, the density and opening size of the V-Pits structure can be controlled, and the internal quantum efficiency of the active layer can be improved, thereby improving the LED characteristics. In addition, through the above arrangement, the extension of the V-Pits structure can be effectively suppressed, and while the radiation recombination efficiency of the active layer (i.e., the external quantum efficiency) is improved, the LED leakage channel is reduced, thereby improving the LED electrical performance. Furthermore, through the above arrangement, the stress of the active layer and the dislocations of the underlying layer can be further released.

[0036] It can be seen from the above technical solutions that the method for manufacturing a semiconductor epitaxial structure provided by the present invention, while achieving the beneficial effects of the above semiconductor epitaxial structure, has a simple and convenient manufacturing process and is easy to produce.

[0037] It can be seen from the above technical solutions that the LED chip provided by the present invention is obtained on the basis of the above semiconductor epitaxial structure. Therefore, while it has the beneficial effects of the above semiconductor epitaxial structure, its manufacturing process is simple and convenient, and it is easy to produce. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0039] Figure 1 A schematic diagram of the structure of a semiconductor epitaxial structure provided by an embodiment of the present invention;

[0040] Figure 2 A schematic diagram showing the variation of the n-type doping concentration of the gate elimination layer with the thickness provided by an embodiment of the present invention;

[0041] Figures 3 to 10 A schematic diagram showing the variation of the n-type doping concentration of the gate elimination layer with the thickness provided by another embodiment of the present invention;

[0042] Explanation of symbols in the figure: 1. substrate, 2. buffer layer, 3. unintentionally doped layer, 4. N-type semiconductor layer, 5. gate elimination layer, 6. sub-shallow well layer, 6.1. potential barrier, 6.2. potential well, 7. active layer, 8. electron blocking layer, 9. P-type semiconductor layer. DETAILED DESCRIPTION

[0043] To make the content of the present invention clearer, the content of the present invention is further described below in conjunction with the accompanying drawings. The present invention is not limited to this specific embodiment. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0044] A semiconductor epitaxial structure, comprising:

[0045] Substrate 1;

[0046] An N-type semiconductor layer 4, a gate-eliminating layer 5, an active layer 7, and a P-type semiconductor layer 9 are sequentially stacked on the surface of the substrate 1; the gate-eliminating layer 5 includes an n-type doped semiconductor layer.

[0047] In the embodiment of the present invention, the gate elimination layer 5 includes a non-uniform n-type doped semiconductor layer.

[0048] It is worth mentioning that the type of substrate 1 is not limited in the semiconductor epitaxial structure of this embodiment. For example, the substrate 1 can be but not limited to a sapphire substrate, a silicon substrate, etc. In addition, the specific material types of the N-type semiconductor layer 4, the active layer 7, and the P-type semiconductor layer 9 are also not limited in the semiconductor epitaxial structure of this embodiment. For example, the N-type semiconductor layer can be but not limited to a gallium nitride layer, and correspondingly, the P-type semiconductor layer can be but not limited to a gallium nitride layer.

[0049] In an embodiment of the present invention, the n-type doping concentration of the elimination layer 5 gradually increases or decreases or changes in a gradient along the first direction; and the maximum doping concentration of the elimination layer 5 along the first direction is greater than the n-type doping concentration of the N-type semiconductor layer 4; the first direction is perpendicular to the substrate 1 and points from the substrate 1 to the N-type semiconductor layer 4.

[0050] In the embodiment of the present invention, a shallow well layer is provided between the gate elimination layer 5 and the active layer 7 , and the shallow well layer includes a plurality of sub-shallow well layers 6 stacked in sequence along a first direction.

[0051] It is worth mentioning that in the embodiment of the present invention, the number of the sub-shallow well layers is preferably two, but this is not a limitation to the present invention.

[0052] In the embodiment of the present invention, the lattice constant of each sub-shallow well layer 6 increases along the first direction, and the lattice constant of the sub-shallow well layer 6 adjacent to the active layer 7 is lower than the lattice constant of the active layer 7; the energy band of each sub-shallow well layer 6 decreases along the first direction, and the energy band of the sub-shallow well layer 6 adjacent to the active layer 7 is higher than the energy band of the active layer 7.

[0053] In an embodiment of the present invention, the sub-shallow well layer 6 is composed of alternating potential barriers 6.1 and potential wells 6.2, and the lattice constant of the elimination layer 5 is smaller than the lattice constant of the potential well 6.2 of the first sub-shallow well layer 6 along the first direction, and the energy band of the elimination layer 5 is larger than the energy band of the potential well 6.2 of the first sub-shallow well layer 6 along the first direction.

[0054] In the embodiment of the present invention, the active layer 7 is composed of alternately cyclic barrier layers and potential well layers, and the band gap energy of the potential well layer is lower than the band gap energy of the barrier layer.

[0055] In the embodiment of the present invention, the n-type doping concentration of the gate elimination layer 5 is 1×10 17 ~1x10 20 cm -3 .

[0056] In the embodiment of the present invention, the gate-eliminating layer 5 includes an n-type doped GaN layer, an AlGaN layer, an AlGaInN layer, a GaInN layer, or an AlInN layer.

[0057] In the embodiment of the present invention, the number of sub-shallow well layers 6 is 1-20, including endpoint values.

[0058] In the embodiment of the present invention, the thickness of the gate-eliminating layer does not exceed 100 nm.

[0059] In the embodiment of the present invention, at least a buffer layer 2 and an unintentionally doped layer 3 are sequentially disposed between the substrate 1 and the N-type semiconductor layer 4 along the first direction.

[0060] In the embodiment of the present invention, an electron blocking layer 8 is further provided between the active layer 7 and the P-type semiconductor layer 9 .

[0061] The embodiment of the present invention further provides a method for manufacturing a semiconductor epitaxial structure, the manufacturing method comprising the following steps:

[0062] Step S01, providing a substrate 1;

[0063] Step S02, growing an N-type semiconductor layer 4, a gate-eliminating layer 5, a shallow well layer, an active layer 7, and a P-type semiconductor layer 9 on the surface of the substrate 1 in sequence; the gate-eliminating layer 5 comprises an n-type doped semiconductor layer;

[0064] Further, the gate elimination layer 5 comprises a non-uniform n-type doped semiconductor layer;

[0065] The n-type doping concentration of the brake elimination layer 5 gradually increases or decreases or changes in a gradient along the first direction; and the highest doping concentration of the brake elimination layer 5 along the first direction is greater than the n-type doping concentration of the N-type semiconductor layer 4; the first direction is perpendicular to the substrate 1 and points from the substrate 1 to the N-type semiconductor layer 4;

[0066] The shallow well layer includes a plurality of sub-shallow well layers 6 stacked in sequence along a first direction, the lattice constant of each sub-shallow well layer 6 increases along the first direction, and the lattice constant of the sub-shallow well layer 6 adjacent to the active layer 7 is lower than the lattice constant of the active layer 7; the energy band of each sub-shallow well layer 6 decreases along the first direction, and the energy band of the sub-shallow well layer 6 adjacent to the active layer 7 is higher than the energy band of the active layer 7;

[0067] Moreover, each sub-shallow well layer 6 is composed of alternating potential barriers 6.1 and potential wells 6.2, and the lattice constant of the elimination layer is smaller than the lattice constant of the potential well 6.2 of the first sub-shallow well layer 6 along the first direction, and the energy band of the elimination layer is larger than the energy band of the potential well 6.2 of the first sub-shallow well layer 6 along the first direction.

[0068] Figure 2 It is a schematic diagram showing the variation of the n-type doping concentration of the gate elimination layer provided by an embodiment of the present invention with the thickness, wherein the abscissa represents the thickness and the ordinate represents the n-type doping concentration.

[0069] Figure 3-10 FIG. 1 is a schematic diagram showing the variation of the n-type doping concentration of the gate elimination layer with the thickness provided in other embodiments of the present invention, wherein the abscissa represents the thickness and the ordinate represents the n-type doping concentration. Fig.10 The doping gradient method shown. It should be noted that Figure 2-10 This is just an example and is not intended to limit the present invention.

[0070] The embodiment of the present invention further provides an LED chip, the LED chip comprising:

[0071] A semiconductor epitaxial structure according to any of the above;

[0072] An N-type electrode, the N-type electrode forms an ohmic contact with the N-type semiconductor layer 4;

[0073] A P-type electrode, the P-type electrode forms an ohmic contact with the P-type semiconductor layer 9 .

[0074] It can be known from the above technical scheme that the semiconductor epitaxial structure provided by the present invention has a gate elimination layer 5 between the N-type semiconductor layer 4 and the active layer 7, and the gate elimination layer 5 includes an n-type doped semiconductor layer. Furthermore, the gate elimination layer 5 includes a non-uniform n-type doped semiconductor layer. Among them, the n-type doping concentration of the gate elimination layer 5 gradually increases or decreases or changes in a gradient along the first direction; and the maximum doping concentration of the gate elimination layer 5 along the first direction is greater than the n-type doping concentration of the N-type semiconductor layer 4. Thereby, the excess electrons are released, the electron concentration is effectively increased, the probability of electron tunneling is increased, the crystal quality is improved, and the operating voltage of the LED is reduced, thereby improving the antistatic ability of the LED.

[0075] Further, by setting: a shallow well layer is provided between the gate elimination layer 5 and the active layer 7, and the shallow well layer includes a plurality of sub-shallow well layers 6 stacked in sequence along the first direction; the lattice constant of each sub-shallow well layer 6 increases along the first direction, and the lattice constant of the sub-shallow well layer 6 adjacent to the active layer 7 is lower than the lattice constant of the active layer 7; the energy band of each sub-shallow well layer 6 decreases along the first direction, and the energy band of the sub-shallow well layer 6 adjacent to the active layer 7 is higher than the energy band of the active layer 7. At the same time, each sub-shallow well layer 6 is composed of alternately cyclic potential barriers 6.1 and potential wells 6.2, and the lattice constant of the gate elimination layer 5 is smaller than the lattice constant of the potential well 6.2 of the first sub-shallow well layer 6 along the first direction, and the energy band of the gate elimination layer 5 is larger than the energy band of the potential well 6.2 of the first sub-shallow well layer 6 along the first direction. The V-Pits structure in the active layer 7 can be effectively opened. On the one hand, the density and opening size of the V-Pits structure can be controlled, and the internal quantum efficiency of the active layer 7 can be improved, thereby improving the LED characteristics. In addition, through the above arrangement, the extension of the V-Pits structure can be effectively suppressed, and while the radiation recombination efficiency of the active layer 7 (i.e., the external quantum efficiency) is improved, the LED leakage channel is reduced, thereby improving the LED electrical performance. Furthermore, through the above arrangement, the stress of the active layer 7 and the dislocations of its underlying layer can be further released.

[0076] It can be seen from the above technical solutions that the method for manufacturing a semiconductor epitaxial structure provided by the present invention, while achieving the beneficial effects of the above semiconductor epitaxial structure, has a simple and convenient manufacturing process and is easy to produce.

[0077] It can be seen from the above technical solutions that the LED chip provided by the present invention is obtained on the basis of the above semiconductor epitaxial structure. Therefore, while it has the beneficial effects of the above semiconductor epitaxial structure, its manufacturing process is simple and convenient, and it is easy to produce.

[0078] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0079] It should also be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises", "comprising" or any other variants thereof are intended to cover non-exclusive inclusion, so that an article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such article or device. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the existence of other identical elements in the article or device including the above elements.

[0080] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A semiconductor epitaxial structure, characterized in that: include: substrate; An N-type semiconductor layer, a gate-eliminating layer, an active layer, and a P-type semiconductor layer are sequentially stacked on the surface of the substrate; The gate elimination layer comprises an n-type doped semiconductor layer; A shallow well layer is provided between the gate elimination layer and the active layer, wherein the shallow well layer comprises a plurality of sub-shallow well layers stacked in sequence along a first direction, wherein the first direction is perpendicular to the substrate and points from the substrate to the N-type semiconductor layer; The lattice constant of each of the sub-shallow well layers increases along the first direction, and the lattice constant of the sub-shallow well layer adjacent to the active layer is lower than the lattice constant of the active layer; the energy band of each of the sub-shallow well layers decreases along the first direction, and the energy band of the sub-shallow well layer adjacent to the active layer is higher than the energy band of the active layer; Each of the sub-shallow well layers is composed of potential barriers and potential wells that are alternately cycled, and the lattice constant of the elimination layer is smaller than the lattice constant of the potential well of the first sub-shallow well layer along the first direction, and the energy band of the elimination layer is larger than the energy band of the potential well of the first sub-shallow well layer along the first direction; The gate elimination layer includes a non-uniform n-type doped semiconductor layer.

2. The semiconductor epitaxial structure according to claim 1, characterized in that: The n-type doping concentration of the elimination gate layer gradually increases or decreases or changes in a gradient along a first direction; and the highest doping concentration of the elimination gate layer along the first direction is greater than the n-type doping concentration of the N-type semiconductor layer.

3. The semiconductor epitaxial structure according to claim 1, characterized in that: The n-type doping concentration of the gate elimination layer is 1×10 17 ~1x10 20 cm -3 .

4. The semiconductor epitaxial structure according to claim 1, characterized in that: The brake elimination layer includes an n-type doped GaN layer, an AlGaN layer, an AlGaInN layer, a GaInN layer, or an AlInN layer.

5. The semiconductor epitaxial structure according to claim 1, characterized in that: The number of layers of the sub-shallow well layer is 1-20, including endpoint values.

6. The semiconductor epitaxial structure according to claim 1, characterized in that: The thickness of the brake elimination layer does not exceed 100 nm.

7. A method for manufacturing a semiconductor epitaxial structure according to any one of claims 1 to 6, characterized in that: The production method comprises the following steps: Step S01, providing a substrate; Step S02, sequentially growing an N-type semiconductor layer, a gate-eliminating layer, a shallow well layer, an active layer, and a P-type semiconductor layer on the surface of the substrate; the gate-eliminating layer includes an n-type doped semiconductor layer; Further, the gate elimination layer comprises a non-uniform n-type doped semiconductor layer; The n-type doping concentration of the elimination gate layer increases gradually or decreases gradually or changes in a gradient along a first direction; and the highest doping concentration of the elimination gate layer along the first direction is greater than the n-type doping concentration of the N-type semiconductor layer; the first direction is perpendicular to the substrate and points from the substrate to the N-type semiconductor layer; The shallow well layer comprises a plurality of sub-shallow well layers stacked in sequence along the first direction, the lattice constant of each of the sub-shallow well layers increases along the first direction, and the lattice constant of the sub-shallow well layer adjacent to the active layer is lower than the lattice constant of the active layer; the energy band of each of the sub-shallow well layers decreases along the first direction, and the energy band of the sub-shallow well layer adjacent to the active layer is higher than the energy band of the active layer; Moreover, each of the sub-shallow well layers is composed of alternating potential barriers and potential wells, and the lattice constant of the elimination layer is smaller than the lattice constant of the potential well of the first sub-shallow well layer along the first direction, and the energy band of the elimination layer is larger than the energy band of the potential well of the first sub-shallow well layer along the first direction.

8. An LED chip, characterized in that: include; The semiconductor epitaxial structure according to any one of claims 1 to 6; An N-type electrode, wherein the N-type electrode forms an ohmic contact with the N-type semiconductor layer; A P-type electrode forms an ohmic contact with the P-type semiconductor layer.

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