Interconnect structure for redistribution layer and semiconductor package

Abstract

The present invention discloses an interconnect structure for a redistribution layer, comprising: a middle through-hole pad; one or a cluster of upper conductive vias, adjacent to the middle through-hole pad, and electrically coupling the middle through-hole pad to the upper through-hole pad; and a lower conductive via, electrically coupling the middle through-hole pad to the lower circuit pad, wherein the lower conductive via is arranged in a horseshoe-shaped through-hole region extending along the periphery of the middle through-hole pad. Therefore, in the present invention, the upper conductive via does not overlap with the lower conductive via, thereby avoiding stress transmission in the vertical direction, reducing the burden on circuit designers, and significantly reducing the operating time.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an interconnection structure for a redistribution layer and a semiconductor package. Background Art

[0002] In recent years, as the design complexity increases, the industry has proposed advanced packaging technologies for system integration. For example, fan-out wafer-level chip-scale package (FO-WLCSP) provides a promising alternative with small size, better signal-to-noise ratio and improved thermal characteristics.

[0003] As known in the art, micro-bumps and redistribution layers (RDL) are used in multi-chip FO-WLCSP to connect adjacent chips and to the input / output (I / O) pads on the fan-out chip. RDL can be the upper metal layer of the chip, and multiple chips share the same RDL in the multi-chip FO-WLCSP. In modern IC design, I / O pads are usually placed along the border of the chip, and RDL is used to redistribute I / O pads to controlled collapse chip connection (controlled collapse chip connection, C4) bump pads, or to connect I / O pads between different chips. I / O pads can be redistributed to the fan-out area outside the chip to increase the number of pins.

[0004] The C4 bump is the interface between the fan-out chip package and the circuit substrate (e.g., the package substrate). As is known to all, the C4 bump is usually subjected to greater stress due to the mismatch of the coefficient of thermal expansion (or CTE (coefficient of thermal expansion)). Therefore, the size and spacing of the C4 bump are larger than the size and spacing of the I / O pad or microbump. This results in that the C4 bump position may be different from its corresponding I / O pad or microbump position.

[0005] Typically, there are thousands of relative positions of pads to bumps (i.e., I / O pads to C4 bump pads), so thousands of via and pad interconnection patterns are generated during the design process of RDL routing, which inevitably increases the runtime and makes the RDL circuit design process cumbersome. Summary of the invention

[0006] In view of this, the present invention provides an interconnect structure for a redistribution layer and a semiconductor package to solve the above problems.

[0007] According to a first aspect of the present invention, an interconnect structure for a redistribution layer is disclosed, comprising:

[0008] Middle through hole pad;

[0009] one or a cluster of upper conductive vias adjacent to the middle via pad and electrically coupling the middle via pad to the upper via pad; and

[0010] A lower conductive via electrically couples the middle via pad with the lower circuit pad, wherein the lower conductive via is arranged in a horseshoe-shaped via region extending along a periphery of the middle via pad.

[0011] According to a second aspect of the present invention, a semiconductor package is disclosed, comprising:

[0012] at least one semiconductor die;

[0013] a molding compound surrounding the semiconductor die; and

[0014] A redistribution layer is disposed on a lower surface of the molding compound, wherein the at least one semiconductor die is electrically connected to an interconnect structure of the redistribution layer, wherein the interconnect structure comprises:

[0015] Middle through hole pad;

[0016] one or a cluster of upper conductive vias adjacent to the middle via pad and electrically coupling the middle via pad to the upper via pad; and

[0017] A lower conductive via electrically couples the middle via pad with the lower circuit pad, wherein the lower conductive via is arranged in a horseshoe-shaped via region extending along a periphery of the middle via pad.

[0018] According to a third aspect of the present invention, an interconnect structure for a redistribution layer is disclosed, comprising:

[0019] Middle through hole pad;

[0020] one or a cluster of upper conductive vias adjacent to the middle via pad and electrically coupling the middle via pad to the upper via pad; and

[0021] A lower conductive via electrically couples the middle via pad to the lower circuit pad, wherein the one or a cluster of upper conductive vias is disposed within a projection area of ​​the upper via pad on the middle via pad, wherein the lower conductive via is arranged on a remaining portion of the middle via pad outside the projection area and does not overlap with the upper conductive via cluster.

[0022] The interconnect structure for the redistribution layer of the present invention has the lower conductive via arranged in a horseshoe-shaped via region extending along the periphery of the middle via pad. Therefore, the upper conductive via in the present invention does not overlap with the lower conductive via, thereby avoiding the transmission of stress in the vertical direction, which can reduce the burden on circuit designers and significantly reduce the operating time; and the above-mentioned method of the present invention can facilitate the layout design between the upper conductive via and the lower conductive via in the redistribution layer. When the upper conductive via or the lower conductive via needs to be changed in position due to design requirements, the position of the upper conductive via or the lower conductive via can be changed by rotation, thereby meeting different design requirements and having better design elasticity and flexibility. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a schematic cross-sectional view illustrating an exemplary fan-out package according to one embodiment of the present invention;

[0024] Figure 2 is a top-down perspective view of an exemplary interconnect structure according to an embodiment of the present invention, the interconnect structure including an intermediate via land pad, one or a cluster of upper conductive vias adjacent to the intermediate via land pad, and a lower conductive via;

[0025] Figure 3 It is shown Figure 2 A schematic cross-sectional view of the relative positions of the middle via pad, the upper conductive via, and the lower conductive via in FIG.

[0026] Figure 4 yes Figure 2 A perspective side view of an exemplary interconnect structure in FIG. 1 ; and

[0027] Figures 5 to 7 An exemplary rotation operation of lower conductive vias arranged within a via region to avoid via overlap is shown according to some embodiments of the present invention. DETAILED DESCRIPTION

[0028] The following description is the best mode of implementing the present invention. This description is made to illustrate the general principles of the present invention and should not be considered as limiting. The scope of the present invention is determined by the appended claims.

[0029] Hereinafter, the inventive concept is fully described with reference to the accompanying drawings, in which exemplary embodiments of the inventive concept are shown. According to the following exemplary embodiments, the advantages and features of the inventive concept and the methods for realizing them will become apparent, and the embodiments will be described in more detail with reference to the accompanying drawings. However, it should be noted that the inventive concept is not limited to the following exemplary embodiments and can be implemented in various forms. Therefore, exemplary embodiments are provided only to disclose the inventive concept and to make those skilled in the art aware of the categories of the inventive concept. Moreover, the drawings shown are only schematic and non-restrictive. In the drawings, for the purpose of illustration, the sizes of some elements may be enlarged and not drawn to scale. In the practice of the present invention, the sizes and relative sizes do not correspond to the actual sizes.

[0030] The terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used herein, the singular terms "one", "an" and "the" are also intended to include plural forms, unless the context clearly indicates otherwise. As used herein, the term "and / or" includes any and all combinations of one or more associated listed items. It should be understood that when an element is referred to as "connected" or "contacted" to another element, it can be directly connected or contacted to another element, or there can be an intermediate element.

[0031] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it can be directly on the other element, or there can be intermediate elements. In contrast, the term "directly" refers to the absence of intermediate elements. It should be understood that when used herein, the terms "include", and / or "comprise" specify the presence of stated features, integers, steps, operations, elements, and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or combinations thereof.

[0032] One or more embodiments of the present invention will now be described with reference to the accompanying drawings, wherein like reference numerals are used to refer to like elements throughout the text, and the structures shown therein are not necessarily drawn to scale. Throughout the specification, the terms "die", "semiconductor chip" and "semiconductor die" may be used interchangeably.

[0033] Please refer to Figure 1 . Figure 1 is a schematic cross-sectional view showing an exemplary fan-out package according to one embodiment of the present invention. Figure 1As shown, a fan-out package 1 (which may be referred to as a semiconductor package) may include at least two semiconductor die 11 and 12 electrically coupled to a redistribution layer (RDL) 20. The RDL (or RDL interposer) may be defined by adding metal layers and dielectric layers on the surface of the wafer to reroute the I / O layout to a looser pitch size. This redistribution (layer) requires a thin film polymer (e.g., benzocyclobutene (BCB), polyimide (PI) or other organic polymers and a metallization material (e.g., aluminum (Al) or copper (Cu)) to reroute the peripheral pads to an area array configuration.

[0034] According to an embodiment of the present invention, for example, RDL 20 may include at least one dielectric layer 201 and at least one metal layer 202. Dielectric layer 201 may include an inorganic material such as silicon nitride, silicon oxide, or the like, but is not limited thereto. According to an embodiment of the present invention, dielectric layer 201 may include a polymer material, but is not limited thereto. Metal layer 202 may include aluminum, copper, tungsten, titanium, titanium nitride, etc. It should be understood that metal layer 202 may include multiple layers of metal traces, and dielectric layer 201 may include multiple layers of dielectric laminates.

[0035] According to an embodiment of the present invention, the die 11 and 12 are flipped so that the active surfaces 11a and 12a directly face the RDL 20. On the active surface 11a of the die 11, a plurality of input / output (I / O) pads 111 may be provided, for example, along the periphery of the active surface 11a thereof. Similarly, on the active surface 12a of the die 12, a plurality of I / O pads 121 may be provided, for example, along the periphery of the active surface thereof. The active surfaces 11a and 12a of the die 11 and 12 may be conformally covered by a passivation layer 130.

[0036] According to an embodiment of the present invention, the die 11 and 12 may include terminals 112 and 122, which include but are not limited to metal bumps or micro bumps respectively disposed on the I / O pads 111 and 121, which are disposed on the flipped active surfaces 11a and 12a. According to an embodiment of the present invention, the terminals 112 and 122 may include a bump pitch of about 20-50 microns, but are not limited thereto. Optionally, a planarization layer 210 such as a dielectric layer or a polymer layer may be applied on the passivation layer 130 and may surround the terminals 112 and 122.

[0037] According to an embodiment of the present invention, the die 11 and 12 may be surrounded and supported by a sealant such as a molding compound 30. The molding compound 30 may have a lower surface 30a flush with the lower surface 210a of the planarization layer 210. The molding compound 30 may have an upper surface 30b flush with the rear surfaces 11b and 12b of the die 11 and 12. The molding compound 30 may be subjected to a curing process during a chip-scale packaging process. According to an embodiment of the present invention, the molding compound 30 may include a mixture of an epoxy resin and a silicon dioxide filler, but is not limited thereto.

[0038] The RDL 20 may include multi-layer conductive vias, such as V1-V3, via pads (such as P2, P3), multi-layer conductive traces (such as T2 and T3), and bump pads BP to fan out I / O pads 111 and 121 to C4 bumps SB on the lower surface of the RDL 20 to have a looser pitch (such as Micrometers). C4 bumps SB are formed on the bump pads BP respectively. Figure 1 Only three layers of conductive vias (eg, V1-V3) and two layers of via pads (eg, P2, P3) are shown. The vias and pads may vary depending on design requirements.

[0039] For example, in Figure 1 In the embodiment, the RDL 20 may include a universal interconnect structure IS, which includes a middle via pad Pn, one or a cluster of upper conductive vias Vn-1 adjacent to the middle via pad Pn and electrically coupling the middle via pad Pn to the upper via pad Pn-1, and a lower conductive via Vn electrically coupling the middle via pad Pn to the lower circuit pad Pn+1. In some embodiments, the lower circuit pad Pn+1 may be a bump pad, but is not limited thereto.

[0040] According to an embodiment of the present invention, when implementing RDL circuit design based on a favorable fan-out wafer-level chip-scale platform, after research by the inventors, it is considered that the following conditions need to be considered or met. First, considering electromigration (EM) and IR performance, in the interconnect structure IS, there is more than one through hole (criterion A) relative to each adjacent through hole pad (or bump pad). For example, one or a cluster of upper conductive vias Vn-1 may include through holes, and the lower conductive via Vn may include For example, the number of the lower conductive vias Vn may be 1, 2, 3 or more. Second, to avoid stress transmission in the vertical direction, one or a cluster of upper conductive vias Vn-1 do not overlap with the lower conductive vias Vn (criterion B).

[0041] Please refer to Figures 2 to 4 . Figure 2 is a top perspective view illustrating an exemplary interconnect structure including a middle via pad, one or a cluster of upper conductive vias adjacent to the middle via pad, and a lower conductive via in accordance with an embodiment of the present invention. Figure 3 It shows Figure 2 Schematic cross-sectional view of the relative positions of the middle via pad, the upper conductive via and the lower conductive via in FIG. Figure 4 yes Figure 2 A side perspective view of an exemplary interconnect structure in which like numbers or labels represent similar layers, regions or elements.

[0042] For the sake of clarity, the dielectric layer or polymer layer of the exemplary interconnect structure is ignored. It should be understood that the shape of the via pad is only for illustration purposes. In some embodiments, the via pad can have a circular, rectangular, square, polygonal, elliptical or irregular shape, but is not limited thereto.

[0043] like Figures 2 to 4 As shown, according to one embodiment, for example, the universal interconnect structure IS includes an intermediate via pad Pn, one or a cluster of upper conductive vias Vn-1 adjacent to the intermediate via pad Pn and electrically coupling the intermediate via pad Pn to the upper via pad Pn-1, and a lower conductive via Vn electrically coupling the intermediate via pad Pn to the lower circuit pad Pn+1. Figure 4 It is also shown that an exemplary C4 bump SB may be disposed on a bump pad extending from the lower circuit pad Pn+1.

[0044] It should be understood that, according to various embodiments, the middle via pad Pn may include a circular, rectangular, square, polygonal, elliptical or irregular shape. It should be understood that, according to various embodiments, the upper via pad Pn-1 may include a circular, rectangular, square, polygonal, elliptical or irregular shape. It should be understood that, according to various embodiments, the middle via pad Pn may have a shape different from that of the upper via pad Pn-1. It should be understood that, according to various embodiments, the middle via pad Pn and the upper via pad Pn-1 may have the same shape.

[0045] According to one embodiment of the present invention, for example, both the middle via pad Pn and the upper via pad Pn-1 may have a circular shape and may be concentric with respect to the central axis AX when viewed from above. One or a cluster of upper conductive vias Vn-1 may be disposed within a projection area PPR of radius r on the middle via pad Pn of radius R. The projection area PPR is substantially equal to the upper surface area of ​​the upper via pad Pn-1. The remainder of the middle via pad Pn located outside the projection area PPR is defined as an annular area RA having a uniform width (equal to Rr), which may be divided into two mirror-symmetrical horseshoe-shaped (or C-shaped or curved strip-shaped) areas by a central dotted line CL intersecting the central axis AX. According to one embodiment of the present invention, one of the two mirror-symmetrical horseshoe-shaped areas (half of the annular area RA) is defined as a via area VAR (indicated by a dotted line). According to an embodiment of the present invention, the lower conductive via Vn is only allowed to be arranged in an imaginary horseshoe-shaped via area VAR, which extends along the circumference of the middle via pad Pn, which is approximately half of the annular area RA, or the horseshoe-shaped via area VAR may be less than or equal to half of the annular area RA (for example, the area of ​​the horseshoe-shaped via area VAR may be less than or equal to half of the area of ​​the annular area RA). The above-mentioned method of the present invention can facilitate the layout design between the upper conductive via and the lower conductive via in the RDL. When the position of the upper conductive via or the lower conductive via needs to be changed due to design requirements, the position of the upper conductive via or the lower conductive via can be changed by rotating as described below, thereby meeting different design requirements and having better design elasticity and flexibility. In one embodiment, the lower conductive via Vn may include a plurality of vias (for example ) to form a lower conductive through-hole array; in addition, the upper conductive through-hole Vn-1 may also be multiple; the lower conductive through-hole or / and the upper conductive through-hole are / is set to be multiple to improve the electrical performance, and at the same time, the multiple lower conductive through-holes and the multiple upper conductive through-holes will not overlap by performing the above-mentioned rotation (for example, they will not overlap when viewed from a top or bottom perspective, or their projections in the vertical direction will not overlap, or their projections in the vertical direction on the middle through-hole pad Pn will not overlap, etc.), so this embodiment meets the demand for improving design flexibility while improving electrical performance. In addition, the multiple lower conductive through-holes can be evenly distributed in the horseshoe-shaped through-hole area VAR to improve electrical performance and make signal transmission more uniform. The multiple upper conductive through-holes can be evenly distributed in the middle through-hole pad Pn to improve electrical performance and make signal transmission more uniform.

[0046] In some cases, when viewed from above, the middle via pad Pn and the upper via pad Pn-1 are not concentric with respect to the central axis AX, and the above criterion B can be satisfied by simply rotating the lower conductive via Vn and the imaginary via area VAR around the central axis AX. For details, please refer to the description of the following embodiments.

[0047] Figure 5 FIG. 4 shows an exemplary rotation operation of the lower conductive via Vn arranged in the via region VAR. Figure 5 In the embodiment, one or a cluster of upper conductive vias Vn-1 includes two conductive vias, and the lower conductive vias Vn include five conductive vias. Figure 5 As shown, the central axis AX of the upper via pad Pn-1 is offset from the central axis AX of the middle via pad Pn. To avoid overlap between the lower conductive via Vn and the upper conductive via Vn-1, the lower conductive via Vn is rotated around the central axis AX together with the imaginary via region VAR by performing a rotation operation of VAR.

[0048] Figure 6 Another exemplary rotation operation of the lower conductive via Vn arranged in the via region VAR is shown. Figure 6 In the embodiment, one or a cluster of upper conductive vias Vn-1 may include four conductive vias, and the lower conductive via Vn may include six conductive vias. The middle via pad Pn and the upper via pad Pn-1 may have a rectangular shape. Figure 6 As shown, the central axis AX of the upper via pad Pn-1 and the middle via pad Pn is offset. In order to avoid overlap between the lower conductive via Vn and the upper conductive via Vn-1, the lower conductive via Vn and the middle via pad Pn are rotated around the central axis AX by performing a rotation operation of VAR. Therefore, in this embodiment, Figure 2 The annular area RA shown may be a circular ring, a square ring or other ring shapes. Figure 2 The horseshoe-shaped through hole area VAR shown may also be a semicircular ring, or half of a square ring, or half of a ring of other shapes (of course, as mentioned above, it may also be less than or equal to half), so the horseshoe-shaped through hole area VAR may also be half of a square ring or a ring of other shapes. The horseshoe-shaped through hole area VAR may be less than or equal to half of the annular area RA, so that it is easier to avoid the overlap between the lower conductive through hole Vn and the upper conductive through hole Vn-1 when performing the rotation operation of VAR, which has better design flexibility and layout flexibility, and facilitates the design of the through hole and the layout of the wiring.

[0049] Figure 7 FIG. 4 shows another exemplary rotation operation of the lower conductive via Vn arranged in the via region VAR. Figure 7 , the cluster of upper conductive vias Vn-1 may include four conductive vias, and the lower conductive via Vn may include five conductive vias. The middle via pad Pn may have a circular shape, and the upper via pad Pn-1 may have a rectangular shape. Figure 7As shown, the central axis AX of the upper via pad Pn-1 is offset from the central axis AX of the middle via pad Pn. To avoid overlap between the lower conductive via Vn and the upper conductive via Vn-1, the lower conductive via Vn is rotated around the central axis AX together with the imaginary via region VAR by performing a rotation operation of VAR.

[0050] The use of the present invention is advantageous because the burden on circuit designers can be reduced and run time can be significantly reduced when implementing RDL circuit design by incorporating novel through-hole configurations into a universal interconnect structure. In addition, the novel through-hole configuration in the universal interconnect structure makes it very easy for RDL circuit design to convert between different minimum C4 bump pitch rules (e.g., the current minimum). The C4 bump pitch for fan-out wafer-level chip scale packaging (FO-WLCSP) is 130μm. The C4 bump pitch for CoWoS (Chip-on-Wafer-on-Substrate) technology is 150μm. The present invention provides a flexible RDL circuit design method for different fan-out packaging technologies, which can be applied to different bump pitch requirements, and has better design flexibility and layout flexibility.

[0051] Those skilled in the art will readily observe that many modifications and variations of the apparatus and method can be made while maintaining the teachings of the present invention.Accordingly, the above disclosure should be interpreted as being limited only by the metes and bounds of the appended claims.

Claims

1. An interconnect structure for a redistribution layer, characterized in that: include: Middle through hole pad; a plurality of upper conductive vias adjacent to the middle via pad and electrically coupling the middle via pad to the upper via pad; and A plurality of lower conductive vias electrically couple the middle via pad to the lower circuit pad, The multiple upper conductive vias are arranged in the projection area of ​​the upper through-hole pad on the middle through-hole pad, and the remaining part of the middle through-hole pad outside the projection area is an annular area with uniform width, wherein the multiple lower conductive vias are arranged in a horseshoe-shaped through-hole area extending along the periphery of the middle through-hole pad, the annular area is divided into two mirror-symmetrical horseshoes by a center line, and wherein one of the two mirror-symmetrical horseshoe-shaped areas is defined as the horseshoe-shaped through-hole area.

2. The interconnect structure for a redistribution layer according to claim 1, characterized in that: The middle via pad includes a circular, rectangular, square, polygonal, elliptical or irregular shape; or / and, the upper via pad includes a circular, rectangular, square, polygonal, elliptical or irregular shape.

3. The interconnect structure for a redistribution layer according to claim 2, characterized in that: The middle via pad and the upper via pad have the same or different shapes.

4. The interconnect structure for a redistribution layer according to claim 1, characterized in that: The projected area is equal to the upper surface area of ​​the upper through hole pad.

5. The interconnect structure for a redistribution layer according to claim 1, characterized in that: The lower conductive via electrically couples the middle via pad with the lower circuit pad.

6. The interconnect structure for a redistribution layer according to claim 1, characterized in that: When viewed from above, the middle via pad and the upper via pad are not concentric with respect to the central axis.

7. The interconnect structure for a redistribution layer according to claim 1, characterized in that: The lower conductive via disposed in the horseshoe-shaped via region does not overlap with the upper conductive via.

8. A semiconductor package, characterized in that: include: at least one semiconductor die; Molding compound, surrounding the semiconductor die; as well as A redistribution layer is disposed on a lower surface of the molding compound, wherein the at least one semiconductor die is electrically connected to an interconnect structure of the redistribution layer, wherein the interconnect structure comprises: Middle through hole pad; a plurality of upper conductive vias adjacent to the middle via pad and electrically coupling the middle via pad to the upper via pad; and A plurality of lower conductive vias electrically couple the middle via pad to the lower circuit pad, The multiple upper conductive vias are arranged in the projection area of ​​the upper through-hole pad on the middle through-hole pad, and the remaining part of the middle through-hole pad outside the projection area is an annular area with uniform width, wherein the multiple lower conductive vias are arranged in a horseshoe-shaped through-hole area extending along the periphery of the middle through-hole pad, the annular area is divided into two mirror-symmetrical horseshoes by a center line, and wherein one of the two mirror-symmetrical horseshoe-shaped areas is defined as the horseshoe-shaped through-hole area.

9. An interconnect structure for a redistribution layer, characterized in that: include: Middle through hole pad; a plurality of upper conductive vias adjacent to the middle via pad and electrically coupling the middle via pad to the upper via pad; and A plurality of lower conductive vias electrically couple the middle via pad to the lower circuit pad, The multiple upper conductive vias are arranged in the projection area of ​​the upper through-hole pad on the middle through-hole pad, and the remaining portion of the middle through-hole pad outside the projection area is a ring-shaped area with uniform width, wherein the upper conductive via is arranged in the projection area of ​​the upper through-hole pad on the middle through-hole pad, wherein the lower conductive via is arranged on the remaining portion of the middle through-hole pad outside the projection area and does not overlap with the upper conductive via cluster.

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