Semiconductor structure and method for forming the same

Abstract

This invention relates to the field of semiconductor manufacturing technology, and more particularly to a semiconductor structure and a method for forming the same. The method for forming the semiconductor structure includes the following steps: providing a substrate; etching the substrate to form a trench and an active region located between adjacent trenches, wherein the trench includes a first trench and a second trench located below and communicating with the first trench, and the inner diameter of the first trench is smaller than the inner diameter of the second trench; filling the trench to form a filling layer with air gaps within the trench. This invention reduces interference between adjacent active regions during the operation of the semiconductor structure, mitigates the impact of the hammer effect, and improves the yield and reliability of the semiconductor structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor device commonly used in electronic devices such as computers. It is composed of multiple storage cells, each of which usually includes a transistor and a capacitor. The gate of the transistor is electrically connected to the word line, the source is electrically connected to the bit line, and the drain is electrically connected to the capacitor. The word line voltage on the word line can control the opening and closing of the transistor, so that the data information stored in the capacitor can be read through the bit line, or the data information can be written into the capacitor.

[0003] In semiconductor structures such as DRAM, each active area overlaps with two word lines (i.e., two word lines pass through the same active area). When one word line is activated and repeatedly refreshed, the following two effects will occur: on the one hand, noise or interference will be generated on the other word line passing through the same active area; on the other hand, before the active area adjacent to the activated word line is activated or refreshed, if the refresh frequency of the activated word line is too high, the active area adjacent to the activated word line will become fragile, resulting in charge loss or leakage problems. The above two effects will cause data errors in one or more active areas adjacent to the activated word line, resulting in the so-called row hammer effect.

[0004] Therefore, how to alleviate the hammering effect, reduce the mutual interference between adjacent active areas, and improve the yield and performance reliability of the semiconductor structure is a technical problem that needs to be solved urgently. Summary of the invention

[0005] The present invention provides a semiconductor structure and a method for forming the same, which are used to solve the problem that the semiconductor structure in the prior art is prone to produce a hammering effect, so as to reduce mutual interference between adjacent active areas and improve the yield and performance reliability of the semiconductor structure.

[0006] In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising the following steps:

[0007] providing a substrate;

[0008] Etching the substrate to form grooves and active areas located between adjacent grooves, wherein the grooves include a first groove and a second groove located below the first groove and connected to the first groove, and the inner diameter of the first groove is smaller than the inner diameter of the second groove;

[0009] The groove is filled to form a filling layer with an air gap in the groove.

[0010] Optionally, the specific steps of forming the grooves and the active area between adjacent grooves include:

[0011] forming a mask layer covering the substrate, wherein the mask layer has an opening exposing the substrate;

[0012] Etching the substrate along the opening to form first grooves and first sub-active regions located between adjacent first grooves;

[0013] The substrate is continuously etched along the first groove to form a second groove connected to the first groove and a second sub-active region located between adjacent second grooves below the first groove, wherein an inner diameter of the first groove is smaller than an inner diameter of the second groove, and a width of the first sub-active region is larger than a width of the second sub-active region.

[0014] Optionally, the depth of the first groove is 20% to 30% of the depth of the groove.

[0015] Optionally, before continuing to etch the substrate along the first groove, the method further includes the following steps:

[0016] A sidewall protection layer is formed to cover the sidewall of the first groove.

[0017] Optionally, the thickness of the sidewall protection layer is 1 / 5 to 1 / 4 of the width of the first sub-active region.

[0018] Optionally, the specific step of forming a second groove below the first groove and communicating with the first groove includes:

[0019] Continue etching the substrate along the first groove to form an initial second groove below the first groove and connected to the first groove;

[0020] Oxidizing the sidewall of the initial second groove to form a sidewall oxide layer, wherein the thickness of the sidewall oxide layer is greater than the thickness of the sidewall protection layer;

[0021] The sidewall oxide layer is removed to form the second groove.

[0022] Optionally, the specific steps of removing the sidewall oxide layer include:

[0023] The sidewall oxide layer and the sidewall protection layer are removed simultaneously.

[0024] Optionally, the specific steps of forming a filling layer having an air gap in the groove include:

[0025] The groove is filled with an atomic layer deposition process to form a filling layer with an air gap.

[0026] Optionally, the top surface of the air gap is flush with the bottom surface of the first groove; or,

[0027] A top surface of the air gap is higher than a bottom surface of the first groove.

[0028] In order to solve the above problem, the present invention further provides a semiconductor structure, comprising:

[0029] substrate;

[0030] A groove located in the substrate, the groove comprising a first groove and a second groove located below the first groove and connected to the first groove, and an inner diameter of the first groove is smaller than an inner diameter of the second groove;

[0031] A filling layer is located in the groove, and an air gap is provided in the filling layer;

[0032] The active area is located between adjacent grooves.

[0033] Optionally, the depth of the first groove is 20% to 30% of the depth of the groove.

[0034] Optionally, the top surface of the air gap is flush with the bottom surface of the first groove; or,

[0035] A top surface of the air gap is higher than a bottom surface of the first groove and lower than a top surface of the first groove.

[0036] Optionally, the active area includes:

[0037] A first sub-active region, located between adjacent first grooves;

[0038] The second sub-active region is located between adjacent second grooves, the top surface of the second sub-active region is in contact with the bottom surface of the first sub-active region, and the width of the first sub-active region is greater than that of the second sub-active region.

[0039] Optionally, also include:

[0040] The word line is located in the first sub-active region.

[0041] Optionally, a bottom surface of the word line is flush with a bottom surface of the first sub-active region; or

[0042] A bottom surface of the word line is higher than a bottom surface of the first sub-active region.

[0043] The semiconductor structure and the method for forming the same provided by the present invention form a groove which is narrow at the top and wide at the bottom between adjacent active areas, and form a filling layer with an air gap in the groove, and utilize the characteristic of air having a relatively low dielectric constant to isolate the adjacent active areas, thereby reducing the interference between the adjacent active areas during the operation of the semiconductor structure, alleviating the influence of the hammering effect, and improving the yield and performance reliability of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Attached Figure 1 is a flow chart of a method for forming a semiconductor structure in a specific embodiment of the present invention;

[0045] Attached Figure 2A-2P It is a schematic diagram of the main process structure in the process of forming a semiconductor structure in a specific embodiment of the present invention;

[0046] Attached Figure 3 It is a cross-sectional schematic diagram of a semiconductor structure provided by a specific embodiment of the present invention. DETAILED DESCRIPTION

[0047] The specific implementation manner of the semiconductor structure and the method for forming the same provided by the present invention will be described in detail below with reference to the accompanying drawings.

[0048] This specific embodiment provides a method for forming a semiconductor structure. Figure 1 is a flow chart of a method for forming a semiconductor structure in a specific embodiment of the present invention, Figure 2A-2P FIG. 1 is a schematic diagram of the main process structure in the process of forming a semiconductor structure in a specific embodiment of the present invention. Figure 1 , Figure 2A-2P As shown, the method for forming a semiconductor structure provided in this specific embodiment includes the following steps:

[0049] Step S11, providing a substrate 20, such as Figure 2A and Figure 2B As shown, Figure 2B yes Figure 2A Cross-section along the AB direction.

[0050] Specifically, the substrate 20 may be, but is not limited to, a silicon substrate. This specific embodiment is described by taking the substrate 20 as a silicon substrate as an example. In other examples, the substrate 20 may be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide or SOI.

[0051] Step S12, etching the substrate 20 to form grooves and active areas located between adjacent grooves, wherein the grooves include a first groove 22 and a second groove 26 located below the first groove 22 and connected to the first groove 22, and the inner diameter R1 of the first groove 22 is smaller than the inner diameter R2 of the second groove 26, such as Figure 2M and Figure 2N As shown, Figure 2N yes Figure 2M Schematic diagram of the cross section along the AB direction.

[0052] Optionally, the specific steps of forming the grooves and the active area between adjacent grooves include:

[0053] A mask layer 21 covering the substrate 20 is formed, and the mask layer 21 has an opening 211 exposing the substrate 20. Figure 2A and Figure 2B As shown;

[0054] The substrate 20 is etched along the opening 211 to form first grooves 22 and first sub-active regions 23 located between adjacent first grooves 22. Figure 2C and Figure 2D As shown, Figure 2D yes Figure 2C Schematic diagram of the cross section along the AB direction;

[0055] The substrate 20 is further etched along the first groove 22 to form a second groove 26 communicating with the first groove 22 and a second sub-active region 25 located between adjacent second grooves 26, wherein the inner diameter of the first groove 22 is smaller than the inner diameter of the second groove 26, and the width of the first sub-active region 23 is larger than the width of the second sub-active region 25. Figure 2M and Figure 2N shown.

[0056] Specifically, a material such as polysilicon can be deposited on the surface of the substrate 20 by chemical vapor deposition, physical vapor deposition or atomic layer deposition to form the mask layer 21, and a plurality of openings 211 exposing the substrate 20 are formed in the mask layer 21 by patterning the mask layer 21. Then, the substrate 20 is etched along the opening 211 to a preset depth by a dry etching process to form the first groove 22. A first sub-active region 23 is formed between two adjacent first grooves 22. In the process of etching the substrate 20, one of SF6, CF4, Cl2, CHF3, O2, Ar or a mixture of two or more gases can be used as the etching gas.

[0057] Optionally, the depth H1 of the first groove 22 is 20% to 30% of the depth of the groove.

[0058] The depth of the groove is the sum of the depth H1 of the first groove 22 and the depth H2 of the second groove 26 to be formed subsequently. The depth H1 of the first groove 22 may be the same as the depth of the buried word line to be formed subsequently.

[0059] Optionally, before continuing to etch the substrate 20 along the first groove 22, the following steps are further included:

[0060] A sidewall protection layer 24 is formed to cover the sidewall of the first groove 22. Figure 2E and Figure 2F As shown, Figure 2F yes Figure 2E Schematic diagram of the cross section along the AB direction.

[0061] Optionally, the thickness of the sidewall protection layer 24 is 1 / 5 to 1 / 4 of the width W of the first sub-active region 23 .

[0062] Specifically, after forming the first groove 22 and the first sub-active region 23, an atomic layer deposition process can be used to deposit silicon nitride on the inner wall of the first groove 22 using NH3 or a mixed gas of N2 and H2 as a reaction gas, and the silicon nitride on the bottom surface of the first groove 22 is removed by a vertical downward etching process, and then the sidewall protection layer 24 covering only the sidewall of the first groove 22 is formed. In the process of removing the silicon nitride on the bottom surface of the first groove 22 by the vertical downward etching process, one or a mixture of two or more gases selected from SF6, CF4, Cl2, CHF3, O2, and Ar can be used as etching gas. The thickness of the sidewall protection layer 24 should not be too large, otherwise it will affect the characteristic size of the second groove 26 formed by subsequent etching; the thickness of the sidewall protection layer 24 should not be too small, otherwise it will not be able to effectively protect the sidewall of the first groove 22 in the subsequent process and affect the formation of the subsequent air gap. Based on this, in this specific embodiment, the thickness of the sidewall protection layer 24 is 1 / 5 to 1 / 4 of the width W of the first sub-active region 23.

[0063] Optionally, the specific steps of forming a second groove 26 below the first groove 22 and communicating with the first groove 22 include:

[0064] The substrate 20 is continuously etched along the first groove 22 to form an initial second groove 30 below the first groove 22 and connected to the first groove 22. Figure 2G and Figure 2H As shown, Figure 2H yes Figure 2G Schematic diagram of the cross section along the AB direction;

[0065] The sidewall of the initial second groove 30 is oxidized to form a sidewall oxide layer 27, and the thickness of the sidewall oxide layer 27 is greater than the thickness of the sidewall protection layer 24. Fig.2I and Figure 2J As shown;

[0066] The sidewall oxide layer 27 is removed to form the second groove 26. Figure 2K and Figure 2L As shown, Figure 2L yes Figure 2K Schematic diagram of the cross section along the AB direction.

[0067] Optionally, the specific steps of removing the sidewall oxide layer 27 include:

[0068] The sidewall oxide layer 27 and the sidewall protection layer 24 are removed at the same time.

[0069] Specifically, after forming the sidewall protection layer 24, the substrate 20 is further etched downward along the first groove 22 to form the initial second groove 30 communicating with the first groove 22 below the first groove 22. Figure 2G and Figure 2H As shown. An initial second sub-active area 31 is formed between two adjacent initial second grooves 30. Afterwards, oxygen plasma is used to oxidize the sidewalls of the second groove 30 to form the sidewall oxide layer 27. In the process of oxidizing the sidewalls of the second groove 30 using oxygen plasma, the RF power is 600W to 2000W, and the temperature is 800℃ to 1000℃. In the process of oxygen oxidation, since the sidewalls of the first groove 22 are covered with the sidewall protection layer 24, the sidewalls of the first groove 22 can be prevented from being oxidized. The thickness of the sidewall oxide layer 27 generated by oxidation can be achieved by adjusting the flow rate and / or time of the oxygen plasma introduced into the initial second groove 30. Afterwards, a mixed solution of HF, H3PO4 and water is used as an etching solution, and a wet etching process is used to simultaneously remove the sidewall oxide layer 27 and the sidewall protection layer 24 to form the second groove 26. A second sub-active area 25 is formed between two adjacent second grooves 26, as shown Figure 2K and Figure 2L After removing the mask layer 21, the following is obtained: Figure 2M and Figure 2N Since the thickness of the sidewall oxide layer 27 is greater than the thickness of the sidewall protection layer 24, after removing the sidewall oxide layer 27 and the sidewall protection layer 24, the width of the formed second sub-active region 25 is smaller than the width of the first sub-active region 23, the inner diameter R2 of the second groove 26 is greater than the inner diameter R1 of the first groove 22, and there is a step at the junction of the first sub-active region 23 and the second sub-active region 25 (i.e., the junction of the first groove 22 and the second groove 26), as shown in FIG. Figure 2N shown.

[0070] Step S13, filling the groove to form a filling layer 28 with an air gap 281 in the groove. Fig.2Oand Figure 2P As shown, Figure 2P yes Fig.2O Schematic diagram of the cross section along the AB direction.

[0071] Optionally, the specific steps of forming the filling layer 28 having the air gap 281 in the groove include:

[0072] The groove is filled with an atomic layer deposition process to form a filling layer 28 with an air gap 281 .

[0073] Specifically, the atomic layer deposition process has the characteristic of conformal deposition. When the atomic layer deposition process is used to fill the groove, since the inner diameter R1 of the first groove 22 located above is smaller than the inner diameter R2 of the second groove 26 located below, the top of the first groove 22 will be directly sealed during the deposition process, thereby forming the filling layer 28 with the air gap 281 in the groove. The formation of the air gap 281 can effectively avoid electrical interference between adjacent active areas and weaken the hammering effect. The material of the filling layer 28 can be, but is not limited to, an oxide material, such as silicon dioxide. When the material of the filling layer 28 is silicon dioxide, the reaction gas can be LTO520 (aminosilane gas) / O2 or N zero / O2.

[0074] Optionally, the top surface of the air gap 281 is flush with the bottom surface of the first groove 22; or,

[0075] The top surface of the air gap 281 is higher than the bottom surface of the first groove 22 .

[0076] Specifically, the air gap 281 may be located only in the second groove 26 , or may extend from the first groove 22 to the second groove 26 .

[0077] In addition, this specific embodiment also provides a semiconductor structure, Figure 3 Schematic diagram of a cross-sectional view of a semiconductor structure provided by a specific embodiment of the present invention. The semiconductor structure provided by this specific embodiment can be used as follows Figure 1 , Figure 2A-2P The semiconductor structure is formed by the method of forming the semiconductor structure shown in FIG. Figure 2A-2P and Figure 3 As shown, the semiconductor structure comprises:

[0078] Substrate 20;

[0079] A groove located in the substrate 20, the groove comprising a first groove 22 and a second groove 26 located below the first groove 22 and connected to the first groove 22, and an inner diameter R1 of the first groove 22 is smaller than an inner diameter R2 of the second groove 26;

[0080] A filling layer 28 is located in the groove, and an air gap 281 is formed in the filling layer 28;

[0081] The active area is located between adjacent grooves.

[0082] Optionally, the depth H1 of the first groove 22 is 20% to 30% of the depth of the groove.

[0083] Optionally, the top surface of the air gap 281 is flush with the bottom surface of the first groove 22; or,

[0084] The top surface of the air gap 281 is higher than the bottom surface of the first groove 22 and lower than the top surface of the first groove 22 .

[0085] Optionally, the active area includes:

[0086] A first sub-active region 23 is located between adjacent first grooves 22;

[0087] The second sub-active region 25 is located between adjacent second grooves 26 , the top surface of the second sub-active region 25 is in contact with the bottom surface of the first sub-active region 23 , and the width of the first sub-active region 23 is greater than that of the second sub-active region 25 .

[0088] Specifically, the width of the second sub-active area 25 is smaller than the width of the first sub-active area 23, the inner diameter R2 of the second groove 26 is larger than the inner diameter R1 of the first groove 22, and there is a step at the junction of the first sub-active area 23 and the second sub-active area 25 (that is, the junction of the first groove 22 and the second groove 26), so that in the process of depositing the filling layer 28 using the atomic layer deposition process, the top opening of the first groove 22 can be closed in advance, thereby forming the air gap 281 in the groove.

[0089] Optionally, the semiconductor structure further includes:

[0090] The word line is located in the first sub-active region 23 .

[0091] Optionally, the bottom surface of the word line is flush with the bottom surface of the first sub-active region 23; or

[0092] The bottom surface of the word line is higher than the bottom surface of the first sub-active region 23 .

[0093] The semiconductor structure and the method for forming the same provided in this specific embodiment form a groove that is narrow at the top and wide at the bottom between adjacent active areas, and form a filling layer with an air gap in the groove, thereby isolating the adjacent active areas by utilizing the characteristic of air having a lower dielectric constant, thereby reducing the interference between adjacent active areas during the operation of the semiconductor structure, alleviating the impact of the hammering effect, and improving the yield and performance reliability of the semiconductor structure.

[0094] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A method for forming a semiconductor structure, characterized in that: The steps include: providing a substrate; forming a mask layer covering the substrate, wherein the mask layer has an opening exposing the substrate; Etching the substrate along the opening to form first grooves and first sub-active regions located between adjacent first grooves; forming a sidewall protection layer covering the sidewall of the first groove; Continue etching the substrate along the first groove to form an initial second groove below the first groove and connected to the first groove; Oxidizing the sidewall of the initial second groove to form a sidewall oxide layer, wherein the thickness of the sidewall oxide layer is greater than the thickness of the sidewall protection layer; The sidewall oxide layer is removed to form a second groove and a second sub-active region located between adjacent second grooves, wherein the inner diameter of the first groove is smaller than the inner diameter of the second groove, and the width of the first sub-active region is larger than the width of the second sub-active region; the first groove and the second groove located below the first groove and connected to the first groove together constitute a groove; The groove is filled to form a filling layer with an air gap in the groove.

2. The method for forming a semiconductor structure according to claim 1, wherein: The depth of the first groove is 20% to 30% of the depth of the groove.

3. The method for forming a semiconductor structure according to claim 1, wherein: The thickness of the sidewall protection layer is 1 / 5 to 1 / 4 of the width of the first sub-active region.

4. The method for forming a semiconductor structure according to claim 1, wherein: The specific steps of removing the sidewall oxide layer include: The sidewall oxide layer and the sidewall protection layer are removed simultaneously.

5. The method for forming a semiconductor structure according to claim 1, wherein: The specific steps of forming a filling layer with an air gap in the groove include: The groove is filled with an atomic layer deposition process to form the filling layer having the air gap.

6. The method for forming a semiconductor structure according to claim 1, wherein: The top surface of the air gap is flush with the bottom surface of the first groove; or, A top surface of the air gap is higher than a bottom surface of the first groove.

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