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Storage device, storage controller and storage system

A storage device and storage system technology, applied in the field of storage systems, can solve problems such as difficulty in meeting high-capacity and high-speed data transmission

Pending Publication Date: 2022-03-08
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, when using a signal modulation method based on non-return-to-zero (NRZ) type codi

Method used

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  • Storage device, storage controller and storage system
  • Storage device, storage controller and storage system
  • Storage device, storage controller and storage system

Examples

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Embodiment Construction

[0024] Hereinafter, some examples of embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0025] figure 1 is a block diagram of a storage system 10 according to some embodiments of the inventive concept. The storage system 10 may include a storage device 100 and a storage controller 200 . In embodiments to be described below, the memory device 100 included in the memory system 10 is illustrated as a dynamic random access memory (DRAM), ie, a volatile memory, but the present disclosure and inventive concepts are not limited thereto. For example, other kinds of volatile memories may be applied as the storage device 100 . Alternatively, the memory device 100 according to one or more embodiments of the inventive concept may include a nonvolatile memory such as a resistive memory device, a flash memory device, or the like.

[0026] The memory device 100 may include a transmitter 120 and a memory cell array 140 . The mem...

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Abstract

The provided storage device may apply a pulse amplitude modulation method to data (DQ) signal transmission/reception, and may scale a DQ signal according to an operating frequency condition, thereby improving data transmission performance and effectively improving power consumption. The memory device includes a memory cell array and a data input/output circuit configured to scale a DQ signal including data read from the memory cell array, and output the scaled DQ signal. The data input/output circuit is configured to scale the DQ signal based on n-level pulse amplitude modulation (PAMn) (where n is an integer of 4 or more) with a DQ parameter corresponding to an operating frequency condition and output the DQ signal. Other aspects include a storage controller in communication with the storage device, and a storage system including the storage device and the storage controller.

Description

[0001] Cross References to Related Applications [0002] This application is based upon and claims the benefit of priority from Korean Patent Application No. 10-2020-0114871 filed with the Korean Intellectual Property Office on September 8, 2020, the entire contents of which are hereby incorporated by reference. technical field [0003] The present disclosure relates to memory devices, and more particularly, to memory devices configured to generate pulse amplitude modulation based data (DQ) signals, memory controllers, and memory systems including the memory devices and memory controllers. Background technique [0004] With the rapid distribution of mobile devices and the rapid growth of Internet access, the demand for high-capacity, high-speed data transmission is also increasing. However, when using a non-return-to-zero (NRZ) type coding-based signal modulation method, it may be difficult to meet the demands of high-capacity and high-speed data transmission. [0005] In r...

Claims

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Application Information

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IPC IPC(8): G11C11/4076G11C7/22
CPCG11C7/222G11C11/4076H04L25/4917G11C7/1057G11C7/1006G11C7/1045G06F3/0659H03K7/02G06F13/16G11C7/1051G11C7/1078H03K19/01742
Inventor 李受哲孙永训赵泫润崔荣暾崔桢焕
Owner SAMSUNG ELECTRONICS CO LTD