Packaging structure and electronic equipment

Abstract

The embodiments of the present application provide a substrate, a packaging structure, and an electronic device. The substrate is used to be electrically connected to a chip, the chip includes a power terminal and a signal terminal, the substrate includes a first substrate and a second substrate mounted on the first substrate, the first substrate includes a first wiring, the first wiring is used to be electrically connected to the power terminal, the second substrate includes a second wiring, the second wiring is used to be electrically connected to the signal terminal, and the spacing between the lines of the second wiring is smaller than the spacing between the lines of the first wiring. The substrate provided by the present application is small in size and highly integrated.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a substrate, a packaging structure and an electronic device. Background Art

[0002] Metal substrates are widely used in high-power module packaging, such as Direct Bond Ceramic (DBC), Active Metal Brazing (AMB) and Direct Bond Aluminum (DBA). Metal substrates have good heat dissipation and high current flow capacity. In the package, metal substrates connect internal and external circuits, provide mechanical support, and provide electrical insulation. However, the size of existing metal substrates is relatively large. Summary of the invention

[0003] The embodiments of the present application provide a substrate, a packaging structure including the substrate, and an electronic device including the packaging structure, aiming to achieve good electrical performance while obtaining a small-sized, highly integrated substrate and packaging structure, as well as a smaller-sized electronic device.

[0004] In a first aspect, an embodiment of the present application provides a substrate for electrically connecting to a chip, wherein the chip includes a power terminal and a signal terminal, the substrate includes a first substrate and a second substrate mounted on the first substrate, the first substrate includes a first wiring, the first wiring is used to electrically connect to the power terminal, the second substrate includes a second wiring, the second wiring is used to electrically connect to the signal terminal, and the spacing between the lines of the second wiring is smaller than the spacing between the lines of the first wiring.

[0005] The substrate of the present application includes a first substrate and a second substrate. The first wiring (power line) used to connect to the power terminal of the chip is formed on the first substrate, and the second wiring (signal line) used to connect to the signal terminal of the chip is formed on the second substrate. That is to say, the power line and signal line of the present application are respectively arranged on two different boards. Compared with the solution of integrating the power line and the signal line on one board, the spacing between the lines of the second wiring can be made smaller than the spacing between the lines of the first wiring, which is conducive to the miniaturization of the substrate, thereby improving the integration of the packaging structure, reducing the production cost, and saving the internal space of the electronic device.

[0006] In some embodiments, the first substrate includes a first metal layer, the first wiring is formed on the first metal layer, the second substrate includes a second metal layer, the second wiring is formed on the second metal layer, and the thickness of the second metal layer is less than the thickness of the first metal layer, so as to ensure that the spacing between the lines of the second wiring formed on the second metal layer can be made smaller than the spacing between the lines of the first wiring, so that the lines of the second wiring are more dense, which is conducive to reducing the volume of the second substrate, realizing the miniaturization of the substrate, and improving the integration of the packaging structure. Of course, in other embodiments, the thickness of the second metal layer can be equal to or greater than the thickness of the first metal layer, as long as the spacing between the lines of the second wiring formed on the second metal layer is less than the spacing between the lines of the first wiring formed on the first metal layer.

[0007] In some embodiments, the thickness of the second metal layer is 0.035 mm to 2 mm. By limiting the thickness of the second metal layer to 0.035 mm to 2 mm, the thickness of the second metal layer is ensured to be thin enough, so that when the second wiring is formed on the second metal layer, the spacing between the lines of the second wiring can be small enough, that is, the second metal layer can be etched at a high density, so that the lines of the second wiring can be made denser, which is conducive to reducing the volume of the second substrate, realizing the miniaturization of the substrate, and improving the integration of the packaging structure.

[0008] In some embodiments, the spacing between two adjacent circuits in the circuit of the second wiring is 0.1 mm to 0.5 mm. By limiting the spacing between two adjacent circuits in the circuit of the second wiring to 0.1 mm to 0.5 mm, it is possible to ensure that the spacing between the circuits of the second wiring is small enough, thereby ensuring that the circuits of the second wiring can be dense enough, further reducing the volume of the second substrate, realizing miniaturization of the substrate, and improving the integration of the packaging structure.

[0009] In some embodiments, the first metal layer includes an avoidance groove, and the second substrate is at least partially embedded in the avoidance groove. That is to say, the second substrate in this embodiment is at least partially embedded in the first substrate, which not only reduces the planar size of the substrate, but also reduces the size of the substrate in the thickness direction, further improving the integration of the substrate.

[0010] In some embodiments, the first substrate includes a carrier plate, the first metal layer is disposed on the carrier plate, and the surface of the second wiring facing away from the carrier plate is flush with the surface of the first metal layer facing away from the carrier plate. In other words, the second wiring layer is flush with the surface of the first wiring layer, so that when the chip is disposed on the substrate, the chip can be flip-chip bonded to the substrate, the portion of the chip with the power terminal can be disposed on the first substrate and electrically connected to the first wiring, and the portion of the chip with the signal terminal can be disposed on the second substrate and electrically connected to the second wiring, thereby avoiding the connection between the signal terminal and the second wiring through a wire, simplifying the manufacturing steps of the packaging structure, and improving the production efficiency of the packaging structure.

[0011] In some embodiments, the second substrate further comprises an insulating plate, the second wiring is arranged on the insulating plate, and the side of the insulating plate facing away from the second wiring is connected to the surface of the first wiring. By installing the second substrate on the first substrate, it is beneficial to reduce the plane area of ​​the entire substrate, thereby improving the integration of the substrate and the packaging structure.

[0012] In some embodiments, the second substrate includes an insulating plate, the second wiring is disposed on the insulating plate, the first substrate includes a carrier plate, the first wiring is disposed on the carrier plate, the side of the insulating plate is connected to the side of the carrier plate, and the first wiring is spaced from the second wiring. Compared with the second substrate being welded to the surface of the first metal layer, the area of ​​the welding surface where the side of the insulating plate is connected to the side of the carrier plate is smaller, the corresponding process cost is reduced, and the insulating plate can be welded to any side of the carrier plate, which is more flexible in design.

[0013] In some embodiments, the first substrate further includes a third metal layer, and the third metal layer is disposed on the surface of the carrier plate facing away from the first wiring. The material of the third metal layer is copper. Of course, the third metal layer can also be other metal materials or non-metallic materials such as aluminum and nickel. The third metal layer is used to conduct away the heat transferred from the chip to the first wiring, so that the chip dissipates heat faster, ensuring the electrical performance of the chip. At the same time, the third metal layer can also enhance the strength of the entire substrate.

[0014] In some embodiments, the second substrate further includes a fourth metal layer, which is disposed on a surface of the insulating plate facing away from the second wiring. The fourth metal layer is used to conduct away the heat transferred from the chip to the first wiring, so that the chip dissipates heat faster, ensuring the electrical performance of the chip, and the fourth metal layer can also enhance the strength of the second substrate.

[0015] In some embodiments, there are multiple second substrates, which are installed on the first substrate at intervals and are respectively arranged close to the chip electrically connected thereto. This is equivalent to arranging the second wiring arranged on one board on two boards respectively, so that the second substrate can be made smaller, and the two second substrates can be arranged at different positions according to the chip electrically connected thereto, so that the layout is more flexible and the stress of the packaging structure is easier to control.

[0016] In a second aspect, an embodiment of the present application further provides a packaging structure, the packaging structure comprising a chip and the above-mentioned substrate, the chip comprising a power terminal and a signal terminal, the chip being arranged on the first wiring, the power terminal being electrically connected to the first wiring, and the signal terminal being electrically connected to the second wiring. The packaging structure having the substrate provided by the present application effectively improves the integration, heat dissipation performance and electrical performance.

[0017] In some embodiments, the signal terminal is electrically connected to the second wiring through a wire; or the signal terminal is electrically connected to the second wiring through a pad. When the second substrate is mounted on the first wiring layer of the first substrate, the signal terminal is electrically connected to the second wiring through a wire. When the second substrate is embedded in the first substrate, or the second substrate is connected to the side of the first substrate, the chip can be flip-chip bonded on the first substrate and the second substrate, and the signal terminal is electrically connected to the second wiring through a pad, avoiding the connection between the signal terminal and the second wiring through a wire, simplifying the manufacturing steps of the packaging structure, and improving the production efficiency of the packaging structure.

[0018] In some embodiments, the packaging structure includes a third substrate, the third substrate includes a third wiring, the spacing between the lines of the third wiring is smaller than the spacing between the lines of the first wiring, and the third wiring is connected between the signal terminal and the second wiring. In other words, the third substrate can be understood as a transfer board between the chip and the second wiring, so that the electrical connection relationship between multiple chips and the second wiring is more concise. Of course, in other embodiments, the chip can also be directly electrically connected to the second wiring.

[0019] In some embodiments, the packaging structure includes an electronic component, which is disposed on the third substrate and electrically connected to the third wiring, and is used to assist the third wiring in switching the circuit between the chip and the second wiring.

[0020] In a third aspect, an embodiment of the present application further provides an electronic device, the electronic device comprising a circuit board and the above-mentioned packaging structure, wherein the packaging structure is electrically connected to the circuit board. The electronic device having the packaging structure provided by the present application has effectively improved integration, heat dissipation performance and electrical performance.

[0021] The substrate of the present application includes a first substrate and a second substrate. The first wiring (power line) used to connect to the power terminal of the chip is formed on the first substrate, and the second wiring (signal line) used to connect to the signal terminal of the chip is formed on the second substrate. That is to say, the power line and signal line of the present application are respectively arranged on two different boards. Compared with the solution of integrating the power line and the signal line on one board, the spacing between the lines of the second wiring can be made smaller than the spacing between the lines of the first wiring, which is conducive to the miniaturization of the substrate, thereby improving the integration of the packaging structure, reducing the production cost, and saving the internal space of the electronic device. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a structural schematic diagram of an electronic device provided in an embodiment of the present application;

[0023] Figure 2 yes Figure 1 A partial structural schematic diagram of a packaging structure of a power device package shown;

[0024] Figure 3 yes Figure 2 A schematic structural diagram of a first embodiment of a substrate of a packaging structure shown;

[0025] Figure 4 It is a structural schematic diagram of a substrate in the related art;

[0026] Figure 5 yes Figure 3 A schematic diagram of the cross-sectional structure of the substrate shown in the AA direction;

[0027] Figure 6 yes Figure 2 A schematic diagram of the structure of the substrate and the lead frame combined as shown;

[0028] Figure 7 yes Figure 3 A structural diagram of a second embodiment of a substrate shown;

[0029] Figure 8 yes Figure 3 A structural diagram of a third embodiment of a substrate shown;

[0030] Fig. 9 yes Figure 8 A schematic cross-sectional structure diagram of a substrate shown;

[0031] Fig.10 yes Figure 8 The schematic diagram of the structure of the substrate and the chip combined as shown;

[0032] Fig.11 yes Fig.10 A schematic cross-sectional structure diagram of a substrate shown;

[0033] Fig.12 yes Figure 3 A structural diagram of a fourth embodiment of a substrate shown;

[0034] Fig.13 yes Fig.12 Schematic diagram of the cross-sectional structure of the substrate shown. DETAILED DESCRIPTION

[0035] The embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0036] See also Figure 1 , Figure 1 It is a structural diagram of an electronic device 100 provided in an embodiment of the present application.

[0037] The electronic device 100 includes a packaging structure 1, a circuit board 2 and a housing 3. The packaging structure 1 is mounted on the circuit board 2 and electrically connected to the circuit board 2 to control the operation of the packaging structure 1 through the circuit board 2. The packaging structure 1 and the circuit board 2 are both contained inside the housing 3. The packaging structure 1 is a power module of the electronic device 100, which is used to realize the conversion of the electrical signal of the electronic device 100. The electronic device 100 in this embodiment includes but is not limited to wind turbines, photovoltaic generators, electric vehicles, white appliances and other electronic devices 100 with the packaging structure 1. The integration, heat dissipation performance and electrical performance of the electronic device 100 with the packaging structure 1 provided in this application are effectively improved.

[0038] See also Figure 2 , Figure 2 yes Figure 1 The packaging structure of the electronic device 100 shown in the figure, the device of this packaging structure can be a power switching device, such as rectification, inversion, power factor correction, etc., a partial structural schematic diagram of the packaging structure 1.

[0039] The package structure 1 includes a substrate 10 and a chip 20. The chip 20 is arranged on the substrate 10. The chip 20 includes a power terminal and a signal terminal. The power terminal is the collector (source), emitter (drain) and other electrodes of the chip 20 that bear high-power and high-voltage signals, and the signal terminal is the control gate (gate) switch of the chip 20 and other electrodes that bear low-power and low-voltage signals. The power terminal of the chip 20 is electrically connected to a part of the substrate 10, and the signal terminal of the chip 20 is electrically connected to another part of the substrate 10 to be electrically connected to other devices through the substrate 10. In this embodiment, the package structure 1 includes but is not limited to various types of power converters such as DC-DC converters and DC-AC converters. The integration, heat dissipation performance and electrical performance of the package structure 1 with the substrate 10 provided in the present application are effectively improved.

[0040] The packaging structure 1 may further include a packaging body (not shown) and a heat sink (not shown). The packaging body is packaged on a side of the substrate 10 where the chip 20 is provided, so as to package the chip 20 and other devices on the substrate 10. The heat sink is connected to a side of the substrate 10 facing away from the chip 20, so as to dissipate heat from electronic devices such as the chip 20 packaged in the packaging body, thereby ensuring the electrical performance of the chip 20 and other devices.

[0041] In some embodiments, some structures with control functions are also integrated inside the package, such as a control device equipped with a control circuit, which is electrically connected to the chip 20 and can control the operation of the chip 20. For safety and reliability, the temperature state of the package structure 1 will be monitored in real time. For example, a temperature sensor can be integrated in the package structure 1. If the temperature is too high or rises too fast, it means that the circuit is dangerous, and preventive actions can be taken in advance, such as turning off the power supply.

[0042] See also Figure 2 and Figure 3 , Figure 3 yes Figure 2 The structure diagram of the first embodiment of the substrate 10 of the packaging structure 1 is shown.

[0043] The substrate 10 includes a first substrate 11 and a second substrate 12, the second substrate 12 is mounted on the first substrate 11, the first substrate 11 includes a first wiring 111, the second substrate 12 includes a second wiring 121, and the spacing between the lines of the second wiring 121 is smaller than the spacing between the lines of the first wiring 111, that is, the lines of the second wiring 121 are arranged more densely than the lines of the first wiring 111. The chip 20 is provided on the first wiring 111, the power terminal is electrically connected to the first wiring 111, and the signal terminal is electrically connected to the second wiring 121.

[0044] It is understandable that the circuits on the substrate are usually formed by etching, such as Figure 4 , the circuits formed on the substrate 10a in the related art include both power circuits 111a for connecting to the power terminals of the chip and signal circuits 121a for connecting to the signal terminals of the chip. Since the circuit width of the power circuit 111a needs to meet the requirements of high voltage and high current, the metal layer forming the circuit on the substrate 10a needs to be made relatively thick, but the thicker metal layer is greatly affected by the etching process, and it is necessary to consider the difference in width between the top and bottom of the circuit formed by etching the thick metal layer during the etching process. Specifically, the etching process forms grooves separating the circuits by corroding the metal layer. During the corrosion process, the acid corrodes from the surface of the metal layer. Since the sidewalls of the circuit are also affected by the corrosive liquid, the top of the circuit is corroded wider and the bottom is corroded narrower. The difference between the top and bottom of the formed circuit is in a certain proportion to the thickness of the metal layer (corrosion factor). The thicker the metal layer, the greater the absolute width difference between the top and bottom of the circuit.

[0045] In order to ensure the minimum spacing at the bottom of the circuit and the effective width at the top of the circuit, the size of the metal layer has to be relatively enlarged when the metal layer is corroded to ensure the effective area and width at the top of the circuit, that is, the size of the substrate 10a has to be relatively enlarged to ensure the effective area and width at the top of the circuit. However, the signal circuit 121a does not have the requirements of high voltage and high current. Since the signal circuit 121a is also made on a thicker metal layer, the spacing L1 between the circuits of the signal circuit 121a cannot be reduced, resulting in the circuit density of the signal circuit 121a being limited, which is not conducive to the miniaturization of the volume of the substrate 10a, nor is it conducive to the improvement of the heat dissipation efficiency of the substrate 10a.

[0046] The substrate 10 of the present application includes a first substrate 11 and a second substrate 12. The first wiring 111 (power line) for connecting to the power terminal of the chip 20 is formed on the first substrate 11, and the second wiring 121 (signal line) for connecting to the signal terminal of the chip 20 is formed on the second substrate 12. That is to say, the power line and signal line of the present application are respectively arranged on two different boards. Compared with the solution of integrating the power line and the signal line on one board, the spacing L2 between the lines of the second wiring 121 can be made smaller than the spacing between the lines of the first wiring 111, which is conducive to the miniaturization of the substrate 10, thereby improving the integration of the packaging structure 1, reducing the production cost, and saving the internal space of the electronic device 100.

[0047] At the same time, the first substrate 11 is used to electrically connect with the power terminal of the chip 20, and also dissipates heat for the chip 20 and supports the chip 20 and other devices. The second substrate 12 is used to electrically connect with the signal terminal of the chip 20 to realize the electrical connection between the chip 20 and the external lead frame or pin. By forming the first wiring 111 and the second wiring 121 on the first substrate 11 and the second substrate 12 respectively, the first substrate 11 and the second substrate 12 are also functionally differentiated, which is conducive to the optimization of the functional layout of the substrate 10. And the second wiring 121 is not formed on the first substrate 11, which is conducive to optimizing the distribution of the first wiring 111 on the first substrate 11. Compared with forming the first wiring 111 and the second wiring 121 on the first substrate 11 at the same time, forming the first wiring 111 only on the first substrate 11 reduces the number of grooves on the first substrate 11 to a certain extent, and relatively, increases the metal area of ​​the first substrate 11, and optimizes the static and dynamic heat dissipation performance of the package structure 1.

[0048] like Figure 2In this embodiment, the number of chips 20 is eight, and the eight chips 20 are arranged in parallel and spaced apart in pairs on the first wiring 111. The chip 20 can be, for example, a power chip such as an insulated gate bipolar transistor (IGBT), a silicon metal oxide semiconductor field effect transistor (MOSFET) and / or a diode, or other non-power chips. The silicon metal oxide semiconductor field effect transistor can be a silicon metal oxide semiconductor field effect transistor made of silicon, or a silicon metal oxide semiconductor field effect transistor made of silicon carbide or gallium nitride. The chip 20 can be fixed on the first wiring 111 by welding, bonding, or other connection methods. In other embodiments, the arrangement of the chip 20 is not limited to the above description. The chip 20 can also be one or more than eight.

[0049] See also Figure 3 and Figure 5 , Figure 5 yes Figure 3 The cross-sectional structure diagram of the substrate 10 in the AA direction is shown.

[0050] In this embodiment, the first substrate 11 includes a first metal layer 112, a carrier plate 113 and a third metal layer 114. The first metal layer 112 is disposed on the insulating heat-conducting carrier plate 113, and the third metal layer 114 is disposed on the surface of the carrier plate 113 facing away from the first metal layer 112. It can be understood that the first metal layer 112 and the third metal layer 114 are respectively disposed on two opposite surfaces of the carrier plate 113. The substrate 10 can be formed by electroplating, crimping or welding the first metal layer 112 and the third metal layer 114 on two opposite surfaces of the carrier plate 113. The first wiring 111 is formed on the first metal layer 112, that is, the third metal layer 114 is disposed on the surface of the carrier plate 113 facing away from the first wiring 111, and the chip 20 ( Figure 2 ) is disposed on the first metal layer 112. The first metal layer 112 is etched to form the first wiring 111. Of course, in other embodiments, the first substrate may also only include the first metal layer and the carrier plate.

[0051] The material of the first metal layer 112 is copper. Of course, the first metal layer 112 can also be other metal materials such as aluminum and nickel. On the one hand, the first metal layer 112 forms the first wiring 111 to be electrically connected to the chip 20. On the other hand, it can also dissipate heat for the chip 20, so that the heat of the chip 20 is transferred through the first wiring 111, thereby ensuring the electrical performance of the chip 20. The material of the third metal layer 114 is copper. Of course, the third metal layer 114 can also be other metal materials or non-metallic materials such as aluminum and nickel. The third metal layer 114 is used to conduct the heat transferred from the chip 20 to the first wiring 111, so that the chip 20 dissipates heat faster, thereby ensuring the electrical performance of the chip 20. At the same time, the third metal layer 114 can also enhance the strength of the entire substrate 10. The material of the carrier plate 113 is ceramic, and the ceramic can be, for example, alumina, silicon nitride, aluminum nitride, or reinforced aluminum nitride and other ceramic materials. The carrier board 113 is used to achieve electrical isolation and electromagnetic shielding between the first metal layer 112 and the third metal layer 114, and to reflect external electromagnetic interference, thereby preventing external electromagnetic radiation from interfering with the normal operation of the chip 20 and reducing the interference effect of electromagnetic radiation in the surrounding environment on the electronic components in the packaging structure 1.

[0052] The second substrate 12 includes a second metal layer 122, an insulating plate 123 and a fourth metal layer 124. The second metal layer 122 is disposed on the insulating plate 123, and the fourth metal layer 124 is disposed on the surface of the insulating plate 123 facing away from the second metal layer 122. It can be understood that the second metal layer 122 and the fourth metal layer 124 are respectively disposed on two opposite surfaces of the insulating plate 123. The substrate 10 can be formed by electroplating, crimping or welding the second metal layer 122 and the fourth metal layer 124 on two opposite surfaces of the insulating plate 123. The second wiring 121 is formed on the second metal layer 122, that is, the fourth metal layer 124 is disposed on the surface of the insulating plate 123 facing away from the second wiring 121. The second metal layer 122 forms the second wiring 121 through an etching process. In this embodiment, the circuit of the second wiring 121 is a pad. Of course, in other embodiments, the circuit of the second wiring 121 can also be other structures such as a routing. Alternatively, the second substrate 12 can also include only an insulating plate and a second metal layer.

[0053] In this embodiment, the thickness of the second metal layer 122 is less than the thickness of the first metal layer 112, so as to ensure that the spacing between the lines of the second wiring 121 formed on the second metal layer 122 can be made smaller than the spacing between the lines of the first wiring 111, so that the lines of the second wiring 121 are more dense, which is conducive to reducing the volume of the second substrate 12, realizing the miniaturization of the substrate 10, and improving the integration of the package structure 1. Of course, in other embodiments, the thickness of the second metal layer 122 can be equal to or greater than the thickness of the first metal layer 112, as long as the spacing between the lines of the second wiring 121 formed on the second metal layer 122 is smaller than the spacing between the lines of the first wiring 111 formed on the first metal layer 112.

[0054] Specifically, the thickness of the second metal layer 122 is 0.035 mm to 2 mm. By limiting the thickness of the second metal layer 122 to 0.035 mm to 2 mm, the thickness of the second metal layer 122 is ensured to be thin enough, so that when the second wiring 121 is formed on the second metal layer 122, the spacing between the lines of the second wiring 121 can be small enough, that is, the second metal layer 122 can be etched at a high density, so that the lines of the second wiring 121 can be made denser, which is conducive to reducing the volume of the second substrate 12, realizing the miniaturization of the substrate 10, and improving the integration of the package structure 1. Of course, the thickness of the second metal layer 122 can also be other values ​​besides 0.035 mm to 2 mm.

[0055] The spacing between two adjacent lines in the lines of the second wiring 121 is 0.1 mm to 0.5 mm. By limiting the spacing between two adjacent lines in the lines of the second wiring 121 to 0.1 mm to 0.5 mm, it is possible to ensure that the spacing between the lines of the second wiring 121 is small enough, thereby ensuring that the lines of the second wiring 121 are dense enough, further reducing the volume of the second substrate 12, miniaturizing the substrate 10, and improving the integration of the packaging structure 1. Of course, in other embodiments, the spacing between two adjacent lines in the lines of the second wiring 121 can also be other values, as long as the lines of the second wiring 121 are dense enough, and the volume of the second substrate 12 can be further reduced.

[0056] The second substrate 12 may be a direct plating ceramic substrate (Direct Plating ceramic, DPC), that is, the material of the insulating plate 123 is ceramic, and the material of the ceramic may be alumina, zirconium oxide toughened alumina ceramic, aluminum nitride or silicon nitride and other ceramic materials, and the insulating plate 123 is copper-plated on two opposite surfaces to form a second metal layer 122 and a fourth metal layer 124, respectively, and the thickness of the second metal layer 122 and the fourth metal layer 124 is 35 to 200 um, and the thickness of the second metal layer 122 and the fourth metal layer 124 may be the same or different. Of course, the second metal layer 122 and the fourth metal layer 124 may also be formed by electroless nickel immersion gold (Electroless Nickel Immersion Gold, ENIG), electroless nickel palladium gold, surface bare copper, nickel plating, gold plating and other processes.

[0057] The second substrate 12 can also be a direct copper bonding (DCB), that is, the material of the insulating plate 123 is ceramic, and the material of the ceramic can be alumina, zirconium oxide toughened alumina ceramic, aluminum nitride and other ceramic materials. The insulating plate 123 has two opposite surfaces formed by copper pressing to form the second metal layer 122 and the fourth metal layer 124, respectively. The thickness of the second metal layer 122 and the fourth metal layer 124 is 50-400um, and the thickness of the second metal layer 122 and the fourth metal layer 124 can be the same or different. Of course, the second metal layer 122 and the fourth metal layer 124 can also be formed by electroless nickel immersion gold (ENIG), electroless nickel palladium gold, surface bare copper, nickel plating, gold plating, copper plating and other processes.

[0058] The second substrate 12 can also be a thick film plating ceramic (TPC), that is, the material of the insulating plate 123 is ceramic, and the material of the ceramic can be alumina, zirconium oxide toughened alumina ceramic, aluminum nitride and other ceramic materials. The insulating plate 123 is formed into a second metal layer 122 and a fourth metal layer 124 respectively on two opposite surfaces by double-sided co-firing of metal silver paste or metal copper paste with glass. The thickness of the second metal layer 122 and the fourth metal layer 124 is 35 to 200 um, and the thickness of the second metal layer 122 and the fourth metal layer 124 can be the same or different. Of course, the second metal layer 122 and the fourth metal layer 124 can also be formed by electroless nickel immersion gold (ENIG), electroless nickel palladium gold, surface bare copper, gold plating and other processes.

[0059] The second substrate 12 may also be a printed circuit board (PCB), that is, the material of the insulating plate 123 is a flame-resistant resin, and the insulating plate 123 is copper-plated on two opposite surfaces to form a second metal layer 122 and a fourth metal layer 124, respectively. The thickness of the second metal layer 122 and the fourth metal layer 124 is 35 to 200 um, and the thickness of the second metal layer 122 and the fourth metal layer 124 may be the same or different. Of course, the second metal layer 122 and the fourth metal layer 124 may also be formed by electroless nickel immersion gold (ENIG), electroless nickel palladium gold, surface bare copper, nickel plating, gold plating, and the like.

[0060] The second metal layer 122 forms an electrical connection between the second wiring 121 and the chip 20 to realize the electrical connection between the chip 20 and the external device. The fourth metal layer 124 is used to conduct away the heat transferred from the chip 20 to the first wiring 111, so that the chip 20 dissipates heat faster, ensuring the electrical performance of the chip 20. At the same time, the fourth metal layer 124 can also realize metallization welding with the first metal layer 112. The insulating plate 123 is used to realize the electrical isolation between the second metal layer 122 and the fourth metal layer 124. At the same time, the insulating plate 123 also ensures the attachment and support of the double-sided metal of the second substrate.

[0061] In this embodiment, the second substrate 12 is mounted on the first wiring 111 of the first substrate 11, and the side of the insulating plate 123 facing away from the second wiring 121 is connected to the surface of the first wiring 111. Specifically, the fourth metal layer 124 on the side of the insulating plate 123 facing away from the second wiring 121 is arranged on the surface of the first wiring 111, that is, the fourth metal layer 124 is arranged on the surface of the first metal layer 112. The fourth metal layer 124 is fixed to the first metal layer 112 by soldering, laser or ultrasonic welding, and is spaced apart from the chip 20. By mounting the second substrate 12 on the first substrate 11, it is beneficial to reduce the plane area of ​​the entire substrate 10, and improve the integration of the substrate 10 and the packaging structure 1. Of course, in other embodiments, the fourth metal layer can also be fixed to the first metal layer 112 by other connection methods such as bonding and clamping. Alternatively, the insulating plate 123 can also be directly fixed to the first metal layer 112.

[0062] See also Figure 2 and Figure 6 , Figure 6 yes Figure 2 The schematic diagram of the structure between the substrate 10 and the lead frame is shown.

[0063] The signal terminal of the chip 20 is electrically connected to the second wiring 121 through a wire, and the wire is fixed to the second wiring 121 by ultrasonic bonding or welding. The second substrate 12 is installed on the edge of the first metal layer 112, so that the signal terminal is electrically connected to the external device through the second wiring 121 of the second substrate 12. One end of the lead frame a is electrically connected to the second wiring 121, and the other end is electrically connected to the external device to achieve the electrical connection between the chip 20 and the external device. The lead frame a can be welded to the second wiring 121 by melting solder, laser or ultrasound. Some of the pins of the lead frame a can also be equipped with a thermistor to serve as an over-temperature protection for the package structure 1. The width of the second substrate 12 can be greater than, less than or equal to the width of the first substrate 11. Of course, in other embodiments, a wire bonding process can also be used, such as a copper sheet replacing a wire to connect the signal terminal and the second wiring 121 to achieve current transfer, which greatly reduces the internal resistance of the package structure 1, and the cost will not be too high.

[0064] like Figure 2 The package structure 1 further includes a third substrate 13, the third substrate 13 includes a third wiring 131, and the third wiring 131 is connected between the signal terminal and the second wiring 121. In other words, the third substrate 13 can be understood as a transfer board between the chip 20 and the second wiring 121, so that the electrical connection relationship between the plurality of chips 20 and the second wiring 121 is more concise. Of course, in other embodiments, the chip 20 can also be directly electrically connected to the second wiring 121.

[0065] In this embodiment, the number of the third substrates 13 is two, and the two third substrates 13 are arranged on the first wiring 111 at intervals and are respectively located between two adjacent columns of chips 20. The signal terminal of each chip 20 is electrically connected to the third wiring 131 of the third substrate 13 close to it, and the third wiring 131 is electrically connected to the second wiring 121 to realize the switching between the chip 20 and the second wiring 121. Specifically, the signal terminal of the chip 20 is electrically connected to the third wiring 131 close to it through a wire, and one end of the third wiring 131 close to the second substrate 12 is electrically connected to the second wiring 121 through a wire. The switching between the chip 20 close to it and the second wiring 121 is realized through the third substrate 13. Compared with each chip 20 being connected to the second wiring 121 through a wire, each chip 20 is gathered through the third substrate 13 and then electrically connected to the second wiring 121. It is simpler and neater, and the length of the wire is also shortened. Of course, in other embodiments, the number of the third substrates 13 can also be one or more, and the arrangement of the third substrates 13 can also be set according to actual needs.

[0066] The spacing between the lines of the third wiring 131 is smaller than the spacing between the lines of the first wiring 111, that is, the spacing between the lines of the third wiring 131 can be made smaller than the spacing between the lines of the first wiring 111, which is conducive to the miniaturization of the third substrate 13, thereby improving the integration of the packaging structure 1. Of course, in other embodiments, the spacing between the lines of the third wiring 131 can also be equal to or greater than the spacing between the lines of the first wiring 111.

[0067] The package structure 1 includes electronic components, which are disposed on the third substrate 13 and electrically connected to the third wiring 131. Specifically, the electronic components are passive components such as resistors and capacitors, and are used to assist the third wiring 131 in switching the circuit between the chip 20 and the second wiring 121.

[0068] See also Figure 7 , Figure 7 yes Figure 3 FIG. 1 is a structural diagram of a second embodiment of a substrate 10 shown in FIG.

[0069] This embodiment is substantially the same as the first embodiment, except that in this embodiment, there are two second substrates 12, and the two second substrates 12 are installed on the first substrate 11 at intervals. One second substrate 12 is connected to a corresponding third substrate. The two second substrates 12 are respectively arranged close to the chip 20 electrically connected thereto. By providing two second substrates 12, the present application is equivalent to providing the second wiring 121 provided on one board on two boards respectively, so that the second substrate 12 can be made smaller, and the two second substrates 12 can be provided at different positions respectively according to the chip 20 electrically connected thereto, so that the layout is more flexible, and the stress of the packaging structure 1 is easier to control. Of course, in other embodiments, there can also be multiple second substrates 12, and multiple second substrates 12 are installed on the first substrate 11 at intervals.

[0070] See also Figure 8 and Fig. 9 , Figure 8 yes Figure 3 The structural diagram of the third embodiment of the substrate 10 shown in FIG. Fig. 9 yes Figure 8 Schematic diagram of the cross-sectional structure of the substrate 10 is shown.

[0071] This embodiment is substantially the same as the first embodiment, except that the first metal layer 112 in this embodiment includes an avoidance groove 1121, and the second substrate 12 is completely embedded in the avoidance groove 1121. Specifically, the fourth metal layer 124 of the second substrate 12 is welded and fixed to the bottom wall of the avoidance groove 1121, and the second wiring 121 of the second substrate 12 is insulated from the first metal layer 112. In other words, the second substrate 12 in this embodiment is embedded in the first substrate 11, and on the basis of reducing the plane size of the substrate 10, the size of the substrate 10 in the thickness direction is not increased, which further improves the integration of the substrate 10. Of course, in other embodiments, the second substrate 12 can also be at least partially embedded in the avoidance groove 1121, and the fourth metal layer 124 of the second substrate 12 and the avoidance groove 1121 can also be connected and fixed by bonding, clamping, etc. Alternatively, the third substrate can also be embedded in the first metal layer.

[0072] In this embodiment, there are two second substrates 12, and correspondingly, there are two avoidance grooves 1121, and each substrate 12 is respectively embedded in the avoidance groove 1121 corresponding thereto. The line of the second wiring 121 is a routing line, and the surface of the second wiring 121 facing the notch of the avoidance groove 1121 is flush with the notch. In other words, the second wiring 121 layer is flush with the surface of the first wiring 111 layer facing away from the carrier board 113, so that the chip 20 can be flip-chip bonded to the substrate 10, such as Figure 10-11 The chip 20 with power terminals can be disposed on the first substrate 11 and electrically connected to the first wiring 111, and the chip 20 with signal terminals can be disposed on the second substrate 12 and electrically connected to the second wiring 121. Specifically, the power terminals and the first wiring 111, and the signal terminals and the second wiring 121 are welded by pads, thereby avoiding the connection between the signal terminals and the second wiring 121 by wires, simplifying the package structure 1 ( Figure 2 ) manufacturing steps, thereby improving the production efficiency of the package structure 1. Of course, in other embodiments, the circuit of the second wiring 121 can also be other structures such as a pad. Alternatively, the number of the second substrate 12 and the avoidance groove 1121 is one or more, and each second substrate is embedded in the avoidance groove corresponding to it at intervals. Alternatively, all the chips are arranged on the first wiring, and the chip and the second substrate are electrically connected by wires.

[0073] See also Fig.12 and Fig.13 , Fig.12 yes Figure 3 The structure diagram of the fourth embodiment of the substrate 10 shown in FIG. Fig.13 yes Fig.12 Schematic diagram of the cross-sectional structure of the substrate 10 is shown.

[0074] This embodiment is substantially the same as the first embodiment, except that the side of the insulating plate 123 in this embodiment is connected to the side of the carrier plate 113, and the first wiring 111 and the second wiring 121 are spaced apart. Specifically, the insulating plate 123 and the carrier plate 113 are welded together by high-energy laser or other methods. Compared with the second substrate 12 welded to the surface of the first metal layer 112 in the first embodiment, the area of ​​the welding surface where the side of the insulating plate 123 and the side of the carrier plate 113 are connected is smaller, the corresponding process cost is reduced, and the insulating plate 123 can be welded to any side of the carrier plate 113, which is more flexible in design. Of course, in other embodiments, the second substrate 12 can also be installed on the first substrate 11 by other connection methods.

[0075] In the scenario of this embodiment, the line of the second wiring 121 is a routing line, the first wiring 111 of the first substrate 11 and the second wiring 121 of the second substrate 12 have the same orientation, and the chip 20 can be directly flip-chip bonded to the substrate 10. The portion of the chip 20 with a power terminal can be arranged on the first substrate 11 and electrically connected to the first wiring 111, and the portion of the chip 20 with a signal terminal is arranged on the second substrate 12 and electrically connected to the second wiring 121. Specifically, the power terminal and the first wiring 111, and the signal terminal and the second wiring 121 are all welded, thereby avoiding the connection between the signal terminal and the second wiring 121 through a wire, simplifying the package structure 1 ( Figure 2 ) manufacturing steps, thereby improving the production efficiency of the package structure 1. Of course, in other embodiments, the circuit of the second wiring 121 can also be other structures such as a pad. Alternatively, the number of second substrates is multiple, and multiple second substrates are connected to any side of the first substrate at intervals, or multiple second substrates are respectively arranged on different sides of the first substrate. Alternatively, all chips are arranged on the first wiring, and the chip and the second substrate are electrically connected through wires.

[0076] The protection scope of the present application is not limited to the above-mentioned embodiments 1 to 4. Any combination of embodiments 1 to 4 is also within the protection scope of the present application. That is to say, the multiple embodiments described above can also be arbitrarily combined according to actual needs.

[0077] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A packaging structure, comprising a substrate and a chip electrically connected to the substrate, wherein the chip comprises a power terminal and a signal terminal, characterized in that: The substrate includes a first substrate and a second substrate mounted on the first substrate, the first substrate includes a first metal layer and a first wiring, the first wiring is formed on the first metal layer, the first wiring is used to be electrically connected to the power terminal, the second substrate includes a second wiring, the second wiring is used to be electrically connected to the signal terminal, the spacing between the lines of the second wiring is smaller than the spacing between the lines of the first wiring, the chip is arranged on the first wiring, the first substrate is used to support the chip, the first metal layer is used to provide heat dissipation for the chip, the power terminal is electrically connected to the first wiring, and the signal terminal is electrically connected to the second wiring.

2. The packaging structure according to claim 1, characterized in that: The second substrate includes a second metal layer, the second wiring is formed on the second metal layer, and the thickness of the second metal layer is smaller than that of the first metal layer.

3. The packaging structure according to claim 2, characterized in that: The thickness of the second metal layer is 0.035 mm to 2 mm.

4. The packaging structure according to any one of claims 1 to 3, characterized in that: The spacing between two adjacent lines in the second wiring is 0.1 mm to 0.5 mm.

5. The packaging structure according to claim 2, characterized in that: The first metal layer includes an avoidance groove, and the second substrate is at least partially embedded in the avoidance groove.

6. The packaging structure according to claim 5, characterized in that: The first substrate comprises a carrier plate, the first metal layer is disposed on the carrier plate, and a surface of the second wiring facing away from the carrier plate is flush with a surface of the first metal layer facing away from the carrier plate.

7. The packaging structure according to any one of claims 1 to 3, characterized in that: The second substrate further includes an insulating plate, the second wiring is disposed on the insulating plate, and a side of the insulating plate facing away from the second wiring is connected to a surface of the first wiring.

8. The packaging structure according to any one of claims 1 to 3, characterized in that: The second substrate includes an insulating plate, the second wiring is arranged on the insulating plate, the first substrate includes a supporting plate, the first wiring is arranged on the supporting plate, the side of the insulating plate is connected to the side of the supporting plate, and the first wiring is spaced from the second wiring.

9. The packaging structure according to claim 8, characterized in that: The first substrate further includes a third metal layer, and the third metal layer is disposed on a surface of the carrier plate facing away from the first wiring.

10. The packaging structure according to claim 7, characterized in that: The second substrate further includes a fourth metal layer, and the fourth metal layer is disposed on a surface of the insulating plate facing away from the second wiring.

11. The packaging structure according to claim 1, characterized in that: There are a plurality of second substrates, and the plurality of second substrates are installed on the first substrate at intervals and are respectively arranged close to the chips electrically connected thereto.

12. The packaging structure according to claim 1, characterized in that: The signal terminal is electrically connected to the second wiring through a wire; or the signal terminal is electrically connected to the second wiring through a pad.

13. The packaging structure according to claim 12, characterized in that: The packaging structure includes a third substrate, the third substrate includes a third wiring, a spacing between lines of the third wiring is smaller than a spacing between lines of the first wiring, and the third wiring is connected between the signal terminal and the second wiring.

14. The packaging structure according to claim 13, characterized in that: The packaging structure includes an electronic component, which is disposed on the third substrate and electrically connected to the third wiring.

15. An electronic device, characterized in that: The electronic device comprises a circuit board and the packaging structure according to any one of claims 1 to 14, and the packaging structure is electrically connected to the circuit board.

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