Clock calibration circuit, device and method

Abstract

The present invention provides a clock calibration circuit, device and method. The clock calibration circuit only needs to perform frequency division processing on a clock signal using a detection period as a frequency division coefficient, so that the effective pulse of the obtained frequency division signal is generated at the detection termination time, and then detects the effective edge of a reference clock signal near the detection termination time, that is, near the time when the effective pulse of the frequency division signal is generated, to obtain a detection result, and then realizes that the effective edge of the frequency division signal to be output is aligned with the effective edge of the reference clock signal according to the detection result. Compared with using a standard reference signal to calibrate the clock signal for each clock cycle, this scheme only needs to perform edge calibration on the frequency division signal, thereby improving the accuracy of the frequency division signal by eliminating the accumulated error. This method has low input requirements for an external standard timing system and is suitable for long-term calibration or unattended scenarios.

Description

Technical Field

[0001] The present application relates to the technical field of clock circuits, and in particular to providing a clock calibration circuit, device and method. Background Art

[0002] In order to ensure the normal operation of electronic equipment, it is often necessary to set up a clock circuit inside to provide a clock signal.

[0003] The clock circuit is usually equipped with a crystal oscillator or an oscillator. Due to its working characteristics, the actual frequency of the output clock signal has some deviation from the nominal frequency, so it needs to be calibrated. The existing calibration method is to calibrate each clock cycle of the clock signal based on an external standard reference signal, and then obtain the target clock signal after frequency division. However, this method has high requirements on the accuracy of the reference signal, so the input requirements of the external standard timing system that provides the reference signal are also high. Summary of the invention

[0004] The present application provides a clock calibration circuit, characterized in that it is applied to a clock circuit, the clock circuit is used to provide a clock signal, and the clock calibration circuit includes:

[0005] A frequency division module, connected to the clock circuit, for performing frequency division processing on the clock signal with a detection period as a frequency division coefficient to obtain a frequency division signal;

[0006] A detection module is used to be connected to the clock circuit and the frequency division module, and is used to:

[0007] In a time range where there is only one valid edge of the reference clock signal and the first preset time length from the detection end time of the detection cycle, the valid edge of the reference clock signal is detected by the clock signal to obtain a detection result; according to the detection result, the pulse calibration quantity, the detection start time and the frequency division start time of the next detection cycle are determined, and the frequency division signal of the next detection cycle is corrected;

[0008] A calibration module is used to be connected to the clock circuit and to be connected to the detection module, and is used to perform pulse calibration on the clock signal within the calibration period to be output according to the detection period, the clock signal, the calibration period and the pulse calibration quantity.

[0009] In one embodiment, the detection module is further used for:

[0010] Generate a window detection signal according to the detection period and the first preset time length, wherein a valid pulse of the window detection signal corresponds to a valid edge of the reference clock signal, and both ends of the valid pulse of the window detection signal are respectively different from the detection termination time by the first preset time length;

[0011] Based on the window detection signal, the effective edge of the reference clock signal is detected with the clock signal to obtain the detection result.

[0012] In one embodiment, the detection result includes the detection of the effective edge of the reference clock signal by the detection termination time, and the duration information between the detection time of the effective edge and the detection termination time; the duration information is characterized as a first number of clock cycles; the pulse calibration number includes the number of added pulses; the detection module is further configured to: if the effective edge is detected before the detection termination time, then:

[0013] Using the first number as the number of added pulses;

[0014] Taking the detection time as the detection start time and the frequency division start time;

[0015] Adjusting the effective pulse of the frequency-divided signal so that the effective pulse of the frequency-divided signal is generated at the detection time;

[0016] The added pulse quantity is used to indicate the quantity of increased pulses.

[0017] In one embodiment, the first preset duration is a second number of clock cycles of the clock signal, and the detection module is further configured to:

[0018] At the time when the effective pulse of the window detection signal is generated, the clock cycle of the clock signal is counted down with the second number as the initial value until the effective edge is detected before the detection termination time, and the second number at the end of the counting is used as the first number.

[0019] In one embodiment, the pulse calibration number also includes a subtraction pulse number, and the detection module is further configured to: if the valid edge is not detected by the detection termination time,

[0020] The first number is used as the number of pulses to be reduced; wherein the number of pulses to be reduced is used to indicate the number of pulses to be reduced;

[0021] Taking the detection time as the detection start time and the frequency division start time;

[0022] The divided frequency signal is maintained.

[0023] In one embodiment, the detection module is further used for:

[0024] If the valid edge is not detected by the time the detection ends, the clock signal clock cycle is incremented with 0 as the initial value to obtain a count value until the valid edge is detected, and the count value at the end of the counting is used as the first quantity.

[0025] In one embodiment, the calibration module comprises:

[0026] A generation control unit connected to the detection module, configured to correct the number of added pulses according to the detection period and the calibration period, and generate a pulse addition enable signal according to the calibration period and the corrected number of added pulses;

[0027] A pulse compensation unit is connected to the generation control unit and the clock circuit respectively, and is used to increase the pulse of the clock signal within the calibration period to be output according to the clock signal and the pulse adding enable signal.

[0028] In one embodiment, the generation control unit is further configured to:

[0029] If the detection period is equal to the calibration period, the number of added pulses is maintained unchanged;

[0030] If the detection period is greater than the calibration period, [N(T1 / T2)] is used as the corrected number of added pulses;

[0031] If the detection period is less than the calibration period, N(T1 / T2) is used as the corrected number of added pulses;

[0032] Wherein, [] represents rounding down, N is the number of pulses before correction, T1 is the calibration period, and T2 is the detection period.

[0033] In one embodiment, the calibration period is characterized by 2 n The corrected number of pulses is represented by:

[0034]

[0035] Wherein, A is the corrected number of pulses, A i The value of is 0 or 1, i, m and n are natural numbers, and m is less than n;

[0036] The generation control unit is also used for:

[0037] If A iThe value of is 1, then in each round of segmentation, a segmentation point is set to divide the interval formed by the previous segmentation point on the calibration period into two, and the moment of the segmentation point is used as the first trigger moment, until 2 is obtained. i the first triggering moment, the previous segmentation point is a segmentation point set before the current round of segmentation;

[0038] Based on the first triggering moment, a pulse having a width of one clock cycle of the clock signal is generated to obtain the pulse adding enable signal.

[0039] In one embodiment, the generation control unit is further configured to:

[0040] After the first trigger moment is delayed by a second preset time length, a pulse with a width of one clock cycle of the clock signal is generated to obtain the pulse enable signal; wherein the second preset time length is an integer multiple of the clock cycle.

[0041] In one of the embodiments, when the pulse calibration number also includes a subtraction pulse number;

[0042] The generation control unit is further used to correct the number of subtraction pulses according to the detection period and the calibration period, and generate a subtraction pulse enable signal according to the calibration period and the corrected number of subtraction pulses;

[0043] The pulse compensation unit is further configured to reduce the pulse of the clock signal within the calibration period to be output according to the clock signal and the pulse reduction enable signal.

[0044] In one embodiment, the generation control unit is further configured to:

[0045] If the detection period is equal to the calibration period, the number of the subtraction pulses is maintained unchanged;

[0046] If the detection period is greater than the calibration period, [M(T1 / T2)] is used as the corrected number of subtraction pulses;

[0047] If the detection period is less than the calibration period, M(T1 / T2) is used as the corrected number of subtraction pulses;

[0048] Wherein, [] represents rounding down, M is the number of the subtraction pulses before correction, T1 is the calibration period, and T2 is the detection period.

[0049] In one embodiment, the calibration period is characterized by 2 n The clock cycle of the clock signal, the corrected number of the subtraction pulses is characterized by:

[0050]

[0051] Wherein, D is the number of pulses after correction, D j The value of is 0 or 1, j, p and n are natural numbers, and p is less than n;

[0052] The generation control unit is also used for:

[0053] If D j The value of is 1, then in each round of segmentation, a segmentation point is set to divide the interval formed by the previous segmentation point on the calibration period into two, and the moment of the segmentation point is used as the second triggering moment, until 2 is obtained. j the second triggering moment, the previous segmentation point is a segmentation point set before the current round of segmentation;

[0054] At each of the second trigger moments, a pulse with a width equal to one clock cycle of the clock signal is generated to obtain the pulse reduction enable signal.

[0055] In one embodiment, the pulse compensation unit includes: a first NOT gate, a second NOT gate, a third NOT gate, a first trigger, a second trigger, a third trigger, an AND gate, a NAND gate, an OR gate, a buffer circuit and a two-way selector;

[0056] Wherein, the input end of the first NOT gate is connected to the generation control unit, and the input end of the second NOT gate is used to be connected to the clock circuit;

[0057] The input terminal of the first trigger is connected to the output terminal of the first NOT gate, the clock terminal of the first trigger is connected to the output terminal of the second NOT gate, and the output terminal of the first trigger is connected to the first input terminal of the AND gate;

[0058] The second input terminal of the AND gate is connected to the clock circuit, and the output terminal of the AND gate is connected to the first input terminal of the two-way selector;

[0059] The input end of the second trigger is connected to the generation control unit, and the output end of the second trigger is respectively connected to the input end of the third trigger and the first input end of the NAND gate;

[0060] The input end of the third NOT gate and the clock end of the third flip-flop are respectively connected to the clock circuit, and the output end of the third NOT gate is respectively connected to the first input end of the OR gate and the clock end of the second flip-flop;

[0061] The output end of the third trigger is connected to the second input end of the NAND gate, and the output end of the NAND gate is connected to the second input end of the OR gate and the input end of the buffer circuit respectively;

[0062] The output end of the buffer circuit is connected to the control end of the two-way selector, and the output end of the OR gate is connected to the second input end of the two-way selector.

[0063] A clock calibration device, comprising:

[0064] Clock circuit;

[0065] And any clock calibration circuit described above.

[0066] A clock calibration method is applied to a clock circuit, wherein the clock circuit is used to provide a clock signal, and the clock calibration method comprises:

[0067] Performing frequency division processing on the clock signal using the detection period as a frequency division coefficient to output a frequency division signal;

[0068] In a time range where there is only one valid edge of the reference clock signal and the first preset time length is from the detection end moment of the detection period, the valid edge of the reference clock signal is detected by the clock signal to obtain a detection result;

[0069] Determine the pulse calibration quantity, detection start time and frequency division start time of the next detection cycle according to the detection result, and correct the frequency division signal of the next detection cycle;

[0070] Pulse calibration is performed on the clock signal within the calibration period to be output according to the detection period, the clock signal, the calibration period and the pulse calibration number.

[0071] The above-mentioned clock calibration circuit only needs to divide the clock signal with the detection period as the division coefficient, so that the effective pulse of the obtained divided signal is generated at the detection termination time, and then detect the effective edge of the reference clock signal near the detection termination time, that is, near the time when the effective pulse of the divided signal is generated, to obtain the detection result, and then determine the pulse calibration number, detection start time and division start time of the next detection period according to the detection result, and correct the divided signal of the next detection period. Finally, the calibration module is combined to perform pulse calibration on the clock signal in the calibration period to be output according to the detection period, clock signal, calibration period and pulse calibration number, so as to achieve the effective edge of the divided signal to be output to be aligned with the effective edge of the reference clock signal. Compared with using a standard reference signal to calibrate the clock signal for each clock cycle, this scheme only needs to perform edge calibration on the divided signal, so as to improve the accuracy of the divided signal by eliminating the accumulated error. This method has low input requirements for the external standard timing system and is suitable for long-term calibration or unattended scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0072] Figure 1A structural block diagram of a clock calibration circuit according to an embodiment of the present application;

[0073] Figure 2 A timing diagram of various signals of a clock calibration circuit according to an embodiment of the present application;

[0074] Figure 3 A timing diagram of various signals of a clock calibration circuit according to another embodiment of the present application;

[0075] Figure 4 This is a schematic diagram of sampling results of the clock calibration circuit of this application;

[0076] Figure 5 A timing diagram of various signals of a clock calibration circuit according to another embodiment of the present application;

[0077] Figure 6 A structural block diagram of a clock calibration circuit according to another embodiment of the present application;

[0078] Figure 7 This is a circuit structure diagram of a pulse compensation unit according to an embodiment of the present application;

[0079] Figure 8 A timing diagram of various signals of a clock calibration circuit according to another embodiment of the present application;

[0080] Fig. 9 FIG. 4 is a flow chart of a clock calibration method according to an embodiment of the present application. DETAILED DESCRIPTION

[0081] It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0082] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0083] It should be noted that all directional indications in the embodiments of the present application (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly. The connection can be a direct connection or an indirect connection.

[0084] In addition, in this application, descriptions such as "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in this field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by this application.

[0085] Figure 1 FIG. 1 is a schematic diagram of the structure of a clock calibration circuit according to an embodiment of the present invention. The clock calibration circuit is applied to a clock circuit, and the clock circuit is used to provide a clock signal. Figure 1 As shown, the clock calibration circuit includes a frequency division module 101, a detection module 102 and a calibration module 103. The frequency division module 101 is used to connect with the clock circuit 100, and is used to divide the clock signal with the detection period as the frequency division coefficient to obtain the frequency division signal; the detection module 102 is used to connect with the clock circuit 100 and the frequency division module 101, and is used to detect the effective edge of the reference clock signal with the clock signal within the time range of the first preset time length from the detection end time of the detection period when there is only one effective edge of the reference clock signal, and obtain the detection result; determine the pulse calibration number, detection start time and frequency division start time of the next detection period according to the detection result, and correct the frequency division signal of the next detection period; the calibration module 103 is used to connect with the clock circuit 100 and the detection module 102, and is used to perform pulse calibration on the clock signal in the calibration period to be output according to the detection period, the clock signal, the calibration period and the pulse calibration number.

[0086] The frequency division module 101 performs frequency division processing on the clock signal with the detection period as the frequency division coefficient, so that the effective pulse of the frequency division signal obtained after the frequency division processing is generated at the detection end time of the detection period. Among them, the detection period can be preset manually, which can be an integer multiple of the clock period of the clock signal, usually so that the calendar clock can be obtained after the frequency division processing, and the detection period can be determined according to the calendar clock.

[0087] The reference clock signal may be an external reference clock provided to the detection module 102. When the detection module 102 detects the effective edge of the reference clock signal, there is only one effective edge of the reference clock within the detection time range, and it is separated from the detection end time of the detection cycle by a first preset time length. The time range is separated from the detection end time of the detection cycle by a first preset time length, and the two boundary times forming the time range may be separated from the detection end time of the detection cycle by a first preset time length, that is, the detection end time of the detection cycle may be located at the midpoint of the time range. Figure 2 As shown, t f As the detection cycle detection termination time, there is only one valid edge of the reference clock signal in the time range formed by time t1 and time t2, which is located at time t x , time t1 and time t2 are respectively related to the detection cycle detection end time t f The first preset time length L1 can be set according to the frequency deviation between the clock signal and the reference clock signal, and it does not exceed one detection cycle.

[0088] The effective edge of the reference clock signal is detected by using the clock signal, and the effective edge of the reference clock signal can be detected by using the effective pulse of the clock signal. When the reference clock signal is detected to change from the first level to the second level, it indicates that the effective edge of the reference clock signal is detected. Figure 2 , assuming that the effective pulse of the clock signal is at a high level, and the effective edge of the reference clock signal is the rising transition edge from a low level to a high level, then the time when the effective pulse of the clock signal detects the rising transition edge of the reference clock signal is t a It can be understood that since the detection of the effective edge of the clock signal to the reference clock signal is performed within a specific time interval, the time interval needs to include only one effective edge of the reference clock signal, so the calibration is suitable for the calibration of small error clock signals.

[0089] The detection result can be used to characterize the relationship between the detection time when the effective edge is detected and the detection termination time. The detection module 102 can determine the pulse calibration number, the detection start time and the frequency division start time of the next detection cycle based on the detection result, and correct the frequency division signal of the next detection cycle. The pulse calibration number can be used to indicate the number of pulses of the calibration clock signal. After the calibration module 103 performs pulse calibration on the clock signal in the calibration cycle to be output based on the detection cycle, the clock signal, the calibration cycle and the pulse calibration number, it will affect the frequency division signal obtained by the frequency division counting. The detection start time is the starting time of the detection cycle. When the detection cycle is constant, the detection start time determines the detection termination time of the detection cycle, that is, it affects the detection result, and then it will also affect the frequency division signal obtained by frequency division based on the detection cycle. The frequency division start time is the starting time of the frequency division counting in a frequency division cycle, which determines the time when the effective pulse of the frequency division signal is generated. Therefore, the pulse calibration number, the detection start time, the frequency division start time and the correction frequency division signal will affect the output of the frequency division signal, and finally make the effective edge of the frequency division signal to be output aligned with the effective edge of the reference clock signal.

[0090] The clock calibration circuit of the embodiment of the present invention only needs to perform frequency division processing on the clock signal with the detection period as the frequency division coefficient, so that the effective pulse of the obtained frequency division signal is generated at the detection termination time, and then detect the effective edge of the reference clock signal near the detection termination time, that is, near the time when the effective pulse of the frequency division signal is generated, to obtain the detection result, and then determine the pulse calibration number, detection start time and frequency division start time of the next detection period according to the detection result, and correct the frequency division signal of the next detection period, and finally combine the calibration module 103 to perform pulse calibration on the clock signal in the calibration period to be output according to the detection period, clock signal, calibration period and pulse calibration number, so as to achieve the effective edge of the frequency division signal to be output to be aligned with the effective edge of the reference clock signal. Compared with using a standard reference signal to calibrate the clock signal for each clock period, this scheme only needs to perform edge calibration on the frequency division signal, so as to improve the accuracy of the frequency division signal by eliminating the accumulated error. This method has low input requirements for the external standard timing system and is suitable for long-term calibration or unattended scenarios.

[0091] In one embodiment, the detection module 102 is also used to generate a window detection signal based on a detection period and a first preset duration, wherein a valid pulse of the window detection signal corresponds to a valid edge of a reference clock signal, and both ends of the valid pulse of the window detection signal are respectively different from the detection termination moment by a first preset duration; based on the window detection signal, the valid edge of the reference clock signal is detected with the clock signal to obtain a detection result.

[0092] It can be understood that in order to ensure that when edge detection is performed, it is performed within the time range of the first preset time length from the detection end moment of the detection period, a window detection signal can be generated according to the detection period, the reference clock signal and the clock signal, and then based on the window detection signal, within the time interval where the valid pulse of the window detection signal is located, the valid edge of the reference clock signal is detected with the clock signal. The waveform of the window detection signal can be referred to Figure 2 As shown, the effective pulse is located in the time interval from t1 to t2, and the two ends of the effective pulse are respectively different from the detection termination time by a first preset time length L1.

[0093] The detection end time of the detection period can be predicted based on the detection period, and then the first preset time length is moved forward and backward based on the detection end time, so as to obtain the window detection signal. To ensure that the effective pulse of the window detection signal corresponds to only one effective edge of the reference clock signal, the frequency f of the reference clock signal is ref Should satisfy 1<2L1f ref<2, that is, the effective pulse width of the window detection signal should be greater than one cycle of the reference clock signal and less than two cycles of the reference clock signal. In addition, in order to ensure the accuracy of the clock signal to detect the effective edge of the reference clock signal, the frequency of the reference clock signal f ref The frequency of the clock signal f calr Should satisfy 2f ref <f calr To ensure the validity of the reference clock signal, the frequency deviation of the reference clock signal should be less than f calr / 2 k , of which 2 k Indicates that the detection cycle is clock cycle 2 k times.

[0094] This embodiment generates a window detection signal according to the detection period and the first preset time length, thereby limiting the time interval for the clock signal to detect the valid edge of the reference clock signal. The principle is simple and effective.

[0095] In one embodiment, the detection result includes the situation in which the effective edge of the reference clock signal is detected up to the detection termination time, and the duration information between the detection time when the effective edge is detected and the detection termination time; the duration information is represented as a first number of clock cycles of the clock signal, and the pulse calibration number includes the number of added pulses. The detection module 102 is also used for: if the effective edge is detected before the detection termination time, then: use the first number as the number of added pulses; use the detection time as the detection start time and the frequency division start time; adjust the effective pulse of the frequency division signal so that the effective pulse of the frequency division signal is generated at the detection time; wherein the number of added pulses is used to indicate the number of increased pulses.

[0096] It can be understood that, ideally, the clock signal should be aligned with the effective edge of the reference clock signal at the detection termination time. If the clock signal frequency is too low, it will result in the detection termination time t not being reached. f The valid edge of the reference clock is detected. Figure 3 As shown, due to the detection termination time t f It has been determined in advance that after the detection time is obtained, the duration information can be determined according to the detection time and the detection termination time, wherein the duration information can be represented by a first number of clock cycles. When a valid edge is detected before the detection termination time, the detection module 102 uses the first number as the number of added pulses to instruct the calibration module 103 to subsequently increase the number of pulses, and at the same time re-determines the detection time as the detection start time of the next detection cycle and the frequency division start time of the next frequency division cycle, and further adjusts the effective pulse of the frequency division signal so that the effective pulse of the frequency division signal is generated at the detection time.

[0097] Specifically, refer to Figure 3As shown in the figure, when the clock signal detects the edge of the reference clock signal, it is assumed that at t a The effective edge of the reference clock signal is detected at the time. Theoretically, the detection time is t a However, considering that the reference clock signal and the clock signal come from different clocks, the cross-clock domain signal usually needs clock synchronization when performing edge detection, that is, three samplings are required. Figure 4 As shown, the first sampling is to sample the effective edge of the reference clock signal, that is, at t a The effective edge of the reference clock is sampled at the moment, and the second sampling is to sample the result of the first sampling with the clock signal, that is, at t b The first sampling is valid at time t, and the third sampling is to sample the result of the second sampling with the clock signal, that is, at time t c The second sampling result is valid, and the final edge detection result is equal to the XOR operation of the third sampling result and the second sampling result. Therefore, the detection time is actually time t b , the final edge detection result is at time t b To time t c Effective, for example, the edge detection result can be represented by the detection pulse in the figure.

[0098] Before re-determining the detection start time and the frequency division start time, the original detection start time of the next detection cycle is the detection end time t of the current detection cycle. f , the detection start time is re-determined as time t b ; The original frequency division start time of the next frequency division cycle is the detection end time t f ,refer to Figure 3 The frequency division signal in the re-determined frequency division starting time should also be time t b In fact, due to the synchronous clock, the re-determined detection start time and frequency division start time are actually the next clock rising edge when the detection result is valid, that is, time t c The output of the frequency division signal can be obtained by using a counter to count the clock signal clock cycle. Suppose the frequency division coefficient is 2 k , the start time of the next frequency division cycle is re-determined as time t c After that, at time t c 2 k -1 counts down, such as Figure 3 As shown in the figure, when the count reaches 0, one frequency division cycle count is completed. Similarly, the effective pulse of the adjusted frequency division signal is actually generated at time t c , its waveform can be referred to Figure 3 The final output is shown.

[0099] The first number indicates the number of clock cycles that the reference clock signal and the clock signal differ from each other within a frequency division cycle when the reference clock signal and the clock signal are output at the same initial time. When a valid edge is detected before the detection termination time, the valid pulse of the frequency division signal is adjusted, and the detection time is used again as the detection start time and the frequency division start time, and the first number of clock cycles that differ between the detection time and the detection termination time of the valid edge is used as the number of added pulses to perform pulse calibration on the clock signal of the next calibration cycle, thereby achieving pulse calibration on the clock signal of the next detection cycle, so that the valid edge of the frequency division signal to be output can be gradually aligned with the valid edge of the reference clock signal, and finally the frequency division signal is aligned with the reference clock signal.

[0100] In one embodiment, the first preset duration is a second number of clock cycles of a clock signal, and the detection module 102 is also used to: at the time when a valid pulse of the window detection signal is generated, count down the clock cycles of the clock signal using the second number as the initial value until a valid edge is detected before the detection termination time, and use the second number at the end of the counting as the first number.

[0101] refer to Figure 3 The detection count shown is to obtain the detection time t b and the detection end time t f The first preset duration L1 can be characterized as a second number of clock cycles of the clock signal. For example, 15 clock cycles are taken as an example in the figure. Then, by using the clock cycle detection counting method, the clock cycle of the clock signal is counted down with 15 as the initial value at the effective pulse generation time t1 of the window detection signal until the detection time t b When a valid edge is detected, the counting ends, and the second number is now 7, which is used as the first number, and the number of added pulses is also 7. In this way, the first number is obtained by detecting the count through the clock cycle without performing intermediate calculations, which is simple and efficient.

[0102] In one embodiment, the pulse calibration number also includes the number of reduced pulses, and the detection module 102 is also used to: if no valid edge is detected by the end of the detection termination time, then: use the first number as the number of reduced pulses; wherein the number of reduced pulses is used to indicate the number of reduced pulses; use the detection time as the detection start time and the frequency division start time; and maintain the frequency division signal.

[0103] It can be understood that, ideally, the clock signal should be aligned with the valid edge of the reference clock signal at the detection termination time. If the clock signal frequency is too high, it will result in the detection termination time t being reached. f The valid edge of the reference clock has not yet been detected. Figure 5As shown, due to the detection termination time t f It has been determined in advance that after the detection time is obtained, the duration information can be determined according to the detection time and the detection termination time, wherein the duration information can be represented by a first number of clock cycles. f If the effective edge of the reference clock is still not detected, the normal output of the frequency division signal is maintained. Figure 5 As shown in the final output, the detection module 102 uses the first number as the subtraction pulse number to instruct the calibration module 103 to subsequently reduce the number of pulses, and further re-determines the detection moment as the detection start moment of the next detection cycle and the frequency division start moment of the next frequency division cycle.

[0104] Specifically, refer to Figure 5 As shown in the figure, when the clock signal detects the edge of the reference clock signal, it is assumed that at t a The effective edge of the reference clock signal is detected at the time. Theoretically, the detection time is t a However, considering that the reference clock signal and the clock signal come from different clocks, the cross-clock domain signal usually needs clock synchronization when performing edge detection, that is, three samplings are required. Figure 4 As shown, the first sampling is to sample the effective edge of the reference clock signal, that is, at t a The effective edge of the reference clock is sampled at the moment, and the second sampling is to sample the result of the first sampling with the clock signal, that is, at t b The first sampling is valid at time t, and the third sampling is to sample the result of the second sampling with the clock signal, that is, at time t c The second sampling result is valid, and the final edge detection result is equal to the XOR operation of the third sampling result and the second sampling result. Therefore, the detection time is actually time t b , the final edge detection result is at time t b To time t c Effective, for example, the edge detection result can be represented by the detection pulse in the figure.

[0105] Before re-determining the detection start time and the frequency division start time, the original detection start time of the next detection cycle is the detection end time t of the current detection cycle. f , the detection start time is re-determined as time t b ; The original frequency division start time of the next frequency division cycle is the detection end time t f ,refer to Figure 5 The frequency division signal in the re-determined frequency division starting time should also be time t bIn fact, due to the synchronous clock, the re-determined detection start time and frequency division start time are actually the next clock rising edge when the detection result is valid, that is, time t c The output of the frequency division signal can be obtained by using a counter to count the clock signal clock cycle. Suppose the frequency division coefficient is 2 k , the start time of the next frequency division cycle is re-determined as time t c After that, at time t c 2 k -1 counts down, such as Figure 5 As shown, when the count reaches 0, one frequency division cycle count is completed.

[0106] In the case that no valid edge is detected by the end of the detection, the frequency division signal is output normally, and the detection time is used again as the detection start time and the frequency division start time, and the first number of clock cycles between the detection time of the valid edge and the detection end time is used as the number of subtraction pulses, so as to perform pulse calibration on the clock signal of the next calibration cycle, and then realize pulse calibration on the clock signal of the next detection cycle, so that the valid edge of the frequency division signal to be output can be gradually aligned with the valid edge of the reference clock signal, and finally the frequency division signal is aligned with the reference clock signal. Among them, due to the synchronous clock, the actual re-determined detection start time and frequency division start time have a deviation of 2-3 clock cycles from the theoretically re-determined detection start time and frequency division start time, so the frequency division signal finally output will also have a deviation of 2-3 clock cycles.

[0107] In one embodiment, the detection module 102 is also used to: if no valid edge is detected by the end of the detection, then use 0 as the initial value to increment the clock cycle of the clock signal to obtain a count value until a valid edge is detected, and use the count value at the end of the counting as the first quantity.

[0108] refer to Figure 5 The detection count shown is to obtain the detection time t b and the detection end time t f The first preset duration L1 can be characterized as a second number of clock cycles of the clock signal, for example, 15 clock cycles are taken as an example in the figure, and then the clock cycle detection counting method is used to detect the end time t f The clock signal is counted up with 0 as the initial value to obtain the count value until the time t b When a valid edge is detected, the counting ends, and the count value is 8 at this time. 8 is taken as the first number, and the number of subtraction pulses is also 8. In this way, the first number is obtained by detecting the count through the clock cycle without performing intermediate calculations, which is simple and efficient.

[0109] In one embodiment, the calibration module 103 includes a generation control unit 1032 and a pulse compensation unit 1031. Figure 6 The generation control unit 1032 is connected to the detection module 102, and is used to correct the number of pulses according to the detection cycle and the calibration cycle, and generate a pulse enable signal according to the calibration cycle and the corrected number of pulses; the pulse compensation unit 1031 is connected to the generation control unit 1032 and the clock circuit 100, respectively, and is used to increase the pulses of the clock signal within the calibration cycle to be output according to the clock signal and the pulse enable signal.

[0110] It can be understood that the calibration cycle can be preset manually, indicating the minimum time unit for calibration. The number of added pulses indicates the number of pulses that need to be added during the detection cycle, and the pulse compensation unit 1031 increases the number of pulses during the calibration cycle. The detection cycle and the calibration cycle are not necessarily equal, so the number of added pulses needs to be corrected according to the detection cycle and the calibration cycle.

[0111] The generation control unit 1032 may be provided with a signal generator, and after obtaining the corrected number of pulses, an enable signal is generated. The pulse enable signal generated according to the calibration cycle information and the number of pulses may carry the time information and the number information of the added pulses, which may be used to indicate that a preset number of pulses are added at a preset time within the calibration cycle of the clock signal.

[0112] In one embodiment, the generation control unit 1032 is also used for: if the detection period is equal to the calibration period, the number of added pulses is maintained unchanged; if the detection period is greater than the calibration period, [N(T1 / T2)] is used as the corrected number of added pulses; if the detection period is less than the calibration period, N(T1 / T2) is used as the corrected number of added pulses; wherein, [] indicates rounding down, N is the number of added pulses before correction, T1 is the calibration period, and T2 is the detection period.

[0113] Among them, both the detection period and the calibration period can be represented as an exponential power of 2. For example, if the detection period is represented as 2 k , the calibration cycle is characterized as 2 n When correcting the number of pulses according to the detection period and calibration period, if the detection period is equal to the calibration period, the number of pulses is not corrected and its value remains N; if the detection period is greater than the calibration period, the proportion of the calibration period in the detection period can be calculated first to obtain 2 n-k , then calculate the product of the number of pulses added and the proportion, and round down the product to get the corrected number of pulses added [N2 n-k ]; If the detection cycle is less than the calibration cycle, after calculating the proportion, the product of the number of pulses added and the proportion can be calculated to obtain the corrected number of pulses added N2 n-k .

[0114] In one embodiment, the calibration period is characterized by 2 n The clock cycle of the clock signal, the corrected number of pulses is represented by:

[0115]

[0116] Among them, A is the number of pulses added after correction, A i The value of is 0 or 1, i, m and n are natural numbers, and m is less than n.

[0117] The generation control unit 1032 is further used to: if A i If the value of is 1, then in each round of segmentation, a segmentation point is set to divide the interval formed by the previous segmentation point on the calibration period into two, and the moment of the segmentation point is used as the first trigger moment, until 2 is obtained. i A first trigger moment, the front division point is a division point set before the current round division; based on the first trigger moment, a pulse with a width of one clock cycle of the clock signal is generated to obtain a pulse enable signal.

[0118] It can be understood that when the calibration period is preset, the calibration period should satisfy the value of the clock period of the clock signal whose value is equal to the exponential power of 2. The number of pulses is an integer, which can be represented as the sum of multiple different exponential powers of 2. When generating the pulse enable signal, at least one round of segmentation can be performed for any exponential power of 2, wherein in each round of segmentation, a segmentation point is set to divide the interval formed by the previous segmentation point dividing the calibration period into two, and the moment of the segmentation point is used as the first trigger moment, until the first trigger moments equal to the exponential power of 2 are obtained, and then pulses with a width of one clock period of the clock signal are generated based on each first trigger moment. For example, if the calibration period is 2 5 =32, A is equal to 12, that is, A is represented as equal to 2 2 and 2 3 The sum of, on the one hand, for 2 2=4, that is, 4 segmentation points are to be obtained as the first triggering moment; at least one round of segmentation is performed, wherein in the first round of segmentation, since there is only one interval of the calibration period at this time, the number of segmentation points set in this round of segmentation is 1, which is located at the 16th clock cycle. Since the number of segmentation points in this round does not reach 4, the segmentation is continued; in the second round of segmentation, since there are two intervals of the 0th to 16th clock cycle and the 16th to 32nd clock cycle after the first round of segmentation, the number of segmentation points set in this round of segmentation is 2, which are located at the 8th clock cycle and the 16th to 32nd clock cycle, respectively. The first and second rounds of segmentation have four intervals, namely the 0th to 8th clock cycle, the 8th to 16th clock cycle, the 16th to 24th clock cycle, and the 24th to 32nd clock cycle. Therefore, the number of segmentation points set for this round of segmentation is 4, which are located at the 4th, 12th, 20th, and 28th clock cycles respectively. At this time, the 4 first triggering moments are the 4th, 12th, 20th, and 28th clock cycles respectively. 2 The segmentation is completed; on the other hand, for 2 3 =8, that is, to obtain 8 segmentation points as the first triggering moment, the above segmentation steps are also performed. It can be seen from the above that the third round of segmentation only obtains 4 first triggering moments, which does not reach 8, so the fourth round of segmentation is continued on this basis. When performing the fourth round of segmentation, since there are eight intervals of the 0th to 4th clock cycle, the 4th to 8th clock cycle, the 8th to 12th clock cycle, the 12th to 16th clock cycle, the 16th to 20th clock cycle, the 20th to 24th clock cycle, the 24th to 28th clock cycle, and the 28th to 32nd clock cycle after the first, second, and third rounds of segmentation, the number of segmentation points set in this round of segmentation is 8, which are located at the 2nd, 6th, 10th, 14th, 18th, 22nd, 26th, and 30th clock cycles respectively. At this time, the 8 first triggering moments are the 2nd, 6th, 10th, 14th, 18th, 22nd, 26th, and 30th clock cycles respectively. So far, for 2 3 The segmentation is finished.

[0119] After obtaining the above-mentioned first triggering moment, a pulse is generated based on each first triggering moment, thereby obtaining a pulse reduction enable signal. The first triggering moment can be used to stimulate the pulse to be generated immediately at the current moment, that is, the pulse is generated at the first triggering moment; in addition, the first triggering moment can also be used to stimulate the pulse to be generated at a specific moment, that is, the pulse is not generated at the first triggering moment.

[0120] In one embodiment, the clock cycle can be counted by a counter to determine the first triggering moment. The counter can use a binary counting method to start counting from 0. For example, assuming n=20, m=8, that is, the calibration cycle is 2 20 , The corresponding relationship between the valid bit ADD[i] of ADD[8:0] and the clock cycle count of the clock signal can be shown in Table 1.

[0121] Table 1

[0122] Clock cycle count ADD[i] Number of generated pulses 1000_0000_0000_0000_0000 ADD[0] 1 ？100_0000_0000_0000_0000 ADD[1] 2 ？？10_0000_0000_0000_0000 ADD[2] 4 ？？？1_0000_0000_0000_0000 ADD[3] 8 ？？？？_1000_0000_0000_0000 ADD[4] 16 ？？？？_？100_0000_0000_0000 ADD[5] 32 ？？？？_？？10_0000_0000_0000 ADD[6] 64 ？？？？_？？？1_0000_0000_0000 ADD[7] 128 ？？？？_？？？？_1000_0000_0000 ADD[8] 256

[0123] Among them, the symbol "?" is "0" or "1", indicating that a pulse will be generated regardless of whether the bit is "0" or "1".

[0124] The number of added pulses is represented as the sum of multiple different exponential powers of 2, and then at least one round of segmentation is performed for any exponential power of 2, wherein in each round of segmentation, a segmentation point is set to divide the interval formed by the previous segmentation point dividing the calibration period into two, and the moment at the segmentation point is used as the first trigger moment, until a number of first trigger moments equal to the exponential power of 2 is obtained, and then pulses with a width of a clock period of a clock signal are generated based on the first trigger moments corresponding to each exponential power of 2, so that the pulse uniformity of the pulse enable signal can be achieved, and then the pulses in the clock signal can be uniformly increased, so that the pulses of the calibrated clock signal are uniform.

[0125] In one embodiment, the generation control unit 1032 is also used to: generate a pulse with a width of one clock cycle of the clock signal after delaying the first trigger moment by a second preset time length, and obtain a pulse enable signal; wherein the second preset time length is an integer multiple of the clock cycle.

[0126] It can be understood that after performing at least one round of segmentation for any exponential power of 2 to obtain the first trigger moments equal to the exponential powers of 2, the pulse can be generated after delaying the second preset time length based on each first trigger moment, so that the pulse uniformity of the pulse enable signal can still be achieved. The second preset time length is an integer multiple of the clock cycle, for example, 1 clock cycle, or 2 clock cycles, and its specific value is not limited thereto.

[0127] In one embodiment, when the pulse calibration number also includes the subtraction pulse number; the generation control unit 1032 is also used to correct the subtraction pulse number according to the detection cycle and the calibration cycle, and generate a subtraction pulse enable signal according to the calibration cycle and the corrected subtraction pulse number; the pulse compensation unit 1031 is also used to reduce the pulse of the clock signal within the calibration cycle to be output according to the clock signal and the subtraction pulse enable signal.

[0128] It can be understood that the reduced pulse number indicates the number of pulses that need to be reduced during the detection cycle, while the pulse compensation unit 1031 reduces the pulse number during the calibration cycle. The detection cycle and the calibration cycle are not necessarily equal, so the reduced pulse number needs to be corrected according to the detection cycle and the calibration cycle.

[0129] The generation control unit 1032 may be provided with a signal generator, and after obtaining the corrected number of pulse reductions, an enable signal is generated. The pulse reduction enable signal generated according to the calibration cycle information and the number of pulse reductions may carry the time information and quantity information of the increase and decrease pulses, which may be used to indicate that a preset number of pulses are reduced at a preset time within the calibration cycle of the clock signal.

[0130] In one embodiment, the generation control unit 1032 is also used for: if the detection period is equal to the calibration period, the number of subtraction pulses is maintained unchanged; if the detection period is greater than the calibration period, [M(T1 / T2)] is used as the corrected number of subtraction pulses; if the detection period is less than the calibration period, M(T1 / T2) is used as the corrected number of subtraction pulses; wherein, [] represents rounding down, M is the number of subtraction pulses before correction, T1 is the calibration period, and T2 is the detection period.

[0131] Among them, both the detection period and the calibration period can be represented as an exponential power of 2. For example, if the detection period is represented as 2 k , the calibration cycle is characterized as 2 n When correcting the number of pulse reduction according to the detection period and calibration period, if the detection period is equal to the calibration period, the number of pulse reduction is not corrected and its value remains M; if the detection period is greater than the calibration period, the proportion of the calibration period in the detection period can be calculated first to obtain 2 n-k , then calculate the product of the number of pulse reduction and the proportion, and round down the product to get the corrected number of pulse reduction [M2 n-k ]; If the detection period is less than the calibration period, after calculating the proportion, the product of the number of subtracted pulses and the proportion can be calculated to obtain the corrected number of added pulses M2 n-k .

[0132] In one embodiment, the calibration period is characterized by 2 n The clock cycle of the clock signal, the corrected number of subtraction pulses is represented by:

[0133]

[0134] Where D is the number of pulses after correction, D j The value of is 0 or 1, j, p and n are natural numbers, and p is less than n.

[0135] The generation control unit 1032 is further used to: if D j If the value of is 1, then in each round of segmentation, a segmentation point is set to divide the interval formed by the previous segmentation point on the calibration period into two, and the moment of the segmentation point is used as the second trigger moment, until 2 is obtained. ja second triggering moment, the former segmentation point being the segmentation point set before the current round of segmentation; a pulse having a width of one clock cycle of the clock signal is generated at each second triggering moment to obtain a pulse reduction enable signal.

[0136] It can be understood that when the calibration period is preset, the calibration period should satisfy the clock period of the clock signal whose value is equal to the exponential power of 2. The number of subtraction pulses is an integer, which can be characterized as the sum of multiple different exponential powers of 2. When generating the subtraction pulse enable signal, for any exponential power of 2, at least one round of segmentation can be performed, wherein in each round of segmentation, a segmentation point is set to divide the interval formed by the previous segmentation point dividing the calibration period into two, and the moment at which the segmentation point is located is used as the second trigger moment until a second trigger moment equal to the exponential power of 2 is obtained. Among them, the specific segmentation action performed in the process of generating the subtraction pulse enable signal can refer to the segmentation action performed on the generation of the addition pulse enable signal in the above embodiment, and will not be repeated here.

[0137] Then, at each second triggering moment, a pulse with a width of one clock cycle of the clock signal is generated. In this way, the pulse uniformity of the pulse reduction enable signal can be achieved, thereby uniformly reducing the pulses in the clock signal, so that the pulses of the calibrated clock signal are uniform.

[0138] Among them, at most one of the number of added pulses and the number of subtracted pulses can be greater than 0. When the number of added pulses and the number of subtracted pulses are both 0, the generated add pulse enable signal and subtract pulse enable signal indicate that the number of pulses to be increased and decreased is 0, and at this time, the pulse compensation unit 1031 does not perform an increase or decrease pulse operation on the clock signal; when the number of added pulses is 0 and the number of subtracted pulses is not 0, the number of increased pulses indicated by the add pulse enable signal is 0, and the number of reduced pulses indicated by the subtracted pulse enable signal is not 0, and at this time, in combination with the clock signal, the pulse compensation unit 1031 only performs a subtracted pulse operation on the clock signal; when the number of added pulses is not 0 and the number of subtracted pulses is 0, the number of increased pulses indicated by the add pulse enable signal is not 0, and the number of reduced pulses indicated by the subtracted pulse enable signal is 0, and at this time, in combination with the clock signal, the pulse compensation unit 1031 only performs an add pulse operation on the clock signal.

[0139] In summary, through the above increase and decrease actions, in 2 n In the clock cycle of a clock signal, a maximum of 20+2 1 +2 2 +……+2 m =2 m+1 -1 pulse, similarly, up to 2 pulses can be reduced p+1 -1 pulse, the calibration range of the system is (-2 p+1 -1, 2 m+1 -1) clock cycles, the calibration resolution is 1 / 2 nThe clock signal is calibrated directly according to the number of added pulses and the number of subtracted pulses, and there is no need to sample the clock signal. The method is simple to implement, thereby simplifying the system structure.

[0140] In one embodiment, Figure 7 As shown, the pulse compensation unit 1031 includes: a first NOT gate 311, a second NOT gate 312, a third NOT gate 313, a first trigger 321, a second trigger 322, a third trigger 323, an AND gate 331, a NAND gate 332, an OR gate 341, a buffer circuit 351 and a two-way selector 361. Among them, the input end of the first NOT gate 311 is connected to the generation control unit 1032 ( Figure 7 The input terminal of the second NOT gate 312 is connected to the clock circuit 100 ( Figure 7 The input end of the first trigger 321 is connected to the output end of the first NOT gate 311, the clock end of the first trigger 321 is connected to the output end of the second NOT gate 312, and the output end of the first trigger 321 is connected to the first input end of the AND gate 331; the second input end of the AND gate 331 is connected to the clock circuit 100, and the output end of the AND gate 331 is connected to the first input end of the two-way selector 361; the input end of the second trigger 322 is connected to the generation control unit 1032, and the output end of the second trigger 322 is respectively connected to the input end of the third trigger 323 and the first input end of the AND gate 332. The input end of the third NOT gate 313 and the clock end of the third trigger 323 are respectively connected to the clock circuit 100, and the output end of the third NOT gate 313 is respectively connected to the first input end of the OR gate 341 and the clock end of the second trigger 322; the output end of the third trigger 323 is connected to the second input end of the NAND gate 332, and the output end of the NAND gate 332 is respectively connected to the second input end of the OR gate 341 and the input end of the buffer circuit 351; the output end of the buffer circuit 351 is connected to the control end of the two-way selector 361, and the output end of the OR gate 341 is connected to the second input end of the two-way selector 361.

[0141] Specific, combined Figure 8As shown, on the one hand, the input end of the first NOT gate 311 receives the subtraction pulse enable signal del_en (taking one pulse as an example in the figure) output by the generation control unit 1032, and after flipping, the reverse subtraction pulse enable signal del_en_n is obtained, and then sent to the input end of the first trigger 321, and the input end of the second NOT gate 312 receives the clock signal src_clk provided by the clock circuit 100, and after flipping, it is sent to the clock end of the first trigger 321, so as to realize the falling edge synchronization of the reverse subtraction pulse enable signal del_en_n with the falling edge of the clock signal src_clk, and obtain the reverse subtraction pulse falling edge synchronization signal del_en_neg. The first input terminal of the AND gate 331 receives the reverse subtraction pulse falling edge synchronization signal del_en_neg, and the second input terminal of the AND gate 331 receives the clock signal src_clk. The AND gate 331 ANDs the reverse subtraction pulse falling edge synchronization signal del_en_neg with the clock signal src_clk to obtain the subtraction pulse output signal clk_del_calr, and outputs it to the first input terminal of the two-way selector 361. It should be understood that due to the influence of the system structure, there may be a delay (for example, 100% delay) between the subtraction pulse enable signal del_en and the clock signal src_clk, and between the reverse subtraction pulse falling edge synchronization signal del_en_neg and the clock signal src_clk. Figure 4 In the embodiment, there is a delay between the pulse generation time of the subtraction pulse enable signal del_en and the rising edge of the corresponding clock signal src_clk, and there is a delay between the falling edge of the reverse subtraction pulse falling edge synchronization signal del_en_neg and the falling edge of the corresponding clock signal src_clk).

[0142] On the other hand, the input end of the second flip-flop 322 receives the pulse enable signal add_en (including one pulse in the figure as an example) output by the generation control unit 1032, and the input end of the third NOT gate 313 receives the clock signal src_clk, which is flipped to obtain the reverse clock signal src_clk_n, which is then sent to the clock end of the second flip-flop 322 and the first input end of the OR gate 341. The second flip-flop 322 implements the falling edge synchronization of the pulse enable signal with the falling edge of the clock signal according to the reverse clock signal src_clk_n and add_en, and obtains the pulse falling edge synchronization signal add_en_neg. The input end of the third trigger 323 receives the pulse falling edge synchronization signal add_en_neg, and the clock end of the third trigger 323 receives the clock signal src_clk, so as to realize the rising edge synchronization of the pulse falling edge synchronization signal add_en_neg using the rising edge of the clock signal src_clk to obtain the pulse rising edge synchronization add_en_pos, and the NAND gate 332 performs NAND operation on the pulse falling edge synchronization signal add_en_neg and the pulse rising edge synchronization add_en_pos to obtain the pre-pulse selection signal add_en_sel_pre. The buffer circuit 351 delays the pre-adding pulse selection signal add_en_sel_pre to obtain the adding pulse selection signal add_en_sel, and provides it to the control end of the two-way selector 361. The OR gate 341 performs an OR operation on the pre-adding pulse selection signal add_en_sel_pre and the reverse clock signal src_clk_n to obtain the additional clock signal ext_clk, and sends it to the second input end of the two-way selector 361. The first input end of the two-way selector 361 can be a high level end 1, and the second input end of the two-way selector 361 can be a low level end 0. Under the drive of the adding pulse selection signal add_en_sel, the calibration output signal clk_calr is finally output. Similarly, it should be understood that due to the influence of the system structure, there may be a delay between the adding pulse enable signal add_en and the clock signal src_clk, between the adding pulse falling edge synchronization signal add_en_neg and the clock signal src_clk, and between the adding pulse rising edge synchronization add_en_pos and the clock signal src_clk.

[0143] In one embodiment, the buffer circuit 351 may include a plurality of buffers connected in series.

[0144] like Figure 8 As shown, taking three buffers as an example, buffer 01, buffer 02 and buffer 03 are connected in series in sequence to delay the pre-add pulse selection signal add_en_sel_pre. The number of buffers can be set as needed to adjust the delay time, so that the added pulse reaches the desired width.

[0145] An embodiment of the present invention further provides a clock calibration device, comprising a clock circuit and the clock calibration circuit described in any one of the above embodiments.

[0146] The working principle and beneficial effects of the clock calibration device of this embodiment can be referred to the above-mentioned clock calibration circuit embodiment, which will not be described in detail here.

[0147] The embodiment of the present invention further provides a clock calibration method, which is applied to a clock circuit, and the clock circuit is used to provide a clock signal. Fig. 9 As shown, the clock calibration method includes steps S110 to S140.

[0148] Step S110, dividing the clock signal by using the detection period as the frequency division coefficient to obtain a frequency division signal.

[0149] Step S120, within a time range of a first preset time length from a detection cycle detection termination moment when there is only one valid edge of the reference clock signal, the valid edge of the reference clock signal is detected using the clock signal to obtain a detection result.

[0150] Step S130, determining the pulse calibration quantity, the detection start time and the frequency division start time of the next detection cycle according to the detection result, and correcting the frequency division signal of the next detection cycle.

[0151] Step S140 , performing pulse calibration on the clock signal within the calibration period to be output according to the detection period, the clock signal, the calibration period and the pulse calibration quantity.

[0152] The working principle and beneficial effects of the clock calibration method according to the embodiment of the present invention have been specifically described in the above-mentioned clock calibration circuit, and will not be described in detail here.

[0153] In one embodiment, when there is only one valid edge of the reference clock signal and within a time range of a first preset time length from the detection termination moment of the detection period, the valid edge of the reference clock signal is detected with a clock signal, and the step of obtaining the detection result includes: generating a window detection signal according to the detection period and the first preset time length, wherein the valid pulse of the window detection signal corresponds to the valid edge of a reference clock signal, and the two ends of the valid pulse of the window detection signal are respectively different from the detection termination moment by a first preset time length; based on the window detection signal, the valid edge of the reference clock signal is detected with the clock signal to obtain the detection result.

[0154] In one embodiment, the detection result includes the situation that the effective edge of the reference clock signal is detected until the detection termination time, and the duration information between the detection time when the effective edge is detected and the detection termination time; the duration information is represented as a first number of clock cycles, and the pulse calibration number includes the number of added pulses; the pulse calibration number, the detection start time and the frequency division start time of the next detection cycle are determined according to the detection result, and the step of correcting the frequency division signal of the next detection cycle includes: if the effective edge is detected before the detection termination time, the first number is used as the number of added pulses; the detection time is used as the detection start time and the frequency division start time; the effective pulse of the frequency division signal is adjusted so that the effective pulse of the frequency division signal is generated at the detection time; wherein, the number of added pulses is used to indicate the number of increased pulses.

[0155] In one embodiment, the first preset duration is the clock cycle of the second number of the clock signal. Before taking the first number as the step of adding the pulse number, the clock calibration method also includes: at the time when the effective pulse of the window detection signal is generated, counting down the clock cycle of the clock signal with the second number as the initial value until a valid edge is detected before the detection termination time, and taking the second number at the end of the counting as the first number.

[0156] In one embodiment, the pulse calibration number also includes the subtraction pulse number, and the pulse calibration number, detection start time and frequency division start time of the next detection cycle are determined according to the detection results, and the step of correcting the frequency division signal of the next detection cycle includes: if no valid edge is detected by the end time of the detection, the first number is used as the subtraction pulse number; wherein the subtraction pulse number is used to indicate the reduction of the number of pulses; the detection time is used as the detection start time and the frequency division start time; and the frequency division signal is maintained.

[0157] In one embodiment, before taking the first number as the step of reducing the number of pulses, the clock calibration method further includes: taking 0 as the initial value to count the clock cycles of the clock signal to obtain a count value until a valid edge is detected, and taking the count value at the end of the counting as the first number.

[0158] In one embodiment, the step of performing pulse calibration on the clock signal within the calibration cycle to be output according to the detection cycle, the clock signal, the calibration cycle and the pulse calibration number includes: correcting the number of added pulses according to the detection cycle and the calibration cycle, and generating a pulse add enable signal according to the calibration cycle and the corrected number of added pulses; and increasing the pulses of the clock signal within the calibration cycle to be output according to the clock signal and the pulse add enable signal.

[0159] In one embodiment, the step of correcting the number of added pulses according to the detection period and the calibration period includes: if the detection period is equal to the calibration period, the number of added pulses is maintained unchanged; if the detection period is greater than the calibration period, [N(T1 / T2)] is used as the corrected number of added pulses; if the detection period is less than the calibration period, N(T1 / T2) is used as the corrected number of added pulses; wherein, [] indicates rounding down, N is the number of added pulses before correction, T1 is the calibration period, and T2 is the detection period.

[0160] In one embodiment, the calibration period is characterized by 2 n The clock cycle of the clock signal, the corrected number of pulses is represented by:

[0161]

[0162] Among them, A is the number of pulses added after correction, A i The value of i is 0 or 1, i, m and n are natural numbers, and m is less than n; the step of generating a pulse enable signal according to the calibration period and the corrected pulse number includes: if A i If the value of is 1, then in each round of segmentation, a segmentation point is set to divide the interval formed by the previous segmentation point on the calibration period into two, and the moment of the segmentation point is used as the first trigger moment, until 2 is obtained. i A first trigger moment, the front division point is a division point set before the current round division; based on the first trigger moment, a pulse with a width of one clock cycle of the clock signal is generated to obtain a pulse enable signal.

[0163] In one embodiment, based on the first trigger moment, a pulse with a width of one clock cycle of the clock signal is generated, and the step of obtaining a pulse enable signal includes: after delaying the first trigger moment by a second preset time length, a pulse with a width of one clock cycle of the clock signal is generated to obtain a pulse enable signal; wherein the second preset time length is an integer multiple of the clock cycle.

[0164] In one embodiment, when the pulse calibration number also includes the subtraction pulse number; the step of performing pulse calibration on the clock signal within the calibration cycle to be output according to the detection cycle, the clock signal, the calibration cycle and the pulse calibration number also includes: correcting the subtraction pulse number according to the detection cycle and the calibration cycle, and generating a subtraction pulse enable signal according to the calibration cycle and the corrected subtraction pulse number; reducing the pulses of the clock signal within the calibration cycle to be output according to the clock signal and the subtraction pulse enable signal.

[0165] In one embodiment, the step of correcting the number of subtraction pulses according to the detection period and the calibration period includes: if the detection period is equal to the calibration period, the number of subtraction pulses is maintained unchanged; if the detection period is greater than the calibration period, [M(T1 / T2)] is used as the corrected number of subtraction pulses; if the detection period is less than the calibration period, M(T1 / T2) is used as the corrected number of subtraction pulses; wherein, [] represents rounding down, M is the number of subtraction pulses before correction, T1 is the calibration period, and T2 is the detection period.

[0166] In one embodiment, the calibration period is characterized by 2 n The clock cycle of the clock signal, the corrected number of subtraction pulses is represented by:

[0167]

[0168] Where D is the number of pulses after correction, D j The value of is 0 or 1, j, p and n are natural numbers, and p is less than n; the step of generating a pulse reduction enable signal according to the calibration period and the corrected pulse reduction number also includes: if D j If the value of is 1, then in each round of segmentation, a segmentation point is set to divide the interval formed by the previous segmentation point on the calibration period into two, and the moment of the segmentation point is used as the second trigger moment, until 2 is obtained. j a second triggering moment, the former segmentation point being the segmentation point set before the current round of segmentation; a pulse having a width of one clock cycle of the clock signal is generated at each second triggering moment to obtain a pulse reduction enable signal.

[0169] Another embodiment of the present invention further provides a clock calibration method, comprising steps (a1) to (a12).

[0170] Step (a1), dividing the clock signal by using the detection period as the frequency division coefficient to obtain a frequency division signal.

[0171] Step (a2), generating a window detection signal according to the detection period and the first preset time length, wherein a valid pulse of the window detection signal corresponds to a valid edge of the reference clock signal, and both ends of the valid pulse of the window detection signal are respectively different from the detection termination moment by the first preset time length; based on the window detection signal, the valid edge of the reference clock signal is detected with the clock signal to obtain the detection result.

[0172] Step (a3), the detection result includes the situation that the effective edge of the reference clock signal is detected by the detection termination time, and the time length information between the detection time when the effective edge is detected and the detection termination time; the time length information is characterized as a first number of clock cycles, and the pulse calibration number includes the number of added pulses. The first preset time length is a second number of clock cycles of the clock signal. If the effective edge is detected before the detection termination time, at the time when the effective pulse of the window detection signal is generated, the clock cycle of the clock signal is counted down with the second number as the initial value until the effective edge is detected before the detection termination time, and the second number at the end of the counting is used as the first number; the first number is used as the number of added pulses; the detection time is used as the detection start time and the frequency division start time; the effective pulse of the frequency division signal is adjusted so that the effective pulse of the frequency division signal is generated at the detection time; wherein the number of added pulses is used to indicate the number of increased pulses.

[0173] Step (a4): if the detection period is equal to the calibration period, the number of added pulses is maintained unchanged; if the detection period is greater than the calibration period, [N(T1 / T2)] is used as the corrected number of added pulses; if the detection period is less than the calibration period, N(T1 / T2) is used as the corrected number of added pulses; wherein [] represents rounding down, N is the number of added pulses before correction, T1 is the calibration period, and T2 is the detection period.

[0174] Step (a5), the calibration cycle is characterized as 2 n The clock cycle of the clock signal, the corrected number of pulses is represented by:

[0175]

[0176] Among them, A is the number of pulses added after correction, A i The value of is 0 or 1, i, m and n are natural numbers, and m is less than n; if A i If the value of is 1, then in each round of segmentation, a segmentation point is set to divide the interval formed by the previous segmentation point on the calibration period into two, and the moment of the segmentation point is used as the first trigger moment, until 2 is obtained. i A first trigger moment, the front division point is the division point set before the current round; after the first trigger moment is delayed by a second preset time length, a pulse with a width of one clock cycle of the clock signal is generated to obtain a pulse enable signal; wherein the second preset time length is an integer multiple of the clock cycle.

[0177] Step (a6), increasing the pulse of the clock signal within the calibration period to be output according to the clock signal and the pulse adding enable signal.

[0178] Step (a7), the pulse calibration number also includes the number of subtracted pulses. If no valid edge is detected by the end of the detection, the clock signal clock cycle is counted incrementally with 0 as the initial value to obtain the count value until the valid edge is detected. The count value at the end of the count is used as the first number; the first number is used as the number of subtracted pulses; the detection time is used as the detection start time and the frequency division start time; the frequency division signal is maintained; wherein the number of subtracted pulses is used to indicate the number of reduced pulses.

[0179] Step (a8): if the detection period is equal to the calibration period, the number of subtraction pulses is maintained unchanged; if the detection period is greater than the calibration period, [M(T1 / T2)] is used as the corrected number of subtraction pulses; if the detection period is less than the calibration period, M(T1 / T2) is used as the corrected number of subtraction pulses; wherein [] represents rounding down, M is the number of subtraction pulses before correction, T1 is the calibration period, and T2 is the detection period.

[0180] Step (a9), the calibration cycle is characterized as 2 n The clock cycle of the clock signal, the corrected number of subtraction pulses is represented by:

[0181]

[0182] Where D is the number of pulses after correction, D j The value of is 0 or 1, j, p and n are natural numbers, and p is less than n; the step of generating a pulse reduction enable signal according to the calibration period and the corrected pulse reduction number also includes: if D j If the value of is 1, then in each round of segmentation, a segmentation point is set to divide the interval formed by the previous segmentation point on the calibration period into two, and the moment of the segmentation point is used as the second trigger moment, until 2 is obtained. j a second triggering moment, the former segmentation point being the segmentation point set before the current round of segmentation; a pulse having a width of one clock cycle of the clock signal is generated at each second triggering moment to obtain a pulse reduction enable signal.

[0183] Step (a10), reducing the pulse of the clock signal within the calibration period to be output according to the clock signal and the pulse reduction enable signal.

[0184] It should be understood that although the above Fig. 9 In the flowchart, each step is shown in sequence as indicated by the arrows, and each step in step (a1) to step (a10) is shown in sequence as indicated by the numbers, but these steps are not necessarily performed in the order indicated by the arrows or numbers. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be performed in other orders. Moreover, Fig. 9At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily one by one, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0185] The above description is only a preferred embodiment of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A clock calibration circuit, characterized in that: Applied to a clock circuit, the clock circuit is used to provide a clock signal, and the clock calibration circuit includes: A frequency division module, connected to the clock circuit, for performing frequency division processing on the clock signal with a detection period as a frequency division coefficient to obtain a frequency division signal; A detection module is used to be connected to the clock circuit and the frequency division module, and is used to: In a time range where there is only one valid edge of the reference clock signal and the first preset time length from the detection termination time of the detection period, the valid edge of the reference clock signal is detected by the clock signal to obtain a detection result; the detection result includes the situation that the valid edge of the reference clock signal is detected up to the detection termination time, and the time length information between the detection time of the valid edge and the detection termination time; Determine the pulse calibration quantity, detection start time and frequency division start time of the next detection cycle according to the detection result, and correct the frequency division signal of the next detection cycle; A calibration module is used to be connected to the clock circuit and to be connected to the detection module, and is used to perform pulse calibration on the clock signal within the calibration period to be output according to the detection period, the clock signal, the calibration period and the pulse calibration quantity.

2. The clock calibration circuit according to claim 1, characterized in that: The detection module is also used for: Generate a window detection signal according to the detection period and the first preset time length, wherein a valid pulse of the window detection signal corresponds to a valid edge of the reference clock signal, and both ends of the valid pulse of the window detection signal are respectively different from the detection termination time by the first preset time length; Based on the window detection signal, the effective edge of the reference clock signal is detected with the clock signal to obtain the detection result.

3. The clock calibration circuit according to claim 2, characterized in that: The duration information is characterized as a first number of clock cycles of the clock signal; the pulse calibration number includes the number of added pulses; the detection module is further configured to: if the valid edge is detected before the detection termination time, then: Using the first number as the number of added pulses; Taking the detection time as the detection start time and the frequency division start time; Adjusting the effective pulse of the frequency-divided signal so that the effective pulse of the frequency-divided signal is generated at the detection time; The added pulse quantity is used to indicate the quantity of increased pulses.

4. The clock calibration circuit according to claim 3, characterized in that: The first preset duration is a second number of clock cycles of the clock signal, and the detection module is further used for: At the time when the effective pulse of the window detection signal is generated, the clock cycle of the clock signal is counted down with the second number as the initial value until the effective edge is detected before the detection termination time, and the second number at the end of the counting is used as the first number.

5. The clock calibration circuit according to claim 3, characterized in that: The pulse calibration quantity also includes the number of subtraction pulses, and the detection module is further configured to: if the valid edge is not detected by the detection termination time, The first number is used as the number of pulses to be reduced; wherein the number of pulses to be reduced is used to indicate the number of pulses to be reduced; Taking the detection time as the detection start time and the frequency division start time; The divided frequency signal is maintained.

6. The clock calibration circuit according to claim 5, characterized in that: The detection module is also used for: If the valid edge is not detected by the time the detection ends, the clock cycle of the clock signal is incremented with 0 as the initial value to obtain a count value until the valid edge is detected, and the count value at the end of the counting is used as the first quantity.

7. The clock calibration circuit according to claim 3 or 5, characterized in that: The calibration module comprises: A generation control unit connected to the detection module, configured to correct the number of added pulses according to the detection period and the calibration period, and generate a pulse addition enable signal according to the calibration period and the corrected number of added pulses; A pulse compensation unit is connected to the generation control unit and the clock circuit respectively, and is used to increase the pulse of the clock signal within the calibration period to be output according to the clock signal and the pulse adding enable signal.

8. The clock calibration circuit according to claim 7, characterized in that: The generation control unit is also used for: If the detection period is equal to the calibration period, the number of added pulses is maintained unchanged; If the detection period is greater than the calibration period, [N(T1 / T2)] is used as the corrected number of added pulses; If the detection period is less than the calibration period, N(T1 / T2) is used as the corrected number of added pulses; Wherein, [] represents rounding down, N is the number of pulses before correction, T1 is the calibration period, and T2 is the detection period.

9. The clock calibration circuit according to claim 7, characterized in that:The calibration cycle is characterized as 2 n The corrected number of pulses is represented by: Wherein, A is the corrected number of pulses, A i The value of is 0 or 1, i, m and n are natural numbers, and m is less than n; The generation control unit is also used for: If A i The value of is 1, then in each round of segmentation, a segmentation point is set to divide the interval formed by the previous segmentation point on the calibration period into two, and the moment of the segmentation point is used as the first trigger moment, until 2 is obtained. i the first triggering moment, the previous segmentation point is a segmentation point set before the current round of segmentation; Based on the first triggering moment, a pulse having a width of one clock cycle of the clock signal is generated to obtain the pulse adding enable signal.

10. The clock calibration circuit according to claim 9, characterized in that: The generation control unit is also used for: After the first trigger moment is delayed by a second preset time length, a pulse with a width of one clock cycle of the clock signal is generated to obtain the pulse enable signal; wherein the second preset time length is an integer multiple of the clock cycle.

11. The clock calibration circuit according to claim 7, characterized in that: When the pulse calibration number also includes a subtraction pulse number; The generation control unit is further used to correct the number of subtraction pulses according to the detection period and the calibration period, and generate a subtraction pulse enable signal according to the calibration period and the corrected number of subtraction pulses; The pulse compensation unit is further configured to reduce the pulse of the clock signal within the calibration period to be output according to the clock signal and the pulse reduction enable signal.

12. The clock calibration circuit according to claim 11, characterized in that: The generation control unit is also used for: If the detection period is equal to the calibration period, the number of the subtraction pulses is maintained unchanged; If the detection period is greater than the calibration period, [M(T1 / T2)] is used as the corrected number of subtraction pulses; If the detection period is less than the calibration period, M(T1 / T2) is used as the corrected number of subtraction pulses; Wherein, [] represents rounding down, M is the number of the subtraction pulses before correction, T1 is the calibration period, and T2 is the detection period.

13. The clock calibration circuit according to claim 11, characterized in that: The calibration cycle is characterized as 2 n The clock cycle of the clock signal, the corrected number of the subtraction pulses is characterized by: Wherein, D is the number of pulses after correction, D j The value of is 0 or 1, j, p and n are natural numbers, and p is less than n; The generation control unit is also used for: If D j The value of is 1, then in each round of segmentation, a segmentation point is set to divide the interval formed by the previous segmentation point on the calibration period into two, and the moment of the segmentation point is used as the second triggering moment, until 2 is obtained. j the second triggering moment, the previous segmentation point is a segmentation point set before the current round of segmentation; At each of the second trigger moments, a pulse with a width equal to one clock cycle of the clock signal is generated to obtain the pulse reduction enable signal.

14. The clock calibration circuit according to claim 11, characterized in that: The pulse compensation unit includes: a first NOT gate, a second NOT gate, a third NOT gate, a first trigger, a second trigger, a third trigger, an AND gate, a NAND gate, an OR gate, a buffer circuit and a two-way selector; Wherein, the input end of the first NOT gate is connected to the generation control unit, and the input end of the second NOT gate is used to be connected to the clock circuit; The input terminal of the first trigger is connected to the output terminal of the first NOT gate, the clock terminal of the first trigger is connected to the output terminal of the second NOT gate, and the output terminal of the first trigger is connected to the first input terminal of the AND gate; The second input terminal of the AND gate is connected to the clock circuit, and the output terminal of the AND gate is connected to the first input terminal of the two-way selector; The input terminal of the second trigger is connected to the generation control unit, and the output terminal of the second trigger is respectively connected to the input terminal of the third trigger and the first input terminal of the NAND gate; The input end of the third NOT gate and the clock end of the third flip-flop are respectively connected to the clock circuit, and the output end of the third NOT gate is respectively connected to the first input end of the OR gate and the clock end of the second flip-flop; The output end of the third trigger is connected to the second input end of the NAND gate, and the output end of the NAND gate is connected to the second input end of the OR gate and the input end of the buffer circuit respectively; The output end of the buffer circuit is connected to the control end of the two-way selector, and the output end of the OR gate is connected to the second input end of the two-way selector.

15. A clock calibration device, characterized in that: The device comprises: Clock circuit; And the clock calibration circuit according to any one of claims 1 to 14.

16. A clock calibration method, characterized in that: Applied to a clock circuit, the clock circuit is used to provide a clock signal, and the clock calibration method includes: Performing frequency division processing on the clock signal using the detection period as the frequency division coefficient to output a frequency division signal; In a time range where there is only one valid edge of the reference clock signal and the first preset time length from the detection termination time of the detection period, the valid edge of the reference clock signal is detected by the clock signal to obtain a detection result; the detection result includes the situation that the valid edge of the reference clock signal is detected up to the detection termination time, and the time length information between the detection time of the valid edge and the detection termination time; Determine the pulse calibration quantity, detection start time and frequency division start time of the next detection cycle according to the detection result, and correct the frequency division signal of the next detection cycle; Pulse calibration is performed on the clock signal within the calibration period to be output according to the detection period, the clock signal, the calibration period and the pulse calibration number.

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