Control method for coupling time stamp of EtherMAC digital signal
By selecting the local clock of the slave station as the system clock in the EtherMAC network, generating the synchronous signal timestamp and performing the timestamp conversion, the problem that EtherMAC cannot generate the timestamp and control the output signal is solved, and precise coupling control of digital signals is realized , expands the application space and improves the replacement rate of domestically produced autonomous motion control buses.
Patent Information
- Application Number
- CN202210858600.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-07-21
- Publication Date
- 2025-01-03
- Estimated Expiration
- 2042-07-21
AI Technical Summary
EtherMAC lacks a global network system clock that is shared by both the master and slave stations, and cannot generate a time stamp for the digital input signal, nor can it control the output of the digital signal at a given time stamp, which limits its application field.
Design a method to generate a synchronous signal timestamp by selecting the local clock of the slave station in the EtherMAC network as the system clock, and converting absolute time and relative time between the master station and the slave station to realize the digital signal and Coupled control of timestamps. The specific steps include generating a synchronization signal time stamp and sending it to the main station, the main station calculates the synchronization cycle start time, the slave station calculates the time offset value and sends it to the main station, and the main station calculates the delay time of the output signal according to the communication timing to Ensure accurate output.
It provides EtherMAC with global system network time, dynamically offsets node clock jitter and drift, realizes the precise timestamp of digital input signals and the precise triggering of output signals, expands application space, and improves the replacement rate of domestically produced autonomous motion control buses.
Smart Images
Figure CN115242343B_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the field of industrial Ethernet, and in particular to a control method for coupling time stamps of digital signal transmission in EtherMAC industrial real-time Ethernet. Background Art
[0002] The motion control bus based on industrial Ethernet has the advantages of high communication rate, good anti-interference performance, strong real-time performance, etc., and has gradually replaced the traditional pulse and analog interface methods between the motion controller and the servo drive. The digital characteristics of the motion control bus transform the entire motion control system into a fully digital whole. As a result, more open data interaction can be achieved between the motion controller and the servo drive, and on this basis, better control algorithms can be designed, which indirectly improves the overall performance of the motion control system.
[0003] EtherMAC is an industrial real-time Ethernet developed independently by China for motion control technology. After years of technical accumulation, it has become more and more perfect and has been widely used in the field of motion control. EtherMAC is based on the standard industrial Ethernet physical layer, with a data transmission rate of 100Mbps and a lumped frame communication method, which can support up to 255 slave nodes. The data transmission between slaves uses a specially designed EtherMAC protocol stack chip to ensure the time certainty of data forwarding. Its own synchronization management mechanism makes the synchronization signal jitter between slave nodes <1μs. The master station adopts a response mechanism based on network data reception, without the need for a precise and strict real-time timer.
[0004] EtherCAT is an industrial real-time Ethernet developed by Beckhoff of Germany. Its own distributed clock mechanism enables the master and slave stations to share a global system clock. Based on this global system clock, precise timestamps can be generated for sampled signals, and control signals can be output when the specified precise timestamp arrives.
[0005] Compared with EtherCAT, EtherMAC lacks a global network system clock that is shared by the master and slaves. It cannot generate a timestamp based on the global system clock for digital input signals, nor can it control the output of digital signals at a given timestamp, which limits its application areas. Therefore, in order to solve this technical problem, it is necessary to design a global network system clock for EtherMAC to achieve the coupling control of digital input and output signals and timestamps. Summary of the invention
[0006] The invention proposes a control method for coupling time stamp of EtherMAC digital quantity signal, the purpose of which is to provide a unified common global clock for EtherMAC digital quantity signal and realize coupling control of digital quantity signal and time stamp.
[0007] The technical solution of the present invention is as follows:
[0008] A control method for coupling timestamp of EtherMAC digital signal, the target device of the method is an EtherMAC network formed by connecting a master station and slave stations, each slave station synchronously generates a periodic synchronization signal, the time period between each two adjacent synchronization signals is a synchronization period, and the local clock of one of the slave stations is selected as the system clock of the EtherMAC network;
[0009] When the master station communicates with the slave station: the selected slave station generates a synchronization signal based on the local clock of the slave station while generating the synchronization signal. ss , and the synchronization signal timestamp t ss sent to the master station; and the master station uses the synchronization signal timestamp t ss Calculate the start time of the current synchronization cycle and complete the conversion between absolute time and relative time; and use relative time between the master station and the slave station to describe the relevant time of the digital signal;
[0010] The absolute time refers to the time under the system clock, and the relative time refers to the time relative to the start time of the current synchronization cycle.
[0011] As a further improvement of the control method for coupling timestamp of EtherMAC digital signal, the starting time t cs Equal to the synchronization signal timestamp t received by the master station during this synchronization cycle ss and two synchronization periods T c sum.
[0012] As a further improvement of the control method for coupling timestamp of EtherMAC digital signal, when the slave collects the digital input signal, the time offset value t of the collection time relative to the start time of the current synchronization cycle, i.e., the time when the previous synchronization signal was generated, is calculated. rsi , the slave uploads the digital input signal and at the same time rsi Send to the main station together;
[0013] After the master station receives the digital input signal uploaded by the slave station, it timestamps the synchronization signal received during this synchronization cycle. ss With t rsi Sum and get the absolute time t when the slave collects the digital input signal asi .
[0014] As a further improvement of the control method for coupling timestamp of EtherMAC digital signal, when the master station sends a digital output signal to the slave station, the absolute time when the expected digital output signal is output by the slave station is t aso , the master station calculates the starting time t of the synchronization cycle when the slave station outputs the digital output signal according to the communication timing between the master station and the slave station. os and the end time t oe ; if t os ≤t aso <t oe , then the master station will t aso Subtract t os Get the delay time t of the slave output signal rso , and then the digital output signal and t rso Send to slave station at the same time;
[0015] After receiving the digital output signal, the slave station delays the output of the digital output signal based on the start time of the current synchronization cycle. The delay time is equal to the received t rso .
[0016] Compared with the prior art, the present invention has the following beneficial effects: (1) The present invention provides a global system network time for EtheMAC, so that the EtherMAC slave station and the master station can share a unified network system clock; (2) The global system network time of the present invention uses the synchronization signal of the EtherMAC slave station as the time reference, which can dynamically offset the clock jitter and drift between nodes, and has the characteristics of high precision and low jitter; (3) The present invention can provide a coupled precise timestamp for the digital input signal collected by the slave station. The timestamp is based on the clock at the start of the synchronization cycle (i.e., the generation time of the synchronization signal), and generates a corresponding relative timestamp (time offset value t rsi ), the master station receives the time offset value t rsi Then it can be combined with the synchronization signal timestamp t ssThe time when the slave station collects the digital input signal based on the system clock is obtained, thereby meeting the application requirements for signal collection with a timestamp; (4) The present invention adds a digital output signal coupling timestamp function to the EtherMAC network. The timestamp is the delay time of the expected output time of the digital output signal relative to the synchronization signal calculated in advance by the master station based on the start time of the synchronization cycle (i.e., the generation time of the synchronization signal). The slave station responsible for sending the digital output signal outputs the signal according to the specified delay time within the synchronization cycle, thereby meeting the application requirements for outputting the control signal at a precise time; (5) The present invention is only implemented and designed at the application layer in network communication, without modifying the existing EtherMAC hardware protocol stack, and has good compatibility with the existing EtherMAC solution.
[0017] In summary, this method provides a digital signal coupling precision time mechanism for EtherMAC, which not only establishes the global system time for the network, but also provides a precise timestamp for the digital input signal, and at the same time provides a precise timestamp mechanism for the triggering of the digital output signal. It has the characteristics of strong practicality and high signal timestamp accuracy, which can effectively expand the application space of EtherMAC, improve the success rate of domestic autonomous motion control bus replacing foreign ones, and has good application prospects. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] Figure 1 This is a structural diagram of the EtherMAC network.
[0019] Figure 2 This is the timing diagram when EtherMAC adopts communication timing A.
[0020] Figure 3 This is the timing diagram when EtherMAC adopts communication timing B.
[0021] Figure 4 A schematic diagram of generating a coupling time stamp for a digital input signal and outputting a signal according to the coupling time stamp of a digital output signal when communication sequence A is adopted for EtherMAC. In this figure, there is no correlation between the digital input signal and the digital output signal.
[0022] Figure 5 A schematic diagram of generating a coupling time stamp for a digital input signal and outputting a signal according to the coupling time stamp of a digital output signal when communication sequence B is adopted for EtherMAC. In this figure, there is no correlation between the digital input signal and the digital output signal.
[0023] Figure 6This is a timing relationship diagram between the EtherMAC master station and the digital signal action interval. In the figure, DO_A represents the time of outputting the signal under timing A, and DO_B represents the time of outputting the signal under timing B. One of the purposes of this figure is to compare the action time of the two timing relationships. In actual operation, timing A and B cannot exist in the same network at the same time.
[0024] Figure 7 Schematic diagram of the time stamp generation process for digital input signals.
[0025] Figure 8 It is a schematic diagram of the flow of controlling the output of the digital output signal in the present invention. DETAILED DESCRIPTION
[0026] The technical solution of the present invention is described in detail below with reference to the accompanying drawings:
[0027] This embodiment provides a control method for coupling timestamps of EtherMAC digital signals, wherein the target device of the method is an EtherMAC network formed by connecting a master station and slave stations. Figure 1 , the master station and the slave stations are connected by Ethernet cables. Each slave station has two Ethernet interfaces. The first slave station is connected to the master station through an Ethernet port, and then the adjacent slave stations are connected to the network through the Ethernet port. Each slave station mainly includes an EtherMAC protocol stack chip and an application processor. The EtherMAC protocol stack chip is responsible for processing EtherMAC network communications, and at the same time realizes data interaction with the application processor through the data communication interface. After EtherMAC enters the periodic communication state, the EtherMAC protocol stack chips of all slave stations will synchronize and periodically generate synchronization signals to the application processor. The time period between adjacent synchronization signals is called the synchronization period (assuming the period time length is T c ), that is, each synchronization cycle starts at the synchronization signal trigger time. The synchronization signals of all slave nodes are generated and triggered at the same time, and the synchronization signal jitter is <1μs.
[0028] EtherMAC has two communication timings: A and B.
[0029] like Figure 2, when using timing A, in each synchronization cycle, the master station first receives the data uploaded by the slave station: the farthest slave station sends the data to be uploaded to the second-to-last slave station, and then each slave station sends the data to be uploaded by this node together with the data sent by the previous slave station node to the next slave station, and finally summarizes them to the master station. Then, the master station sends the data prepared in the previous synchronization cycle to the slave station: the first slave station receives all the data sent by the master station, takes out the data sent to this slave station node, and then transmits the remaining data to the second slave station, and then each slave station keeps the data sent to this node and sends the remaining data to the next slave station node until it is sent to the farthest slave station. Finally, the master station processes the slave station data received in this synchronization cycle, and the processed data to be sent is kept until the next synchronization cycle and then sent to the slave station.
[0030] like Figure 3 ,When timing B is adopted, in each synchronization cycle, the master station first receives the data uploaded by the slave station, and then immediately processes the slave station data received in this synchronization cycle, and finally sends the processed data to be sent to the slave station in this synchronization cycle.
[0031] It can be seen that, relative to timing B, the master station will delay sending data by one synchronization cycle under timing A.
[0032] It should be noted that due to the unique design mechanism of EtherMAC, the master station can be implemented with a standard network card, and the master station protocol stack code can be implemented with software. Therefore, there is time jitter in the master station's response delay to the slave station data, that is, T d The values are different, and the system cannot know the exact T d This is also one of the reasons why the existing EtherMAC network cannot obtain the accurate acquisition time of digital input signals and cannot control the correct output of digital output signals at the exact moment.
[0033] For the existing EtherMAC network, this method proposes the following improvements:
[0034] First, select the local clock of one of the slaves as the system clock of the EtherMAC network.
[0035] Then, when the master station communicates with the slave station: the selected slave station generates a synchronization signal based on the local clock of the slave station while generating the synchronization signal. ss , and the synchronization signal timestamp t ss sent to the master station; and the master station uses the synchronization signal timestamp t ssCalculate the start time of the current synchronization cycle and complete the conversion between absolute time and relative time; and use relative time to describe the relevant time of digital signals between the master station and the slave station. The absolute time refers to the time under the system clock, and the relative time refers to the time relative to the start time of the current synchronization cycle.
[0036] Specifically, Figures 4 to 6 When the master station communicates with the slave station, no matter which timing is used, the digital input signal collected by the slave station in the Mth synchronization cycle will be added to the data to be uploaded in the M+1th synchronization cycle, and uploaded to the master station in the M+2th synchronization cycle. Therefore, the master station will delay receiving the digital input signal by 2 synchronization cycles. Based on this, if Figure 6 and 7 , the master station can calculate the start time t of the current synchronization cycle (i.e. the synchronization cycle in which the uploaded data is processed) cs Equal to the synchronization signal timestamp t received by the master station during this synchronization cycle ss and two synchronization periods T c Sum: t cs =t ss +2T c .
[0037] Furthermore, for digital input signals:
[0038] like Figures 4 to 6 As mentioned above, no matter which timing is used, the digital input signal collected by the slave in the Mth synchronization cycle will be added to the data to be uploaded in the M+1th synchronization cycle, and uploaded to the master in the M+2th synchronization cycle. In the present invention, when the slave collects the digital input signal, it also calculates the collection time t asir The time offset value t relative to the start time of the current synchronization cycle, that is, the time when the previous synchronization signal was generated rsi =t asir -t ss , and use it as a relative timestamp. When the slave uploads the digital input signal, it will use the relative timestamp t rsi Send it to the master station. Figure 7 After the master station receives the digital input signal uploaded by the slave station, it timestamps the synchronization signal received at the same time in this synchronization cycle. ss (This timestamp comes from the selected slave station, not necessarily from the slave station that collected the signal) and t rsi By summing, we can get the absolute time t when the slave collects the digital input signal. asi = t ss + t rsi .
[0039] For digital output signals:
[0040] like Figure 8 When the master station sends a digital output signal to the slave station, the absolute time when the expected digital output signal is output by the slave station is t aso The master station can calculate the starting time t of the synchronization cycle when the slave station outputs the digital output signal based on the communication timing between the master station and the slave station. os and the end time t oe In this step, the two timing situations are different: Figure 6 When using timing A, after the master station completes data processing in the Nth synchronization cycle, it will send data to the slave station in the N+1th synchronization cycle. After receiving the data, the slave station will output a signal in the N+2th synchronization cycle. Therefore, t os_1 =T cs +2T c =t ss +4T c , t oe_1 = T cs +3T c =t ss +5T c When using timing B, the master station will immediately send data to the slave station after completing data processing in the Nth synchronization cycle, and the slave station will output the signal in the N+1th synchronization cycle, so t os_2 =T cs +T c =t ss +3T c , t oe_2 = T cs +2T c =t ss +4T c Next, the master station makes a judgment: If t os ≤t aso <t oe , indicating that the output signal should be sent out by the master station in this synchronization cycle. The master station will aso Subtract t os Get the delay time t of the slave output signal rso t aso -t os , and then the digital output signal and t rso When the slave station receives the digital output signal and outputs it, it delays the output of the digital output signal based on the start time of the current synchronization cycle, and the delay time is equal to the received t rso , thus ensuring that the signal is output at the correct time.
Claims
1. A control method for coupling timestamp of EtherMAC digital signal, wherein the target device of the method is an EtherMAC network formed by connecting a master station and slave stations, each slave station synchronously generates a periodic synchronization signal, and the time period between each two adjacent synchronization signals is a synchronization period, characterized in that: Select the local clock of one of the slaves as the system clock of the EtherMAC network; When the master station communicates with the slave station: the selected slave station generates a synchronization signal based on the local clock of the slave station while generating the synchronization signal. ss , and the synchronization signal timestamp t ss sent to the master station; and the master station uses the synchronization signal timestamp t ss Calculate the start time of the current synchronization cycle and complete the conversion between absolute time and relative time; and use relative time between the master station and the slave station to describe the relevant time of the digital signal; The absolute time refers to the time under the system clock, and the relative time refers to the time relative to the start time of the current synchronization cycle; The start time t of the current synchronization cycle of the master station cs Equal to the synchronization signal timestamp t received by the master station during this synchronization cycle ss and two synchronization periods T c sum; When the slave collects the digital input signal, the time offset t of the acquisition time relative to the start time of the current synchronization cycle, that is, the time when the previous synchronization signal was generated, is calculated. rsi , the slave uploads the digital input signal and at the same time rsi Send to the main station together; After the master station receives the digital input signal uploaded by the slave station, it timestamps the synchronization signal received during this synchronization cycle. ss With t rsi Sum and get the absolute time t when the slave collects the digital input signal asi ; When the master station sends a digital output signal to the slave station, the absolute time when the expected digital output signal is output by the slave station is t aso , the master station calculates the starting time t of the synchronization cycle when the slave station outputs the digital output signal according to the communication timing between the master station and the slave station. os and the end time t oe ; if t os ≤t aso <t oe , then the master station will t aso Subtract t os Get the delay time t of the slave output signal rso , and then the digital output signal and t rso Send to slave station at the same time; After receiving the digital output signal, the slave station delays the output of the digital output signal based on the start time of the current synchronization cycle. The delay time is equal to the received t rso .