Phase-lock-free all-optical mode matching method and system for quadrature phase shift keying signals

Abstract

The present application provides a non-phase-locked all-optical mode matching method and system for orthogonal phase shift keying signals, the method comprising: using a phase processing module to perform phase processing on the acquired orthogonal phase shift keying optical data sequence divided into two paths, respectively, to obtain a first sequence to be interfered with and a second sequence to be interfered with; using a multiplexer module to perform interference processing on the first sequence to be interfered with and the second sequence to be interfered with, to obtain an interference sequence; using a NOT gate module to perform inverse code processing on the interference sequence, to obtain a symbol matching result; setting the control level of each switch in the parallel switch module according to a preset target sequence, and using the set parallel switch module to process the symbol matching result, to obtain a matching sequence; setting a delay for the matching sequence; using an AND gate module to process the matching sequence in sequence, to obtain a pattern matching result. The embodiment of the present application completely relies on phase processing of the optical data sequence itself to achieve interference matching, which reduces cost and circuit complexity.

Description

Technical Field

[0001] The present application relates to the technical field of optical network security, and in particular to a non-phase-locked all-optical mode matching method and system for quadrature phase-shift keying signals. Background Art

[0002] In today's world, with the rapid development of information technology, data, voice, video and other services are highly popular, and network traffic has exploded. As an important part of the communication network in modern society, optical networks have the characteristics of high bandwidth, large capacity and high-speed transmission. However, with the development of technology, there are endless means of attack against optical networks, including traffic analysis, service destruction and illegal eavesdropping. Among them, service destruction is mainly achieved through physical layer destruction and in-band and out-of-band crosstalk. Illegal eavesdropping has a certain degree of concealment, which poses a huge threat to the security of optical networks. At present, since the research and design of optical networks in transmission, switching and control mainly consider transparency, openness and interconnection, its security measures mainly focus on the security protection of optical transmission channels.

[0003] Among the existing technologies, the more effective technology is the photon firewall, whose core technology is the all-optical mode matching technology. However, the all-optical mode matching technology for high-order phase-modulated optical sequences currently has the limitation of phase locking, that is, it is necessary to ensure that the phase of the target sequence is strictly synchronized with the input optical data sequence, so that the initial phase of the corresponding symbols of the two sequences is the same, the phase change rate is the same, and the phase difference is constant within each symbol time. This requires an extremely complex phase-locked circuit to solve the problem, and the complex circuit will bring high cost problems. Summary of the invention

[0004] In view of this, the purpose of the present application is to propose a non-phase-locked all-optical mode matching method and system for orthogonal phase shift keying signals.

[0005] Based on the above purpose, the present application provides a non-phase-locked all-optical mode matching method for orthogonal phase shift keying signals, which is applied to a non-phase-locked all-optical mode matching system for orthogonal phase shift keying signals. The non-phase-locked all-optical mode matching system for orthogonal phase shift keying signals includes: a phase processing module, a multiplexer module, a NOT gate module, a parallel switch module and an AND gate module. The method includes:

[0006] The phase processing module is used to perform phase processing on the acquired orthogonal phase shift keying optical data sequence divided into two paths, respectively, to obtain a first sequence to be interfered and a second sequence to be interfered; the phase of the first sequence to be interfered is a preset value; the phase of the second sequence to be interfered is opposite to the phase of the orthogonal phase shift keying optical data sequence;

[0007] Using the multiplexer module to perform interference processing on the first sequence to be interfered with and the second sequence to be interfered with to obtain an interference sequence;

[0008] Using the NOT gate module to perform inverse processing on the interference sequence to obtain a symbol matching result;

[0009] Setting the control level of each switch in the parallel switch module according to a preset target sequence, and processing the symbol matching result by using the set parallel switch module to obtain a matching sequence; setting a delay for the matching sequence;

[0010] The matching sequence is processed in sequence using the AND gate module to obtain a pattern matching result.

[0011] In a possible implementation, the phase processing module includes a cascade squarer module and a first phase shifter module; the orthogonal phase shift keying optical data sequence is divided into two paths to obtain a first optical data sequence and a second optical data sequence;

[0012] The phase processing module is used to perform phase processing on the acquired orthogonal phase shift keying optical data sequence divided into two paths to obtain a first sequence to be interfered and a second sequence to be interfered, including:

[0013] Using the cascade squarer module to return the phase of the first optical data sequence to zero, to obtain a first sequence;

[0014] Using the first phase shifter module to perform multiple phase shifting processes on the first sequence to obtain the first sequence to be interfered;

[0015] The second optical data sequence is phase processed by the phase processing module to obtain the second sequence to be interfered.

[0016] In a possible implementation, the phase processing module includes a cascaded phase negator module and a second phase shifter module;

[0017] The using the phase processing module to perform phase processing on the second optical data sequence to obtain the second sequence to be interfered includes:

[0018] The phase of the second optical data sequence is processed by the cascade phase negator module to obtain a second sequence; the second sequence has the same initial phase as the second optical data sequence;

[0019] The second sequence is phase-shifted by 180 degrees using the second phase shifter module to obtain the second sequence to be interfered; the center frequency and phase change rate of the second sequence are the same as those of the first sequence.

[0020] In a possible implementation, the cascaded squarer module includes two squarers;

[0021] The using the cascade squarer module to perform zeroing processing on the phase of the first optical data sequence to obtain a first sequence includes:

[0022] The two squarers are used to perform a second doubling process on the phase of the first optical data sequence to obtain the first sequence.

[0023] In a possible implementation, the first phase shifter module includes a plurality of optical splitters and three phase shifters;

[0024] The using the first phase shifter module to perform multiple phase shifting processes on the first sequence to obtain the first sequence to be interfered includes:

[0025] Using the optical splitter to split the first sequence into two paths, to obtain a first intermediate sequence and a second intermediate sequence;

[0026] Using the phase shifter to perform a 90-degree phase shift on the second intermediate sequence to obtain a third intermediate sequence;

[0027] Using the optical splitter to split the third intermediate sequence into two paths, thereby obtaining a fourth intermediate sequence and a fifth intermediate sequence;

[0028] Using the phase shifter to perform a 90-degree phase shift on the fifth intermediate sequence to obtain a sixth intermediate sequence;

[0029] Using the optical splitter to split the sixth intermediate sequence into two paths, thereby obtaining a seventh intermediate sequence and an eighth intermediate sequence;

[0030] Using the phase shifter to perform a 90-degree phase shift on the eighth intermediate sequence to obtain a ninth intermediate sequence;

[0031] The first intermediate sequence, the fourth intermediate sequence, the seventh intermediate sequence and the ninth intermediate sequence are used as the first sequence to be interfered.

[0032] In a possible implementation, the multiplexer module includes four multiplexers; the phase processing module includes a splitter;

[0033] The using the multiplexer module to perform interference processing on the first sequence to be interfered with and the second sequence to be interfered with to obtain an interference sequence includes:

[0034] inputting the first intermediate sequence, the fourth intermediate sequence, the seventh intermediate sequence and the ninth intermediate sequence into the four multiplexers respectively;

[0035] Using the optical splitter to divide the second sequence to be interfered into four paths and inputting the four paths into the four multiplexers respectively;

[0036] The multiplexer is used to perform interference processing on the existing sequences in the multiplexer to obtain four groups of interference sequences.

[0037] In a possible implementation, setting the control level of each switch in the parallel switch module according to a preset target sequence, and using the set parallel switch module to process the symbol matching result to obtain a matching sequence includes:

[0038] According to the initial phase order of the symbols in the target sequence, the control level of each switch in the parallel switch module is set in sequence;

[0039] The symbol matching result is input into the set parallel switch module, matched with the control level of each switch, and the matching sequence is obtained.

[0040] In a possible implementation manner, setting a delay for the matching sequence includes:

[0041] Starting from the matching sequence corresponding to the last symbol of the target sequence, the delay of each matching sequence is set to an arithmetic progression starting from zero in reverse order of the symbols in the target sequence; the tolerance of the arithmetic progression is a positive value of the unit symbol time.

[0042] In a possible implementation, the using the AND gate module to sequentially process the matching sequence to obtain a pattern matching result includes:

[0043] According to the positive order of the matching sequences, every two matching sequences are taken as a group and input into the AND gate module to obtain a first result;

[0044] In response to the number of the first results being greater than one, every two of the first results are taken as a group and input into the AND gate module according to the positive order of the first results, until the number of the first results is one, thereby obtaining a second result;

[0045] In response to the presence of a first number of pulse signals in the second result, the result of the pattern matching is that a first number of the target sequences exist in the orthogonal phase shift keying optical data sequence;

[0046] In response to the pulse signal not existing in the second result, the result of the pattern matching is that the target sequence does not exist in the quadrature phase shift keying optical data sequence.

[0047] Based on the same inventive concept, the embodiment of the present application also provides a non-phase-locked all-optical mode matching system for orthogonal phase shift keying signals, including: a phase processing module, a multiplexer module, a NOT gate module, a parallel switch module and an AND gate module;

[0048] The phase processing module is used to perform phase processing on the acquired orthogonal phase shift keying optical data sequence divided into two paths, respectively, to obtain a first sequence to be interfered and a second sequence to be interfered; the phase of the first sequence to be interfered is a preset value; the phase of the second sequence to be interfered is opposite to the phase of the orthogonal phase shift keying optical data sequence;

[0049] The multiplexer module is used to perform interference processing on the first sequence to be interfered and the second sequence to be interfered to obtain an interference sequence;

[0050] The NOT gate module is used to perform inverse code processing on the interference sequence to obtain a symbol matching result;

[0051] The parallel switch module is used to set the control level of each switch in the parallel switch module according to a preset target sequence, and process the symbol matching result to obtain a matching sequence; and set a delay for the matching sequence;

[0052] The AND gate module is used to process the matching sequence in sequence to obtain a pattern matching result.

[0053] As can be seen from the above, the present application provides a non-phase-locked all-optical mode matching method and system for orthogonal phase shift keying signals. The non-phase-locked all-optical mode matching system for orthogonal phase shift keying signals includes: a phase processing module, a multiplexer module, a NOT gate module, a parallel switch module and an AND gate module. The method includes: using the phase processing module to perform phase processing on the acquired orthogonal phase shift keying optical data sequence divided into two paths, respectively, to obtain a first sequence to be interfered with and a second sequence to be interfered with; the phase of the first sequence to be interfered with is a preset value; the phase of the second sequence to be interfered with is opposite to the phase of the orthogonal phase shift keying optical data sequence; using the multiplexer module to perform interference processing on the first sequence to be interfered with and the second sequence to be interfered with to obtain an interference sequence; using the NOT gate module to perform inverse code processing on the interference sequence to obtain a symbol matching result; setting the control level of each switch in the parallel switch module according to a preset target sequence, and using the set parallel switch module to process the symbol matching result to obtain a matching sequence; setting a delay for the matching sequence; using the AND gate module to process the matching sequence in sequence to obtain a pattern matching result. The embodiment of the present application realizes the phase-locked all-optical mode matching for the Quadrature Phase Shift Keying (QPSK) modulation format, without the need to introduce a local target sequence and a phase-locked circuit, and solves the limitation of phase locking in the all-optical mode matching of the high-order phase modulation format at a low cost. The all-optical signal processing modules in the system, including the squarer, the phase negator and the all-optical logic gate, are all implemented based on highly nonlinear fiber (HNLF), and the nonlinear effect response time is short, which can realize the all-optical mode matching of signals with higher transmission rates. In addition, compared with the binary modulation format, the QPSK modulation format doubles the number of bits contained in each bit symbol of the signal, improves the matching efficiency of the all-optical mode matching system, and reduces the matching time under the same amount of information. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] In order to more clearly illustrate the technical solutions in the present application or related technologies, the drawings required for use in the embodiments or related technical descriptions are briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0055] Figure 1 A schematic flow chart of a non-phase-locked all-optical mode matching method for a quadrature phase shift keying signal according to an embodiment of the present application;

[0056] Figure 2 This is a schematic diagram of the structure of a non-phase-locked all-optical mode matching system for quadrature phase shift keying signals according to an embodiment of the present application;

[0057] Figure 3 A schematic diagram of an input optical data sequence and a target sequence according to an embodiment of the present application;

[0058] Figure 4 This is a schematic diagram of a process of implementing a squarer and a phase negator using FWM according to an embodiment of the present application;

[0059] Figure 5 This is a schematic diagram of the initial phase change of the optical data sequence of the embodiment of the present application after passing through the cascade squarer;

[0060] Figure 6 It is a waveform diagram of the AND gate processing process of the embodiment of the present application. DETAILED DESCRIPTION

[0061] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0062] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should be the usual meanings understood by people with ordinary skills in the field to which the present application belongs. The "first", "second" and similar words used in the embodiments of the present application do not represent any order, quantity or importance, but are only used to distinguish different components. "Including" or "comprising" and similar words mean that the elements or objects appearing in front of the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0063] As described in the background technology section, in today's world, with the rapid development of information technology, data, voice, video and other services are highly popular, and network traffic has exploded. As an important part of the communication network in modern society, the optical network has the characteristics of high bandwidth, large capacity and high-speed transmission. However, with the development of technology, the means of attack against the optical network are endless, including traffic analysis, service destruction and illegal eavesdropping. Among them, service destruction is mainly achieved through physical layer destruction and in-band and out-of-band crosstalk. Illegal eavesdropping has a certain degree of concealment, which makes the security of the optical network under great threat. At present, since the research and design of optical networks in transmission, switching and management and control mainly consider transparency, openness and interconnection, its security measures mainly focus on the security protection of optical transmission channels.

[0064] Among the existing technologies, the more effective technology is the photon firewall, whose core technology is the all-optical mode matching technology. However, the all-optical mode matching technology for high-order phase-modulated optical sequences currently has the limitation of phase locking, that is, it is necessary to ensure that the phase of the target sequence is strictly synchronized with the input optical data sequence, so that the initial phase of the corresponding symbols of the two sequences is the same, the phase change rate is the same, and the phase difference is constant within each symbol time. This requires an extremely complex phase-locked circuit to solve the problem, and the complex circuit will bring high cost problems.

[0065] Based on the above considerations, an embodiment of the present application proposes a phase-locked all-optical pattern matching method for orthogonal phase shift keying signals, wherein a phase processing module is used to perform phase processing on the acquired orthogonal phase shift keying optical data sequence divided into two paths, respectively, to obtain a first sequence to be interfered and a second sequence to be interfered; the phase of the first sequence to be interfered is a preset value; the phase of the second sequence to be interfered is opposite to the phase of the orthogonal phase shift keying optical data sequence; the multiplexer module is used to perform interference processing on the first sequence to be interfered and the second sequence to be interfered to obtain an interference sequence; the NOT gate module is used to perform inverse code processing on the interference sequence to obtain a symbol matching result; the control level of each switch in the parallel switch module is set according to a preset target sequence, and the symbol matching result is processed by the set parallel switch module to obtain a matching sequence; a delay is set for the matching sequence; and the matching sequence is processed in sequence by the AND gate module to obtain a pattern matching result. The embodiment of the present application realizes phase-locked all-optical mode matching for the QPSK modulation format, without the need to introduce local target sequences and phase-locked circuits, and solves the phase-locking limitations in all-optical mode matching of high-order phase modulation formats at a low cost. The all-optical signal processing modules in the system, including squarers, phase negators, and all-optical logic gates, are all implemented based on HNLF, and their nonlinear effect response time is short, which can realize all-optical mode matching of signals with higher transmission rates. In addition, compared with the binary modulation format, the QPSK modulation format doubles the number of bits contained in each symbol of the signal, improves the matching efficiency of the all-optical mode matching system, and reduces the matching time under the same amount of information.

[0066] The technical solutions of the embodiments of the present application are described in detail below through specific examples.

[0067] refer to Figure 1 The non-phase-locked all-optical mode matching method for orthogonal phase shift keying signals in the embodiment of the present application comprises the following steps:

[0068] Step S101, using a phase processing module to perform phase processing on the acquired orthogonal phase shift keying optical data sequence divided into two paths, respectively, to obtain a first sequence to be interfered and a second sequence to be interfered; the phase of the first sequence to be interfered is a preset value; the phase of the second sequence to be interfered is opposite to the phase of the orthogonal phase shift keying optical data sequence;

[0069] Step S102, using the multiplexer module to perform interference processing on the first sequence to be interfered with and the second sequence to be interfered with to obtain an interference sequence;

[0070] Step S103, using the NOT gate module to perform inverse processing on the interference sequence to obtain a symbol matching result;

[0071] Step S104, setting the control level of each switch in the parallel switch module according to a preset target sequence, and using the set parallel switch module to process the symbol matching result to obtain a matching sequence; setting a delay for the matching sequence;

[0072] Step S105 , using the AND gate module to process the matching sequence in sequence to obtain a pattern matching result.

[0073] refer to Figure 2 , which is a schematic diagram of the structure of a non-phase-locked all-optical mode matching system for orthogonal phase-shift keying signals according to an embodiment of the present application.

[0074] The following, combined Figure 1 and Figure 2 The embodiments of the present application are described in detail.

[0075] For step S101, first, the phase processing module is used to perform phase processing on the acquired orthogonal phase shift keying optical data sequence divided into two paths, so as to obtain a first sequence to be interfered and a second sequence to be interfered; the phase of the first sequence to be interfered is a preset value; the phase of the second sequence to be interfered is opposite to the phase of the orthogonal phase shift keying optical data sequence.

[0076] In some embodiments, the phase processing module includes a cascade squarer module and a first phase shifter module; the orthogonal phase shift keying optical data sequence is divided into two paths to obtain a first optical data sequence and a second optical data sequence; the phase processing module is used to perform phase processing on the acquired orthogonal phase shift keying optical data sequence divided into two paths, respectively, to obtain a first sequence to be interfered with and a second sequence to be interfered with, including: using the cascade squarer module to return the phase of the first optical data sequence to zero to obtain a first sequence; using the first phase shifter module to perform multiple phase shift processing on the first sequence to obtain the first sequence to be interfered with; using the phase processing module to perform phase processing on the second optical data sequence to obtain the second sequence to be interfered with.

[0077] In some embodiments, the cascaded squarer module includes two squarers; using the cascaded squarer module to zero the phase of the first optical data sequence to obtain the first sequence includes: using the two squarers to double the phase of the first optical data sequence twice to obtain the first sequence.

[0078] In some embodiments, the phase processing module includes a cascaded phase negator module and a second phase shifter module; using the phase processing module to perform phase processing on the second optical data sequence to obtain the second sequence to be interfered includes: using the cascaded phase negator module to process the phase of the second optical data sequence to obtain a second sequence; the second sequence is the same as the initial phase of the second optical data sequence; using the second phase shifter module to shift the second sequence by 180 degrees to obtain the second sequence to be interfered; the second sequence is the same as the first sequence in center frequency and phase change rate.

[0079] In this embodiment, the input optical data sequence is in QPSK modulation format, with a total of M QPSK symbols, and the duration of each symbol is T. Assuming that the four optional initial phases are The optical data sequence is divided into two identical paths through a 1*2 optical splitter. One path enters the cascade squarer module of the upper arm, which includes two squarers. The function of the squarer is to double the phase of the signal. The symbol with an initial phase of {0} still has an initial phase of {0} after passing through the squarer. After the sign of the squarer, the initial phase changes to {π}, and the initial phase of the sign of the squarer is {0}. After passing through the squarer, the initial phase of the symbol changes to {π}. After passing through a squarer, the above optical data sequence can obtain a sequence with only two symbols {0, π}. After passing through the squarer again, the symbol with an initial phase of {0} is still {0}, and the symbol with an initial phase of {π} changes to {0}. That is, after passing through two squarers, a sequence with all symbols having an initial phase of {0} is obtained.

[0080] The other path enters the cascade phase negator module of the lower arm, which includes two phase negators. The structure of the phase negator is exactly the same as that of the squarer, except that the pump light and the center wavelength of the filter are different. Taking the aforementioned optical sequence as an example, the symbol with the initial phase of {0} still has the initial phase of {0} after passing through the phase negator. After the phase negator, the initial phase changes to The initial phase of the sign is {π}, and after passing through the phase negator, the initial phase is still {π}. After the phase negator, the initial phase changes to After passing through the phase negator again, the initial phase of the symbol with the initial phase of {0} is still {0}. The initial sign of The initial phase of the symbol is {π}, and the initial phase is The initial sign of That is, the initial phase of each symbol of the sequence output after the cascade phase negator is consistent with the input optical data sequence.

[0081] Since the structure of the phase negator is consistent with that of the squarer, and the pump wavelengths are set one-to-one, the sequence output by it has the same center frequency as the sequence output by the upper arm cascade squarer and has the same phase change rate. The output of the cascade phase negator is amplified to be equal to the output amplitude of the cascade squarer, that is, the power is equal.

[0082] Afterwards, the output of the cascade squarer module is phase-shifted to obtain a sequence to be interfered. In this embodiment, the first phase shifter module is used for processing.

[0083] In some embodiments, the first phase shifter module includes multiple optical splitters and three phase shifters; the use of the first phase shifter module to perform multiple phase shift processing on the first sequence to obtain the first sequence to be interfered includes: using the optical splitter to divide the first sequence into two paths to obtain a first intermediate sequence and a second intermediate sequence; using the phase shifter to perform a 90-degree phase shift processing on the second intermediate sequence to obtain a third intermediate sequence; using the optical splitter to divide the third intermediate sequence into two paths to obtain a fourth intermediate sequence and a fifth intermediate sequence; using the phase shifter to perform a 90-degree phase shift processing on the fifth intermediate sequence to obtain a sixth intermediate sequence; using the optical splitter to divide the sixth intermediate sequence into two paths to obtain a seventh intermediate sequence and an eighth intermediate sequence; using the phase shifter to perform a 90-degree phase shift processing on the eighth intermediate sequence to obtain a ninth intermediate sequence; and using the first intermediate sequence, the fourth intermediate sequence, the seventh intermediate sequence, and the ninth intermediate sequence as the first sequence to be interfered.

[0084] In this embodiment, the output of the cascade squarer module, that is, the first sequence with an initial phase of {0, 0...0}, is divided into two identical paths through a 1*2 optical splitter. One path is the first intermediate sequence, which is used as the first sequence to be interfered. The other path is the second intermediate sequence, which is passed through a 90° phase shifter to obtain an initial phase of The third intermediate sequence is passed through the 1*2 optical splitter to obtain two identical paths, one of which is the fourth intermediate sequence, which is used as the first sequence to be interfered, and the other is the fifth intermediate sequence. After passing through a 90° phase shifter, a sixth intermediate sequence with an initial phase of {π, π…π} is obtained. The sequence is passed through the 1*2 optical splitter again to obtain two identical paths, one of which is the seventh intermediate sequence, which is used as the first sequence to be interfered, and the other is the eighth intermediate sequence. After passing through a 90° phase shifter, an initial phase of The ninth intermediate sequence is used as the first sequence to be interfered. The first intermediate sequence with an initial phase of {0, 0…0} is attenuated by 3 dB, and the initial phase is {π, π…π}. The fourth intermediate sequence and the seventh intermediate sequence are amplified by 3dB, and finally the initial phases are {0, 0...0} respectively. {π, π…π} and The amplitudes of the four interference sequences are consistent and the power is the same, which is represented by P0.

[0085] Furthermore, the output of the cascaded phase negator module is phase shifted to obtain the sequence to be interfered. The amplified output of the cascaded phase negator module, i.e., the second sequence whose initial phase is consistent with each symbol of the optical data sequence, is passed through the second phase shifter module, which is a cascaded 90° phase shifter, which can make each symbol undergo a 180° phase shift, i.e., the initial phase of the symbol with an initial phase of {0} is changed to {π}, and the initial phase is The initial phase change of the sign is The symbol with initial phase {π} changes to {0}, and the initial phase is The initial phase change of the sign is The phase-shifted sequence is input into a 1*4 optical splitter and divided into four identical paths as the second sequence to be interfered. The amplitude of the sequence is consistent with the four-path first sequence to be interfered obtained in the second step above, that is, the power is the same, also P0.

[0086] With respect to step S102, the multiplexer module is used to perform interference processing on the first sequence to be interfered with and the second sequence to be interfered with to obtain an interference sequence.

[0087] In some embodiments, the multiplexer module includes four multiplexers; the phase processing module includes a spectrometer; using the multiplexer module to perform interference processing on the first sequence to be interfered and the second sequence to be interfered to obtain an interference sequence includes: inputting the first intermediate sequence, the fourth intermediate sequence, the seventh intermediate sequence and the ninth intermediate sequence into the four multiplexers respectively; using the spectrometer to divide the second sequence to be interfered into four paths and inputting them into the four multiplexers respectively; using the multiplexer to perform interference processing on the existing sequence in the multiplexer to obtain four groups of the interference sequences.

[0088] In this embodiment, the sequence to be interfered is input into the multiplexer for interference. The first sequence to be interfered and the second sequence to be interfered are input into four multiplexers in pairs. The input of the first multiplexer is the first sequence to be interfered and the second sequence to be interfered with with the initial phase {0, 0…0}. The sign bit of the second sequence to be interfered with with the initial phase {0} generates coherent phase constructive interaction, and the output power is 4 times the original, that is, 4P0; and The first phase is {π}, the first phase is {π}, the second ... The first sequence to be interfered and the second sequence to be interfered, the initial phase of the second sequence to be interfered is The sign bit of the initial phase is {0} and {π}, and the coherent phase occurs, and the output power is 4P0; the sign bit of the initial phase is {0} and {π}, and the interference occurs, and the output power is 2P0; the initial phase is The input of the third multiplexer is the first sequence to be interfered with and the second sequence to be interfered with, the initial phase is {π, π…π}. The sign bit of the first sequence to be interfered with and the initial phase is {π}, the coherent phase is constructed, and the output power is 4P0; the initial phase is and The sign bit of the initial phase is {0}, interference occurs, and the output power is 2P0; the sign bit of the initial phase is {0}, coherent cancellation occurs, and the output power is 0. The input of the fourth multiplexer is The first sequence to be interfered and the second sequence to be interfered, the initial phase of the second sequence to be interfered is The sign bit of the initial phase is {0} and {π}, and the coherent phase occurs, and the output power is 4P0; the sign bit of the initial phase is {0} and {π}, and the interference occurs, and the output power is 2P0; the initial phase is The sign bit of , coherent cancellation occurs, and the output power is 0. In the interference matching sequence output by the four multiplexers, the sign bit where coherent cancellation occurs is the sign matching position, which corresponds to {0}, {π} and The positions of the symbols of the four initial phases in the optical data sequence give four sets of interference sequences.

[0089] With respect to step S103, the interference sequence is inverted by using the NOT gate module to obtain a sign matching result.

[0090] In this embodiment, the interference sequence output by the multiplexer is amplified and then input into the NOT gate for processing. The four groups of interference sequences output by the four multiplexers in the above steps are amplified by fixed power amplifiers and then input into four NOT gates. When the symbol power in the interference sequence is 0, the signal power output by the NOT gate is the largest. When the symbol power is 4P0, the output power of the NOT gate is 0. When the symbol power is 2P0, the output power of the NOT gate is extremely small and close to 0. In the output of the first NOT gate, the symbol position with the initial phase {0} in the optical data sequence outputs a pulse with a larger power, the symbol position with the initial phase {π} outputs 0, and the symbol position with the initial phase {π} outputs 0. and The symbol position output is close to 0; in the output of the second NOT gate, the initial phase of the optical data sequence is The symbol position of the pulse with larger output power has an initial phase of The symbol position output is 0, and the symbol position outputs are close to 0 when the initial phases are {0} and {π}; in the output of the third NOT gate, the symbol position with the initial phase {π} in the optical data sequence outputs a pulse with a larger power, the symbol position with the initial phase {0} outputs 0, and the symbol position with the initial phase is and The symbol position output is close to 0; in the output of the fourth NOT gate, the initial phase of the optical data sequence is The symbol position of the pulse with larger output power has an initial phase of The symbol position output is 0, and the symbol position output of the initial phases {0} and {π} is close to 0.

[0091] For step S104, the control level of each switch in the parallel switch module is set according to a preset target sequence, and the symbol matching result is processed by using the set parallel switch module to obtain a matching sequence; and a delay is set for the matching sequence.

[0092] In some embodiments, the control level of each switch in the parallel switch module is set according to a preset target sequence, and the symbol matching result is processed using the set parallel switch module to obtain a matching sequence, including: setting the control level of each switch in the parallel switch module in sequence according to the initial phase order of the symbols in the target sequence; inputting the symbol matching result into the set parallel switch module to match it with the control level of each switch to obtain the matching sequence.

[0093] In some embodiments, setting the delay for the matching sequence includes: starting from the matching sequence corresponding to the last symbol passing through the target sequence, and setting the delay of each matching sequence in turn to an arithmetic progression starting from zero in reverse order of the symbols in the target sequence; the tolerance of the arithmetic progression is a positive value of the unit symbol time.

[0094] In this embodiment, the output of the NOT gate is used as the symbol matching result of the all-optical mode matching module and connected to the input end of the 4*1 switch. In the above steps, the output of the NOT gate is used as the symbol matching result of the all-optical mode matching module, and the outputs of the four NOT gates correspond to {0} in sequence. {π}, The symbol matching results of the four initial phase symbols in the optical data sequence. If the length of the target sequence is N symbols, N 4*1 switches are used in the parallel module. Using a 1*N optical splitter, each matching result is divided into N identical paths, and the four inputs of the 4*1 switch are connected to {0} in sequence. {π}, The symbol matching results corresponding to the four types of initialization.

[0095] In this embodiment, the control levels of N 4*1 switches are set according to the target sequence. If the control level of the 4*1 switch is a two-bit binary number {00, 01, 10, 11}, it corresponds to four inputs, namely {0}, {π}, Symbol matching results of four initial phases. If the control level of the switch is {00}, the output initial phase is a matching sequence of {0}; if the control level of the switch is {01}, the output initial phase is If the switch control level is {10}, the output initial phase is a matching sequence of {π}; if the switch control level is {11}, the output initial phase is According to the order of the symbols in the target sequence, the control levels of N 4*1 switches are set in sequence to obtain N matching sequences.

[0096] Furthermore, the N-way matching sequence is input into the AND gate array after delay to obtain the final matching result. The N-way matching sequence obtained in the seventh step is respectively input into the AND gate array after {(N-1)*T, (N-2)*T, ... 0} time delay according to the order of the symbols in the target sequence.

[0097] With respect to step S105 , the matching sequence is processed in sequence using the AND gate module to obtain a pattern matching result.

[0098] In some embodiments, the use of the AND gate module to sequentially process the matching sequence to obtain a pattern matching result includes: according to the positive sequence of the matching sequence, taking every two matching sequences as a group and inputting them into the AND gate module to obtain a first result; in response to the number of the first results being greater than one, taking every two first results as a group and inputting them into the AND gate module according to the positive sequence of the first results; until the number of the first results is one, obtaining a second result; in response to the presence of a first number of pulse signals in the second result, the result of the pattern matching is that the first number of target sequences exist in the orthogonal phase shift keying optical data sequence; in response to the absence of the pulse signal in the second result, the result of the pattern matching is that the target sequence does not exist in the orthogonal phase shift keying optical data sequence.

[0099] In this embodiment, the two-input AND gate used is implemented based on the four-wave mixing (FWM) effect of HNLF, so the two input wavelengths need to be inconsistent. The embodiment of the present application uses a wavelength converter to solve this problem. If the target sequence length N is an even number, the first layer has a total of N / 2 AND gates, the second layer has N / 4 AND gates, and so on. The output of the last layer of AND gates is the matching result of the optical data sequence of M-bit symbols and the target sequence of N-bit symbols. If the target sequence length N is an odd number, the first layer has a total of (N+1) / 2 AND gates, where the input of the last AND gate is the symbol matching sequence of the last symbol and the full "1" pulse sequence, the second layer has (N+1) / 4 AND gates, and so on. The output of the AND gate of the last layer is the matching result of the optical data sequence of M-bit symbols and the target sequence of N-bit symbols. If the optical data sequence contains the target sequence, there will be a pulse signal in the matching result. The position of the pulse signal is the position of the last symbol of the target sequence in the optical data sequence. The number of pulse signals is the number of target sequences included in the optical data sequence. If there is no pulse, it means that the optical data sequence does not contain the target sequence.

[0100] In another possible embodiment, Figure 3 The input optical data sequence and the target sequence are shown; the four optional initial phases of the QPSK signal used in this patent are set to Here it is assumed that the input light data sequence Its length M = 16, and its amplitude is A m , power is P m Target sequence Its length N = 4, the target sequence does not need to be generated locally, and the control level of the 4*1 switch in the parallel module can be set according to the symbol order of the target sequence. Let {0}, {π} and The four symbols correspond to four two-bit binary control levels {00}, {01}, {10} and {11} respectively. The input of the 4*1 switch is the matching result of the four symbols output by the all-optical mode matching module. By setting the control level of the input 4*1 switch, the corresponding symbol matching sequence of the control switch output is controlled. According to the target sequence B, the control levels of the four 4*1 switches are set to {01}, {10}, {11} and {00} in sequence.

[0101] Figure 4 The schematic diagram of the process of using FWM to realize the squarer and phase negator is shown; this circuit realizes the squarer and phase negator based on the FWM effect of HNLF. The FWM effect is a nonlinear effect in optical fiber. Two or three light waves with a certain frequency difference interact with each other to generate light of a new frequency. The newly generated idler light will carry the information of the original optical signal.

[0102] Due to the FWM effect of the optical fiber, if the frequencies of the signal light and the pump light are f1 and f2 respectively, idler light idler1 and idler2 will be generated at 2f1-f2 and 2f2-f1 respectively. The initial phase of the idler light idler1 close to the signal light is the initial phase of the signal light. twice, that is At the same time, the phase change rate changes from ω0 to ω0+ω1; the initial phase of the idler light idler2 close to the pump light is the initial phase of the signal light Take the negative, that is At the same time, the phase change rate changes from ω0 to ω0+ω2. The magnitudes of ω1 and ω2 depend on the magnitude of |f1-f2| and the position of the idler light. Based on the above principle explanation, by setting the center frequency of the filter, the output of the squarer is the idler light idler1, and the output of the phase negator is the idler light idler2.

[0103] Figure 5 The schematic diagram shows the initial phase change of the optical data sequence after the cascade squarer; the optical data sequence originally has four symbols After the squarer, the initial phases of the symbols with initial phases {0} and {π} are doubled to {0}, while the initial phases and The initial phases of the symbols are doubled to {π}. After the optical data sequence passes through the first-stage squarer, the output sequence is {π, 0, π, π, 0, π, 0, 0, π, π, 0, π, 0, π, 0}. The sequence is input into the squarer again, and the symbols with initial phases of {0} and {π} are doubled to {0}. The initial phases of the symbols in the sequence output by the second-stage squarer are {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}.

[0104] The signal output by the cascade squarer is then divided into two identical paths through a 1*2 optical splitter. One path is used as the interference sequence after 3dB attenuation, and the initial phase of each symbol is {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}. The other path passes through a 90° phase shifter and then a 1*2 optical splitter and is divided into two identical paths. One path is used as the interference sequence, and the initial phase of each symbol is The other path passes through a 90° phase shifter and then a 1*2 splitter and is divided into two identical paths. One path is amplified by 3dB as the sequence to be interfered with. The initial phase of each symbol is {π, π, π, π, π, π, π, π, π, π, π, π, π, π}. The other path passes through a 90° phase shifter and then amplified by 3dB as the sequence to be interfered with. The initial phase of each symbol is Finally, the four initial phases are {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}. {π,π,π,π,π,π,π,π,π,π,π,π,π,π,π,π}, The power of the interference sequence with the same amplitude is P0.

[0105] After the signal passes through the cascade phase negator, the initial phase of each symbol is the same as the optical data sequence, which is still The frequency and phase change rate of this sequence are the same as the sequence output by the cascade squarer. The sequence is passed through the cascaded 90° phase shifter to obtain a second interference sequence that is 180° different from the initial phase of each symbol of the data optical sequence. The initial phase of each symbol of this sequence is Then it is divided into four identical paths by a 1*4 splitter as the interference sequence, with a power of P0.

[0106] Through 4 multiplexers, the upper and lower arms generate four interference sequences, which interfere with each other in pairs, and the interference results corresponding to the four symbols can be obtained. From top to bottom, the input of the first multiplexer is the initial phase of {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}. For two sequences with the same amplitude, the signal power of each symbol position of the sequence obtained after interference is {2P0, 4P0, 2P0, 2P0, 0, 2P0, 4P0, 4P0, 2P0, 2P0, 4P0, 2P0, 0, 2P0, 4P0}. The position with power 0 is the position of the symbol with initial phase {0} in the data optical sequence, while the mismatched position has a pulse with power 2P0 or 4P0. It is amplified by a fixed power amplifier and input into the NOT gate to eliminate the influence caused by the difference in pulse power at the mismatched position. In this patent, for the input and output of the optical logic gate, "P" represents high power and "0" represents low power of 0 or close to 0. The power of each symbol in the sequence output by the NOT gate is {0, 0, 0, 0, P, 0, 0, 0, 0, 0, 0, 0, P, 0, 0}.

[0107] The input of the second multiplexer is the initial phase

[0108] For two sequences with the same amplitude, the signal power at each symbol position of the sequence obtained after interference is {0, 2P0, 4P0, 0, 2P0, 4P0, 2P0, 0, 4P0, 0, 2P0, 4P0, 2P0, 0, 2P0}. The position where the power is 0 is the initial phase. The position of the symbol in the data optical sequence is 2P0 or 4P0, while the position that does not match the symbol has a pulse with a power of 2P0 or 4P0. After being amplified by a fixed power amplifier, it is input into the NOT gate to eliminate the influence caused by the difference in pulse power at the mismatched position. The power of each symbol in the sequence output by the NOT gate is {P, 0, 0, P, 0, 0, 0, P, 0, P, 0, 0, 0, P, 0}.

[0109] The inputs of the third multiplexer are the initial phases respectively {π, π, π, π, π, π, π, π, π, π, π, π, π, π, π, π}, For two sequences with the same amplitude, the signal power of each symbol position of the sequence obtained after interference is {2P0, 0, 2P0, 2P0, 4P0, 2P0, 0, 0, 2P0, 2P0, 2P0, 0, 2P0, 4P0, 2P0, 0}. The position with power 0 is the position of the symbol with initial phase {π} in the data optical sequence, while the mismatched position has a pulse with power 2P0 or 4P0. It is amplified by a fixed power amplifier and input into the NOT gate to eliminate the influence caused by the difference in pulse power at the mismatched position. The power of each symbol in the sequence output by the NOT gate is {0, P, 0, 0, 0, 0, P, P, 0, 0, 0, P, 0, 0, 0, P}.

[0110] The input of the fourth multiplexer is the initial phase

[0111] For two sequences with the same amplitude, the signal power at each symbol position of the sequence obtained after interference is {4P0, 2P0, 0, 4P0, 2P0, 0, 2P0, 2P0, 4P0, 0, 4P0, 2P0, 0, 2P0, 4P0, 2P0}. The position where the power is 0 is the initial phase. The position of the symbol in the data optical sequence is 2P0 or 4P0, while the position that does not match the symbol has a pulse with a power of 2P0 or 4P0. After being amplified by a fixed power amplifier, it is input into the NOT gate to eliminate the influence caused by the difference in pulse power at the mismatched position. The power of each symbol in the sequence output by the NOT gate is {0, 0, P, 0, 0, P, 0, 0, 0, P, 0, 0, 0}.

[0112] The outputs of the four NOT gates are the symbol matching results output by the all-optical mode matching module, from top to bottom, with the initial phase being {0} {π} The matching results of the four symbols. According to the target sequence The control levels of the four 4*1 switches are set to {01}, {10}, {11}, {00}, so that the outputs of the four switches from top to bottom are {π}, {0}The matching results of the four symbols in the data optical sequence. Delay the four-way symbol matching sequence by 3T, 2T, 1T, 0 in turn, and get four power sequences of {0,0,0,P,0,0,P,0,0,0,P,0,P,0,0}, {0,0,0,P,0,0,0,0,P,P,0,0,0,P,0,0}, {0,0,0,P,0,0,P,0,0,0,P,0,0,P,0,0,0} and {0,0,0,0,P,0,0,0,0,0,0,0,0,0,0,P,0,0}.

[0113] The input of the first AND gate of the first layer is two power sequences {0,0,0,P,0,0,P,0,0,0,0,P,0,P,0,0} and {0,0,0,P,0,0,0,0,P,P,0,0,0,P,0,0} respectively. The second sequence has a different wavelength from the first sequence after wavelength conversion. The output sequence power of the AND gate is {0,0,0,P,0,0,0,0,0,0,0,0,0,P,0,0}, and the output is the sequence The matching result in the optical data sequence, in this patent, × represents any one of the four optional initial phases of the QPSK signal.

[0114] The inputs of the second AND gate of the first layer are two sequences with powers {0,0,0,P,0,0,P,0,0,0,P,0,0,P,0,0} and {0,0,0,0,P,0,0,0,0,0,0,0,0,0,P,0,0} respectively. The wavelength of the second sequence is different from that of the first sequence after wavelength conversion. The power of the sequence output by the AND gate is {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,P,0,0}, and the output is the sequence Matching results in the optical data sequence.

[0115] The input of the second-layer AND gate is the output of the two AND gates in the first layer, that is, two sequences with powers of {0,0,0,P,0,0,0,0,0,0,0,0,0,0,P,0,0} and {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,P,0,0} respectively. Their wavelengths are different, which meets the input requirements of the AND gate. The power of the sequence output by the second-layer AND gate is {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,P,0,0}, which is the target sequence. The matching result in the data optical sequence is that there is one target sequence in the optical data sequence, and the last symbol of the target sequence corresponds to the 14th symbol of the optical data sequence.

[0116] Figure 6 The waveform diagram of the AND gate processing process of the embodiment of the present application is shown; when the optical data sequence is input Target sequence The matching results of the four symbols of the all-optical mode matching module are output as the target sequence after passing through the set 4 4*1 switches. After the delay, four delayed signals are obtained, which are input into two layers of AND gates for parallel integration, and the matching results are output by the last layer of AND gates. The circuit successfully finds the number and position of the target sequence in the input optical data sequence.

[0117] It can be seen from the above embodiments that the phase-locked all-optical pattern matching method for orthogonal phase shift keying signals described in the embodiments of the present application uses a phase processing module to perform phase processing on the acquired orthogonal phase shift keying optical data sequence divided into two paths, respectively, to obtain a first sequence to be interfered and a second sequence to be interfered; the phase of the first sequence to be interfered is a preset value; the phase of the second sequence to be interfered is opposite to the phase of the orthogonal phase shift keying optical data sequence; the first sequence to be interfered and the second sequence to be interfered are interfered by the multiplexer module to obtain an interference sequence; the interference sequence is inverted by the NOT gate module to obtain a symbol matching result; the control level of each switch in the parallel switch module is set according to a preset target sequence, and the symbol matching result is processed by the set parallel switch module to obtain a matching sequence; a delay is set for the matching sequence; and the matching sequence is processed in sequence by the AND gate module to obtain a pattern matching result. The embodiment of the present application realizes the phase-locked all-optical mode matching for the Quadrature Phase Shift Keying (QPSK) modulation format, without the need to introduce a local target sequence and a phase-locked circuit, and solves the limitation of phase locking in the all-optical mode matching of the high-order phase modulation format at a low cost. The all-optical signal processing modules in the system, including the squarer, the phase negator and the all-optical logic gate, are all implemented based on highly nonlinear fiber (HNLF), and the nonlinear effect response time is short, which can realize the all-optical mode matching of signals with higher transmission rates. In addition, compared with the binary modulation format, the QPSK modulation format doubles the number of bits contained in each bit symbol of the signal, improves the matching efficiency of the all-optical mode matching system, and reduces the matching time under the same amount of information.

[0118] It should be noted that the method of the embodiment of the present application can be performed by a single device, such as a computer or server. The method of this embodiment can also be applied to a distributed scenario and completed by multiple devices cooperating with each other. In the case of such a distributed scenario, one of the multiple devices can only perform one or more steps in the method of the embodiment of the present application, and the multiple devices will interact with each other to complete the described method.

[0119] It should be noted that the above describes some embodiments of the present application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the above embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0120] Based on the same inventive concept, corresponding to any of the above-mentioned embodiments and methods, the present application also provides a non-phase-locked all-optical mode matching system for orthogonal phase shift keying signals.

[0121] refer to Figure 2 The non-phase-locked all-optical mode matching system for quadrature phase shift keying signals comprises:

[0122] Phase processing module, multiplexer module, NOT gate module, parallel switch module and AND gate module;

[0123] The phase processing module is used to perform phase processing on the acquired orthogonal phase shift keying optical data sequence divided into two paths, respectively, to obtain a first sequence to be interfered and a second sequence to be interfered; the phase of the first sequence to be interfered is a preset value; the phase of the second sequence to be interfered is opposite to the phase of the orthogonal phase shift keying optical data sequence;

[0124] The multiplexer module is used to perform interference processing on the first sequence to be interfered with and the second sequence to be interfered with to obtain an interference sequence;

[0125] The NOT gate module is used to perform inverse code processing on the interference sequence to obtain a symbol matching result;

[0126] The parallel switch module is used to set the control level of each switch in the parallel switch module according to a preset target sequence, and process the symbol matching result to obtain a matching sequence; and set a delay for the matching sequence;

[0127] The AND gate module is used to process the matching sequence in sequence to obtain a pattern matching result.

[0128] Specifically, the system structure includes a phase processing module, a multiplexer module, a NOT gate module, a parallel switch module and an AND gate module. The phase processing module includes a cascade squarer module, a first phase shifter module, a cascade phase negator module and a second phase shifter module;

[0129] The upper route of the non-phase-locked all-optical mode matching system for orthogonal phase shift keying signals is composed of a cascaded squarer, a 1*2 optical splitter and a 90° phase shifter, and the lower route is composed of a cascaded phase negator, a 90° phase shifter and a 1*4 optical splitter. The four interference sequences generated by the upper arm and the four interference sequences generated by the lower arm are input into four multiplexers one by one to interfere, and the interference matching results of the symbols of the four initial phases are obtained. After amplification by a fixed power amplifier, they are input into the NOT gate, and the output of the four NOT gates is used as the symbol matching result of the final output of the all-optical mode matching structure. The parallel module consists of N 4*1 switches, an optical delayer, a wavelength converter and an AND gate array. The control level of the 4*1 switch is set according to the symbol of the target sequence, so that the switch outputs the corresponding matching sequence. The N-way symbol matching sequence is delayed {(N-1)*T, (N-2)*T, ...0} in sequence according to the order of the symbols in the target sequence and then input into the AND gate array. The wavelength converter is used to ensure that the wavelengths of the two sequences input into the AND gate are different. After layers of AND gates are used to integrate N matching sequences, the output of the last layer of AND gates is used as the matching result between the final optical data sequence and the target sequence, that is, the result of pattern matching.

[0130] When the symbols match, the output of the NOT gate will have a high-power pulse output at the corresponding symbol position, while the unmatched position will output a low-power pulse of 0 or close to 0. Specifically, the cascade squarer on the link is used to convert the initial phases of all symbols in the input QPSK optical data sequence into one initial phase. If the four optional initial phases are Then the sequence output by the cascade squarer contains only symbols with an initial phase of {0}. By passing the sequence through a 90° phase shifter, we can obtain a sequence containing only symbols with an initial phase of The sequence of symbols is passed through a 90° phase shifter to obtain a sequence containing only symbols with an initial phase of {π}. The sequence is passed through a 90° phase shifter to obtain a sequence containing only symbols with an initial phase of {π}. The sequence of symbols is amplified or attenuated to obtain four channels with the same amplitude, and the initial phases are {0, 0…0}, {π, π…π} and The structure of the cascaded phase negator in the lower path is exactly the same as that of the squarer, except that the frequency of the pump light and the center frequency of the filter are set differently. Its function is to adopt a symmetrical structure to offset the influence of the FWM effect of the upper path squarer on the phase change rate. In the output sequence of the cascaded phase negator, the initial phase of each symbol is the same as the optical data sequence, and the center frequency and phase change rate of the sequence are the same as the sequence output by the cascaded squarer. After the output sequence of the cascaded phase negator is amplified to the same power as the output sequence of the squarer, it is passed through a cascaded 90° phase shifter to generate a 180° phase shift, and a second sequence to be interfered is obtained, which differs from the initial phase of each symbol of the optical data sequence by 180°. This sequence is divided into four identical sequences to be interfered by a 1*4 optical splitter for interference with the four first sequences to be interfered generated by the upper arm. The four interference sequences generated by the upper and lower paths are input into the multiplexer one by one to cause interference. The four multiplexers generate interference results corresponding to four symbols respectively. Destructive interference occurs at the position where the symbols match, and no pulse is output; pulses are output at the position where the symbols do not match, and the initial phase difference is The output of the non-matching symbol is 2P0, and the output of the non-matching symbol with an initial phase difference of π is 4P0. In order to eliminate the influence of inconsistent power at the non-matching position, the sequence after four-way interference is input into the NOT gate after passing through the fixed power amplifier. The symbol matching position with no pulse originally outputs a pulse with a larger power after passing through the NOT gate, while the non-matching position with a power of 4P0 originally outputs 0 after passing through the NOT gate, and the non-matching position with a power of 2P0 outputs close to 0 after passing through the NOT gate. The output of the four NOT gates is used as the final symbol matching result of the all-optical mode matching module. In the parallel module, according to the symbols in the N-bit target sequence, N 4*1 switches are controlled to output the corresponding symbol matching sequences respectively. These N sequences are passed through the optical delay device and delayed {(N-1)*T, (N-2)*T, ...0} respectively according to the symbol order in the target sequence, and then input into the AND gate array to AND two by two. Since the AND gate structures are all implemented based on the FWM effect of HNLF, a wavelength converter is required to ensure that the wavelengths of the two sequences input to the AND gate are different. After multiple layers of AND gates, the output of the last layer of AND gates is used as the matching result of the N-bit target sequence and the M-bit optical data sequence.

[0131] For the convenience of description, the above device is described in terms of functions divided into various modules. Of course, when implementing the present application, the functions of each module can be implemented in the same or multiple software and / or hardware.

[0132] The device of the above embodiment is used to implement the corresponding non-phase-locked all-optical mode matching method for orthogonal phase shift keying signals in any of the above embodiments, and has the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0133] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present application (including the claims) is limited to these examples. In line with the concept of the present application, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the present application as described above, which are not provided in detail for the sake of simplicity.

[0134] In addition, to simplify the description and discussion, and in order not to make the embodiments of the present application difficult to understand, the known power supply / ground connection with the integrated circuit (IC) chip and other components may or may not be shown in the provided drawings. In addition, the device can be shown in the form of a block diagram to avoid making the embodiments of the present application difficult to understand, and this also takes into account the fact that the details of the implementation of these block diagram devices are highly dependent on the platform to be implemented in the embodiments of the present application (that is, these details should be fully within the scope of understanding of those skilled in the art). In the case of elaborating specific details (e.g., circuits) to describe exemplary embodiments of the present application, it is obvious to those skilled in the art that the embodiments of the present application can be implemented without these specific details or when these specific details are changed. Therefore, these descriptions should be considered to be illustrative rather than restrictive.

[0135] Although the present application has been described in conjunction with specific embodiments of the present application, many replacements, modifications and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may use the embodiments discussed.

[0136] The embodiments of the present application are intended to cover all such substitutions, modifications and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present application should be included in the scope of protection of the present application.

Claims

1. A non-phase-locked all-optical mode matching method for quadrature phase shift keying signals, characterized in that: The invention is applied to a non-phase-locked all-optical mode matching system for quadrature phase shift keying signals, wherein the non-phase-locked all-optical mode matching system for quadrature phase shift keying signals comprises: a phase processing module, a multiplexer module, a NOT gate module, a parallel switch module and an AND gate module, and the method comprises: The phase processing module is used to perform phase processing on the acquired orthogonal phase shift keying optical data sequence divided into two paths, respectively, to obtain a first sequence to be interfered and a second sequence to be interfered; the phase of the first sequence to be interfered is a preset value; the phase of the second sequence to be interfered is opposite to the phase of the orthogonal phase shift keying optical data sequence; Using the multiplexer module to perform interference processing on the first sequence to be interfered with and the second sequence to be interfered with to obtain an interference sequence; Using the NOT gate module to perform inverse processing on the interference sequence to obtain a symbol matching result; Setting the control level of each switch in the parallel switch module according to a preset target sequence, and processing the symbol matching result by using the set parallel switch module to obtain a matching sequence; setting a delay for the matching sequence; The matching sequence is processed in sequence using the AND gate module to obtain a pattern matching result.

2. The method according to claim 1, characterized in that The phase processing module includes a cascade squarer module and a first phase shifter module; the orthogonal phase shift keying optical data sequence is divided into two paths to obtain a first optical data sequence and a second optical data sequence; The phase processing module is used to perform phase processing on the acquired orthogonal phase shift keying optical data sequence divided into two paths, respectively, to obtain a first sequence to be interfered and a second sequence to be interfered, including: Using the cascade squarer module to return the phase of the first optical data sequence to zero, to obtain a first sequence; Using the first phase shifter module to perform multiple phase shifting processes on the first sequence to obtain the first sequence to be interfered; The second optical data sequence is phase processed by the phase processing module to obtain the second sequence to be interfered.

3. The method according to claim 2, characterized in that The phase processing module comprises a cascaded phase negator module and a second phase shifter module; The using the phase processing module to perform phase processing on the second optical data sequence to obtain the second sequence to be interfered includes: The phase of the second optical data sequence is processed by the cascade phase negator module to obtain a second sequence; the second sequence has the same initial phase as the second optical data sequence; The second sequence is phase-shifted by 180 degrees using the second phase shifter module to obtain the second sequence to be interfered; the center frequency and phase change rate of the second sequence are the same as those of the first sequence.

4. The method according to claim 2, characterized in that: The cascade squarer module includes two squarers; The using the cascade squarer module to perform zeroing processing on the phase of the first optical data sequence to obtain a first sequence includes: The two squarers are used to perform a second doubling process on the phase of the first optical data sequence to obtain the first sequence.

5. The method according to claim 2, characterized in that: The first phase shifter module includes a plurality of optical splitters and three phase shifters; The using the first phase shifter module to perform multiple phase shifting processes on the first sequence to obtain the first sequence to be interfered includes: Using the optical splitter to split the first sequence into two paths, to obtain a first intermediate sequence and a second intermediate sequence; Using the phase shifter to perform a 90-degree phase shift on the second intermediate sequence to obtain a third intermediate sequence; Using the optical splitter to split the third intermediate sequence into two paths, thereby obtaining a fourth intermediate sequence and a fifth intermediate sequence; Using the phase shifter to perform a 90-degree phase shift on the fifth intermediate sequence to obtain a sixth intermediate sequence; Using the optical splitter to split the sixth intermediate sequence into two paths, thereby obtaining a seventh intermediate sequence and an eighth intermediate sequence; Using the phase shifter to perform a 90-degree phase shift on the eighth intermediate sequence to obtain a ninth intermediate sequence; The first intermediate sequence, the fourth intermediate sequence, the seventh intermediate sequence and the ninth intermediate sequence are used as the first sequence to be interfered.

6. The method according to claim 5, characterized in that The multiplexer module includes four multiplexers; the phase processing module includes a splitter; The using the multiplexer module to perform interference processing on the first sequence to be interfered with and the second sequence to be interfered with to obtain an interference sequence includes: inputting the first intermediate sequence, the fourth intermediate sequence, the seventh intermediate sequence and the ninth intermediate sequence into the four multiplexers respectively; Using the optical splitter to divide the second sequence to be interfered into four paths and inputting the four paths into the four multiplexers respectively; The multiplexer is used to perform interference processing on the existing sequences in the multiplexer to obtain four groups of interference sequences.

7. The method according to any one of claims 1 to 6, characterized in that: The step of setting the control level of each switch in the parallel switch module according to a preset target sequence, and processing the symbol matching result by using the set parallel switch module to obtain a matching sequence includes: According to the initial phase order of the symbols in the target sequence, the control level of each switch in the parallel switch module is set in sequence; The symbol matching result is input into the set parallel switch module, matched with the control level of each switch, and the matching sequence is obtained.

8. The method according to any one of claims 1 to 6, characterized in that: The step of setting a delay for the matching sequence includes: Starting from the matching sequence corresponding to the last symbol of the target sequence, the delay of each matching sequence is set to an arithmetic progression starting from zero in reverse order of the symbols in the target sequence; the tolerance of the arithmetic progression is a positive value of the unit symbol time.

9. The method according to any one of claims 1 to 6, characterized in that: The using the AND gate module to sequentially process the matching sequence to obtain a pattern matching result includes: According to the positive order of the matching sequences, every two matching sequences are taken as a group and input into the AND gate module to obtain a first result; In response to the number of the first results being greater than one, every two of the first results are taken as a group and input into the AND gate module according to the positive order of the first results, until the number of the first results is one, thereby obtaining a second result; In response to the presence of a first number of pulse signals in the second result, the result of the pattern matching is that a first number of the target sequences exist in the orthogonal phase shift keying optical data sequence; In response to the pulse signal not existing in the second result, the result of the pattern matching is that the target sequence does not exist in the quadrature phase shift keying optical data sequence.

10. A non-phase-locked all-optical mode matching system for quadrature phase shift keying signals, characterized in that: include: Phase processing module, multiplexer module, NOT gate module, parallel switch module and AND gate module; The phase processing module is used to perform phase processing on the acquired orthogonal phase shift keying optical data sequence divided into two paths, respectively, to obtain a first sequence to be interfered and a second sequence to be interfered; the phase of the first sequence to be interfered is a preset value; the phase of the second sequence to be interfered is opposite to the phase of the orthogonal phase shift keying optical data sequence; The multiplexer module is used to perform interference processing on the first sequence to be interfered and the second sequence to be interfered to obtain an interference sequence; The NOT gate module is used to perform inverse code processing on the interference sequence to obtain a symbol matching result; The parallel switch module is used to set the control level of each switch in the parallel switch module according to a preset target sequence, and process the symbol matching result to obtain a matching sequence; and set a delay for the matching sequence; The AND gate module is used to process the matching sequence in sequence to obtain a pattern matching result.

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