Netlist reconstruction optimization method and device, equipment and storage medium
By acquiring and moving the coupled design units in an integrated circuit to optimize the signal path, the problems of inefficiency and blindness in traditional methods are solved, and more effective timing performance optimization is achieved.
Patent Information
- Application Number
- CN202411049565.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-31
- Publication Date
- 2024-12-06
AI Technical Summary
The traditional seed point unit replication optimization method based on timing analysis is inefficient in operation in integrated circuits, and there is blindness and randomness, resulting in less obvious improvement in timing performance and increasing area.
By obtaining the signal path to be optimized to be optimized, determining the coupled design units have, copying and moving these coupled design units to shorten the signal delay, the specific steps include obtaining the signal path to be optimized, determining the coupled design unit, copying and moving the coupled design unit to Reduce the bounding box of the signal path, thereby optimizing signal delay.
It effectively improves operation efficiency, avoids blindness and randomness, significantly shortens signal delay, and improves timing performance optimization effect.
Smart Images
Figure CN119089833A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to an optimization method, device, equipment and storage medium for netlist reconstruction. Background Art
[0002] In the field of integrated circuits, an important purpose of refactoring the netlist of an integrated circuit during the layout phase is to improve the timing performance of the design. Ways to refactor the netlist include exchanging the input pin network of a design unit, duplicating a design unit, and merging design units.
[0003] In order to optimize timing performance, it is usually achieved by copying design units. However, the traditional copying method based on seed points (usually refers to some key locations selected in the circuit netlist. These locations are used as the starting point for inserting additional units to try to improve the timing behavior of the entire circuit) often has problems such as long running time, no obvious improvement in timing performance, and easy to cause invalid optimization resulting in increased area.
[0004] In summary, the traditional seed point unit replication optimization method based on timing analysis is not only inefficient but also blind and random. Summary of the invention
[0005] The present invention provides a netlist reconstruction optimization method, device, equipment and storage medium, which are used to solve the problems in the prior art that when optimizing the timing performance of an integrated circuit, the unit replication optimization method used has low operating efficiency and is blind and random.
[0006] In order to solve the above technical problems, in a first aspect, the present invention provides a netlist reconstruction optimization method, comprising:
[0007] Obtain a signal path to be optimized that requires timing optimization;
[0008] Determining a plurality of signal paths to be optimized having coupling design units, wherein the coupling design units are simultaneously located in all of the signal paths to be optimized;
[0009] duplicating the coupling design unit to form a coupling design unit combination;
[0010] The target coupling design unit in the coupling design unit combination is moved to the target signal path to be optimized, so as to shorten the signal delay corresponding to the target signal path to be optimized.
[0011] Optionally, shortening the signal delay corresponding to the target signal path to be optimized is specifically:
[0012] The bounding box of the target signal path to be optimized is reduced, wherein the bounding box is a minimum rectangular box surrounding all design units in the target signal path to be optimized.
[0013] Optionally, the reducing the bounding box of the target signal path to be optimized is specifically:
[0014] The perimeter and / or area of the bounding box of the target signal path to be optimized is reduced.
[0015] Optionally, moving the target coupling design unit in the coupling design unit combination to a target signal path to be optimized to shorten a signal delay corresponding to the target signal path to be optimized includes:
[0016] The target coupling design unit is moved along the length direction and the width direction of the boundary box respectively until the length and the width of the boundary box reach a minimum value.
[0017] Optionally, the signal path to be optimized is a path with the longest signal delay between two nodes.
[0018] Optionally, obtaining a signal path to be optimized that needs to be timing optimized includes:
[0019] Evaluate the signal path with the longest signal delay between any two nodes;
[0020] When the signal delay of the signal path is greater than a preset threshold, the signal path is obtained as the signal path to be optimized.
[0021] In a second aspect, the present invention provides an optimization device for netlist reconstruction, comprising:
[0022] An acquisition module, used for acquiring a signal path to be optimized that needs timing optimization;
[0023] A determination module, used for determining a plurality of signal paths to be optimized having coupling design units, wherein the coupling design units are simultaneously located in all the signal paths to be optimized;
[0024] A copy module, used for copying the coupling design unit to form a coupling design unit combination;
[0025] The moving module is used to move the target coupling design unit in the coupling design unit combination to the target signal path to be optimized, so as to shorten the signal delay corresponding to the target signal path to be optimized.
[0026] In a third aspect, the present invention provides a netlist reconstruction optimization device, comprising a memory and a processor, wherein:
[0027] The memory is used to store computer programs;
[0028] The processor is used to read the program in the memory and execute the steps of the netlist reconstruction optimization method provided in the first aspect above.
[0029] In a fourth aspect, the present invention provides a computer-readable storage medium having a readable computer program stored thereon, which, when executed by a processor, implements the steps of the netlist reconstruction optimization method provided in the first aspect above.
[0030] Compared with the prior art, the netlist reconstruction optimization method provided by the present invention has the following beneficial effects:
[0031] The design unit copied by the present invention is a coupled design unit of multiple signal paths to be optimized. It can be understood that the coupled design unit can be directly obtained by traversing the signal path to be optimized. Obviously, compared with the need to traverse multiple possible replication schemes when copying the design unit based on the seed point in the prior art, this can avoid the blindness of copying the design unit and can effectively improve the operating efficiency. In addition, when the target coupled design unit in the coupled design unit combination is moved to the target signal path to be optimized in the present invention, it can ensure that the signal delay corresponding to the target signal path to be optimized is reduced. Obviously, compared with the prior art based on seed point replication of the design unit, this can avoid the problem of randomness in the optimization effect after the unit replication caused by the randomness of the seed point. In summary, the present invention can solve the problem of low operating efficiency, blindness and randomness of the unit replication optimization method used in the prior art when optimizing the timing performance of the integrated circuit. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only part of the embodiments of the present invention, rather than all of the embodiments. For ordinary technicians in this field, without paying creative work, other drawings obtained based on these drawings all fall within the scope of protection of the present invention.
[0033] Figure 1 is a flow chart of a netlist reconstruction optimization method provided by an embodiment of the present invention;
[0034] Figure 2-Figure 5 is an optimized schematic diagram of netlist reconstruction provided by an embodiment of the present invention;
[0035] Figure 6 is a structural diagram of a netlist reconstruction optimization device provided by an embodiment of the present invention;
[0036] Figure 7It is a structural schematic diagram of a netlist reconstruction optimization device provided by an embodiment of the present invention;
[0037] Figure 8 It is a structural schematic diagram of a computer-readable storage medium provided by an embodiment of the present invention. DETAILED DESCRIPTION
[0038] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.
[0039] In order to make the description of the disclosed content more detailed and complete, the following is an illustrative description of the implementation mode and specific examples of the present invention; however, this is not the only form of implementing or applying the specific embodiments of the present invention. The implementation mode covers the features of multiple specific embodiments and the method steps and their sequence for constructing and operating these specific embodiments. However, other specific embodiments can also be used to achieve the same or equal functions and step sequences. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.
[0040] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein.
[0041] In addition, in the description of the embodiments of the present invention, "multiple" means two or more than two, and other quantifiers are similar and should be understood. The preferred embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention. In addition, the embodiments of the present invention and the features therein may be combined with each other without conflict.
[0042] like Figure 1 The flowchart shown is a method for optimizing netlist reconstruction provided by an embodiment of the present invention, which includes the following steps.
[0043] Step S101, obtaining a signal path to be optimized that needs to be timing optimized.
[0044] It is understandable that the signal path to be optimized that needs to be optimized in this step is a path with poor timing indicators. The timing indicator can be defined according to the specific needs of the application, and is not limited in detail here, and the threshold of the timing indicator used to determine whether the signal path is the signal path to be optimized can be set according to the specific needs of the application. For example, when the timing indicator of a certain signal path is greater than the threshold, the signal path can be determined to be a signal path to be optimized.
[0045] As a specific example, Figure 2 The figure shows a schematic diagram of three signal paths (signal path A-signal path C), in which the rectangles represent the design units, and the lines between the rectangles represent the lines between the design units. It can be seen that the signal delays of signal path A and signal path C are large, and it can be considered that the timing of signal path A and signal path C is poor, and they can be used as signal paths to be optimized.
[0046] Step S102: determining a plurality of signal paths to be optimized having coupling design units.
[0047] The coupling design unit is located in all the signal paths to be optimized at the same time.
[0048] It can be understood that the coupling design unit of multiple signal paths to be optimized is a design unit shared by the ends of these signal paths to be optimized.
[0049] It should be noted that the coupling design unit may be located at a legal position in the signal path to be optimized, for example, may be located at a starting point or an end point in the signal path to be optimized.
[0050] As a specific example, Figure 2 As shown, it can be seen that the design unit D is located on the signal path A and the signal path C at the same time, so the design unit D is a coupled design unit of the signal path A and the signal path C.
[0051] As a specific example, Figure 3 As shown, the boundary boxes corresponding to the signal path A and the signal path C can be drawn, so that the design unit D can be determined as the coupling design unit of the signal path A and the signal path C by determining the design unit where the two intersect.
[0052] Step S103, copying the coupling design unit to form a coupling design unit combination.
[0053] It should be noted that the coupling design unit obtained after duplication in this step may be a coupling design unit having the same function as the original coupling design unit.
[0054] It should be noted that the number of the coupling design units copied in this step, that is, the number of coupling design units in the coupling design unit combination, can be defined according to specific needs during application, for example, it can be the same as the number of all signal paths to be optimized;
[0055] However, it should be noted that the number of coupling design units in the coupling design unit combination needs to be greater than the number of previous coupling design units.
[0056] As a specific example, Figure 4 As shown, after copying the design unit D, a copied coupled design unit F can be obtained, so that the design unit D and the design unit F can form a coupled design unit combination.
[0057] Step S104, moving the target coupling design unit in the coupling design unit combination to the target signal path to be optimized, so as to shorten the signal delay corresponding to the target signal path to be optimized.
[0058] However, it should be noted that the method of moving the target coupling design unit in the coupling design unit combination to the path of the target signal to be optimized can be any feasible method as long as it can ensure that the signal delay corresponding to the path of the target signal to be optimized can be shortened.
[0059] As a specific example, the target coupling design unit may be moved from the position of the coupling design unit before replication, and the target signal path to be optimized may be shortened during the movement, so as to achieve the purpose of shortening the signal delay corresponding to the target signal path to be optimized.
[0060] The design unit copied by the embodiment of the present invention is a coupled design unit of multiple signal paths to be optimized. It can be understood that the coupled design unit can be directly obtained by traversing the signal path to be optimized. Obviously, compared with the need to traverse multiple possible replication schemes when copying the design unit based on the seed point in the prior art, this can avoid the blindness of copying the design unit and can effectively improve the operating efficiency. In addition, in the embodiment of the present invention, when the target coupled design unit in the coupled design unit combination is moved to the target signal path to be optimized, it can ensure that the signal delay corresponding to the target signal path to be optimized is reduced. Obviously, compared with the prior art based on seed point replication of the design unit, this can avoid the problem of randomness in the optimization effect after the unit replication caused by the randomness of the seed point. In summary, the embodiment of the present invention can solve the problem of low operating efficiency, blindness and randomness of the unit replication optimization method used in the prior art when optimizing the timing performance of the integrated circuit.
[0061] In an optional implementation manner, shortening the signal delay corresponding to the target signal path to be optimized is specifically:
[0062] The bounding box of the target signal path to be optimized is reduced.
[0063] The boundary box is a minimum rectangular box surrounding all design units in the target signal path to be optimized.
[0064] It should be noted that the delay of the signal path is closely related to its corresponding bounding box. For example, the smaller the bounding box, the smaller the delay of the signal path. By keeping the side lengths of the bounding box moderate and symmetrical, the delay of the signal path can also be optimized.
[0065] Therefore, it can be understood that by reducing the bounding box of the target signal path to be optimized, the signal delay corresponding to the target signal path to be optimized can be shortened, and measuring the size of the bounding box is easier to achieve than directly measuring the delay of the target path to be optimized. Therefore, the solution of this implementation method can make it easier to shorten the signal delay corresponding to the target path to be optimized.
[0066] In an optional implementation manner, the reducing the bounding box of the target signal path to be optimized is specifically:
[0067] The perimeter and / or area of the bounding box of the target signal path to be optimized is reduced.
[0068] It can be understood that by reducing the perimeter and / or area of the bounding box of the target signal path to be optimized, the purpose of shrinking the bounding box can be achieved.
[0069] It should be noted that the method of reducing the perimeter and / or area of the bounding box of the target signal path to be optimized can be any feasible method, for example, the target coupling design unit can be moved along the diagonal of the bounding box to reduce the perimeter and / or area of the bounding box, or the target coupling design unit can be moved along the side length of the bounding box to reduce the perimeter and / or area of the bounding box.
[0070] In an optional implementation, moving the target coupling design unit in the coupling design unit combination to the target signal path to be optimized to shorten the signal delay corresponding to the target signal path to be optimized includes:
[0071] The target coupling design unit is moved along the length direction and the width direction of the boundary box respectively until the length and the width of the boundary box reach a minimum value.
[0072] It can be understood that in this implementation, when the target coupling design unit moves to the minimum length and width along the length and width directions of the boundary box respectively, the area of the boundary box also reaches the minimum value, so that the signal delay corresponding to the target path to be optimized also reaches the minimum value, thereby achieving the purpose of optimizing the timing of the target path to be optimized.
[0073] As a specific example, Figure 5 As shown, the design unit D and the design unit F are respectively moved in the width direction of the boundary box of the signal path A and the boundary box of the signal path C until they are moved to the minimum value of the width, so that the area of the boundary box is minimized; and Figure 2-Figure 5 As shown in FIG. , there are FF (Flip-Flop, trigger) and LUT (Look-Up Table, look-up table).
[0074] In an optional implementation, the signal path to be optimized is a path with the longest signal delay between two nodes.
[0075] It should be noted that the two nodes in this implementation are the input node and the output node of the path.
[0076] It can be understood that if the signal delay of the path with the longest signal delay between two nodes reaches the minimum value, the signal delays corresponding to all signal paths between the two nodes can be small enough, thereby ensuring the optimization effect of the integrated circuit timing to the greatest extent by replicating the design unit.
[0077] In an optional implementation, obtaining a signal path to be optimized that needs to be timing optimized includes:
[0078] Evaluate the signal path with the longest signal delay between any two nodes;
[0079] When the signal delay of the signal path is greater than a preset threshold, the signal path is obtained as the signal path to be optimized.
[0080] It should be noted that the method for evaluating the signal path with the largest signal delay between two nodes can be any feasible method, such as inputting signals to the input nodes of all signal paths between the two nodes and recording the input time, monitoring the output time of the output signals of the output nodes of each signal path, and then obtaining the signal delay of the signal path by subtracting the input time from the output time. In this way, the signal path with the largest signal delay between the two nodes can be compared.
[0081] It should be noted that the preset threshold in this implementation can be set according to specific needs during application and is not limited in detail here.
[0082] Based on the above-mentioned netlist reconstruction optimization method, the embodiment of the present invention provides a netlist reconstruction optimization device, such as Figure 6 As shown, the present invention provides an optimization device for netlist reconstruction, comprising:
[0083] An acquisition module 610 is used to acquire a signal path to be optimized that needs to be optimized in timing;
[0084] A determination module 620, configured to determine a plurality of signal paths to be optimized having coupling design units, wherein the coupling design units are simultaneously located in all of the signal paths to be optimized;
[0085] A copy module 630, used to copy the coupling design unit to form a coupling design unit combination;
[0086] The moving module 640 is used to move the target coupling design unit in the coupling design unit combination to the target signal path to be optimized, so as to shorten the signal delay corresponding to the target signal path to be optimized.
[0087] For other details about how the modules in the above-mentioned netlist reconstruction optimization device implement the above-mentioned technical solution, please refer to the description of the netlist reconstruction optimization method provided in the above-mentioned invention embodiment, which will not be repeated here.
[0088] Based on the above netlist reconstruction optimization method, such as Figure 7 As shown, an embodiment of the present invention further provides a schematic diagram of the structure of a netlist reconstruction optimization device, the identification device includes a processor 71 and a memory 72 coupled to the processor 71. The memory 72 stores a computer program, and when the computer program is executed by the processor 71, the processor 71 executes the steps of the netlist reconstruction optimization method in the above embodiment.
[0089] For other details about how the processor 71 in the above-mentioned netlist reconstruction optimization device implements the above-mentioned technical solution, please refer to the description of the netlist reconstruction optimization method provided in the above-mentioned invention embodiment, which will not be repeated here.
[0090] Among them, the processor 71 can also be called a CPU (Central Processing Unit), and the processor 71 may be an integrated circuit chip with signal processing capabilities; the processor 71 can also be a general-purpose processor, DSP (Digital Signal Process), ASIC (Application Specific Integrated Circuit), FPGA (Field Programmable Gate Array) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, among which the general-purpose processor can be a microprocessor or the processor 71 can also be any conventional processor, etc.
[0091] like Figure 8 As shown, the embodiment of the present invention also provides a schematic diagram of the structure of a computer-readable storage medium, on which a readable computer program 81 is stored; wherein the computer program 81 can be stored in the above storage medium in the form of a software product, including a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor to execute all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, magnetic disk or optical disk, ROM (Read-Only Memory), RAM (Random Access Memory) and other media that can store program codes, or terminal devices such as computers, servers, mobile phones, and tablets.
[0092] In the several embodiments provided by the present invention, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the modules is only a logical function division. There may be other division methods in actual implementation, such as multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or modules, which can be electrical, mechanical or other forms.
[0093] The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical modules, that is, they may be located in one place or distributed on multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
[0094] In addition, each functional module in each embodiment of the present invention may be integrated into a processing module, or each module may exist physically separately, or two or more modules may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may be stored in a computer-readable storage medium.
[0095] In the above embodiments, all or part of the embodiments may be implemented by software, hardware, firmware or any combination thereof. When implemented by software, all or part of the embodiments may be implemented in the form of a computer program product.
[0096] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present invention is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from one website site, computer, server or data center to another website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that a computer can store or a data storage device such as a server or data center that includes one or more available media integrated. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium), or a semiconductor medium (e.g., an SSD (solid state disk, solid state hard disk)).
[0097] The technical solution provided by the present invention is introduced in detail above. The present invention applies specific examples to illustrate the principle and implementation mode of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of the present invention, there will be changes in the specific implementation mode and application scope. In summary, the content of this specification should not be understood as limiting the present invention.
[0098] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, optical storage, etc.) containing computer-usable program code.
[0099] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.
[0100] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.
[0101] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.
[0102] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.
Claims
1. A netlist reconstruction optimization method, It is characterized in that include: Obtain a signal path to be optimized that requires timing optimization; Determining a plurality of signal paths to be optimized having coupling design units, wherein the coupling design units are simultaneously located in all of the signal paths to be optimized; duplicating the coupling design unit to form a coupling design unit combination; The target coupling design unit in the coupling design unit combination is moved to the target signal path to be optimized, so as to shorten the signal delay corresponding to the target signal path to be optimized.
2. The netlist reconstruction optimization method according to claim 1, It is characterized in that The shortening of the signal delay corresponding to the target signal path to be optimized is specifically: The bounding box of the target signal path to be optimized is reduced, wherein the bounding box is a minimum rectangular box surrounding all design units in the target signal path to be optimized.
3. The netlist reconstruction optimization method according to claim 2, It is characterized in that The step of reducing the bounding box of the target signal path to be optimized is specifically: The perimeter and / or area of the bounding box of the target signal path to be optimized is reduced.
4. The netlist reconstruction optimization method according to claim 2, It is characterized in that The step of moving the target coupling design unit in the coupling design unit combination to the target signal path to be optimized, and shortening the signal delay corresponding to the target signal path to be optimized, comprises: The target coupling design unit is moved along the length direction and the width direction of the boundary box respectively until the length and the width of the boundary box reach a minimum value.
5. The netlist reconstruction optimization method according to claim 1, It is characterized in that The signal path to be optimized is a path with the longest signal delay between two nodes.
6. The netlist reconstruction optimization method according to claim 1, It is characterized in that The obtaining of a signal path to be optimized that needs to be timing optimized includes: Evaluate the signal path with the longest signal delay between any two nodes; When the signal delay of the signal path is greater than a preset threshold, the signal path is obtained as the signal path to be optimized.
7. A netlist reconstruction optimization device, It is characterized in that include: An acquisition module, used for acquiring a signal path to be optimized that needs timing optimization; A determination module, used for determining a plurality of signal paths to be optimized having coupling design units, wherein the coupling design units are simultaneously located in all the signal paths to be optimized; A copy module, used for copying the coupling design unit to form a coupling design unit combination; The moving module is used to move the target coupling design unit in the coupling design unit combination to the target signal path to be optimized, so as to shorten the signal delay corresponding to the target signal path to be optimized.
8. The netlist reconstruction optimization device according to claim 7, It is characterized in that The mobile module is also used for: The bounding box of the target signal path to be optimized is reduced, wherein the bounding box is a minimum rectangular box surrounding all design units in the target signal path to be optimized.
9. A netlist reconstruction optimization device, It is characterized in that comprising a memory and a processor, wherein: The memory is used to store computer programs; The processor is used to read the computer program in the memory and execute the steps of any netlist reconstruction optimization method according to claims 1-6.
10. A computer-readable storage medium, It is characterized in that A readable computer program is stored thereon, and when the program is executed by a processor, the steps of any netlist reconstruction optimization method as claimed in claims 1-6 are implemented.