Semiconductor structure and preparation method thereof

Abstract

The invention provides a semiconductor structure and a preparation method thereof. The preparation method of the semiconductor structure comprises the steps that a substrate is provided, and a metal interconnection structure is formed on the substrate; forming a buffer material layer on the surface of the substrate and the side wall and the top surface of the metal interconnection structure; and performing self-ion implantation on the buffer material layer to convert the buffer material layer into a buffer layer. The preparation method of the semiconductor structure is beneficial for improving the stability and the production yield of the semiconductor structure.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] As semiconductor manufacturing processes develop towards 65nm and below nodes, dielectric filling technology becomes crucial in the manufacture of integrated circuits. High-density plasma chemical vapor deposition (HDP-CVD) technology has become one of the mainstream technologies for dielectric filling in these advanced nodes due to its excellent filling performance in high aspect ratio structures.

[0003] The HDP-CVD process has the characteristics of high plasma density and strong glow. Although these characteristics can effectively improve the filling quality of dielectrics, they also bring potential process risks. Especially in the HDP-CVD process, the high-density plasma may cause charging and discharging of the underlying interconnect metal, thereby causing damage to the metal interconnect. In addition, the HDP-CVD process usually uses argon ion bombardment to keep the top of the trench open to ensure the smooth progress of the filling process. However, argon ion bombardment often causes metal chamfering, and even in severe cases, causes disconnection and electrical failure of the metal interconnect.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present application, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0005] Based on this, the embodiments of the present application provide a semiconductor structure and a method for preparing the same, which are beneficial to improving the stability and production yield of the semiconductor structure.

[0006] According to some embodiments, the present application provides a method for preparing a semiconductor structure, which is applied before a chemical vapor deposition process. The method for preparing a semiconductor structure includes:

[0007] Providing a substrate, on which a metal interconnection structure is formed;

[0008] forming a buffer material layer on the substrate surface and the sidewalls and top surface of the metal interconnect structure;

[0009] The buffer material layer is self-ion-implanted to transform the buffer material layer into a buffer layer.

[0010] In some embodiments, the buffer material layer includes a silicon-containing oxide layer.

[0011] In some embodiments, forming a buffer material layer on the substrate surface and the sidewalls and top surface of the metal interconnect structure includes:

[0012] The silicon-containing oxide layer is formed on the substrate surface and the sidewalls and top surface of the metal interconnect structure by a plasma enhanced chemical vapor deposition process to serve as the buffer material layer.

[0013] In some embodiments, the buffer material layer has a thickness ranging from 300 nm to 800 nm.

[0014] In some embodiments, when the self-ion implantation is performed on the buffer material layer, the substrate temperature ranges from 25° C. to 50° C.

[0015] In some embodiments, when the self-ion implantation is performed on the buffer material layer, the ion implantation energy range includes 20 KeV to 70 KeV.

[0016] In some embodiments, when the buffer material layer is subjected to the self-ion implantation, the ion implantation dose range includes 1×10 15 cm -2 ~1×10 17 cm -2 .

[0017] In some embodiments, after the buffer material layer is transformed into the buffer layer, the method for preparing the semiconductor structure further includes:

[0018] The buffer layer is annealed.

[0019] In some embodiments, when the buffer layer is annealed, the annealing temperature ranges from 300° C. to 500° C., and / or the annealing time ranges from 50 minutes to 70 minutes.

[0020] According to some embodiments, the present application further provides a semiconductor structure on the other hand, wherein the semiconductor structure is prepared by using the method for preparing the semiconductor structure provided in any of the aforementioned embodiments.

[0021] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application.

[0022] The embodiments of the present application may or at least have the following advantages:

[0023] In the embodiment of the present application, a buffer layer is formed on the substrate surface and the side walls and top surfaces of the metal interconnect structure before the chemical vapor deposition process. The buffer layer is beneficial for protecting the metal interconnect structure during the subsequent chemical vapor deposition process and improving the stability of the metal interconnect structure during the chemical vapor deposition process. It is also beneficial for improving the processing effect of the subsequent chemical vapor deposition process, making the structure generated by the deposition more uniform and reducing the generation of holes and cracks.

[0024] In an embodiment of the present application, a buffer material layer is first formed on the substrate surface and the sidewalls and top surface of the metal interconnect structure, and then the buffer material layer is self-ion implanted to transform it into a buffer layer. The buffer layer formed by self-ion implantation has a narrower band gap. This band gap characteristic enables the buffer layer to more effectively suppress the accumulation and conduction of plasma charges, and prevents charge damage that may be caused to the metal interconnect structure during the chemical vapor deposition process. Self-ion implantation can also make the buffer layer have a higher density, so that it can effectively resist ion bombardment during the deposition process of the chemical vapor deposition process, greatly reducing the occurrence of metal chamfering, and avoiding mechanical damage and potential circuit breaker risks caused by ion bombardment to the metal interconnect structure.

[0025] Therefore, the application of the embodiments of the present application can be beneficial to improving the stability and production yield of the semiconductor structure.

[0026] Other advantages, objectives and features of the present application will be described in the following description to some extent, and will be apparent to those skilled in the art based on the following examination and study, or can be taught from the practice of the present application to some extent. The objectives and other advantages of the present application can be achieved and obtained through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings.

[0028] Figure 1 A schematic diagram of a process for preparing a semiconductor structure provided in some embodiments of the present application;

[0029] Figure 2 A schematic diagram of a cross-sectional structure of a structure obtained after a metal interconnect structure is formed in a method for preparing a semiconductor structure provided in some embodiments of the present application;

[0030] Figure 3 A schematic diagram of a cross-sectional structure of a structure obtained after a buffer material layer is formed in a method for preparing a semiconductor structure provided in some embodiments of the present application;

[0031] Figure 4 A schematic diagram of a cross-sectional structure of a structure obtained after a buffer layer is formed in a method for preparing a semiconductor structure provided in some embodiments of the present application;

[0032] Figure 5 This is a schematic cross-sectional structural diagram of a structure obtained after forming an isolation dielectric layer in a method for preparing a semiconductor structure provided in some embodiments of the present application.

[0033] Description of reference numerals:

[0034] 11. Metal interconnect structure; 20. Buffer material layer; 30. Buffer layer; 40. Isolation dielectric layer. DETAILED DESCRIPTION

[0035] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0037] It should be understood that when an element or layer is referred to as being "on..." or "adjacent...", it may be directly on or adjacent to other elements or layers, or there may be intervening elements or layers. Spatial relationship terms such as "on..." may be used here to describe the relationship between an element or feature shown in the figures and other elements or features. It should be understood that in addition to the orientations shown in the figures, spatial relationship terms also include different orientations of devices in use and operation. For example, if the device in the accompanying drawings is flipped, the element or feature described as "on..." will be oriented to be "under..." other elements or features. Therefore, the exemplary term "on..." may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0038] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0039] The HDP-CVD process has the characteristics of high plasma density and strong glow. Although these characteristics can effectively improve the filling quality of dielectrics, they also bring potential process risks. Especially in the HDP-CVD process, the high-density plasma may cause charging and discharging of the underlying interconnect metal, thereby causing damage to the metal interconnect. In addition, the HDP-CVD process usually uses argon ion bombardment to keep the top of the trench open to ensure the smooth progress of the filling process. However, argon ion bombardment often causes metal chamfering, and even in severe cases, causes disconnection and electrical failure of the metal interconnect.

[0040] In view of the shortcomings of the related art, the present application provides a semiconductor structure and a method for manufacturing the same, which are beneficial to improving the stability and production yield of the semiconductor structure. The details will be described in the subsequent embodiments.

[0041] According to some embodiments, the present application provides a method for preparing a semiconductor structure, which is applied before a chemical vapor deposition process, for example, before a high-density plasma chemical vapor deposition (HDP-CVD) process.

[0042] See also Figure 1 The method for preparing the semiconductor structure may specifically include the following steps S100 to S300:

[0043] S100: providing a substrate, on which a metal interconnection structure is formed.

[0044] S200: forming a buffer material layer on the substrate surface and the sidewalls and top surface of the metal interconnect structure.

[0045] S300: performing self-ion implantation on the buffer material layer to transform the buffer material layer into a buffer layer.

[0046] In the above preparation method, before the chemical vapor deposition process, a buffer layer is formed on the substrate surface and the side walls and top surface of the metal interconnect structure. The buffer layer is beneficial to protecting the metal interconnect structure during the subsequent chemical vapor deposition process and improving the stability of the metal interconnect structure during the chemical vapor deposition process; it is also beneficial to improve the processing effect of the subsequent chemical vapor deposition process, making the deposited structure more uniform and reducing the generation of holes and cracks.

[0047] In the above preparation method, a buffer material layer is first formed on the substrate surface and the sidewalls and top surface of the metal interconnect structure, and then the buffer material layer is self-ion implanted to transform it into a buffer layer. The buffer layer formed by self-ion implantation has a narrower band gap. This band gap characteristic enables the buffer layer to more effectively suppress the accumulation and conduction of plasma charges, and prevents charge damage that may be caused to the metal interconnect structure during the chemical vapor deposition process. Self-ion implantation can also make the buffer layer have a higher density, so that it can effectively resist ion bombardment during the deposition process of the chemical vapor deposition process, greatly reducing the occurrence of metal chamfering, and avoiding mechanical damage and potential circuit breaker risks caused by ion bombardment to the metal interconnect structure.

[0048] Therefore, the application of the above preparation method can be beneficial to improving the stability and production yield of the semiconductor structure.

[0049] In order to more clearly illustrate the preparation method provided in the above embodiment, Figures 2 to 5 Understand some embodiments of the present application.

[0050] In step S100, refer to Figure 2 , providing a substrate ( Figure 2 (not shown in the figure), a metal interconnection structure 11 is formed on the substrate.

[0051] As an example, the substrate can be made of semiconductor material, insulating material, conductor material or any combination of their material types. The substrate can be a single-layer structure or a multi-layer structure. For example, the substrate can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGe C) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate or other III / V semiconductor substrates or II / VI semiconductor substrates. Or, for example, the substrate can be a layered substrate including a stack of Si and SiGe, a stack of Si and SiC, a silicon on insulator (SOI) or a silicon germanium on insulator, etc.

[0052] See also Figure 3 In step S200 , a buffer material layer 20 is formed on the substrate surface and the sidewalls and top surface of the metal interconnect structure 11 .

[0053] The present embodiment does not specifically limit the constituent materials of the buffer material layer 20 formed on the substrate surface and the sidewalls and top surfaces of the metal interconnect structure 11. In some embodiments, the buffer material layer 20 may include a silicon-containing oxide layer, but is not limited thereto.

[0054] As an example, the silicon-containing oxide layer may include, but is not limited to, a silicon dioxide (SiO 2 ) layer.

[0055] In some embodiments, the above step S200 may be specifically performed as follows: using a plasma-enhanced chemical vapor deposition (PE CVD) process to form a silicon-containing oxide layer on the substrate surface and the sidewalls and top surface of the metal interconnect structure 11 to serve as the buffer material layer 20 .

[0056] By way of example, a silicon dioxide layer may be formed on the substrate surface and the sidewalls and top surface of the metal interconnect structure 11 to serve as the buffer material layer 20 .

[0057] As an example, the process of forming a silicon-containing oxide layer on the substrate surface and the sidewalls and top surface of the metal interconnect structure 11 by using a PECVD process may be specifically performed as follows:

[0058] The structure obtained in step S100 is placed in a PECVD chamber, and a reaction gas is introduced. The reaction gas is evenly distributed in the PECVD chamber and is in full contact with the substrate surface and the side walls and top surfaces of the metal interconnect structure 11. Radio frequency or microwave power is applied to form a plasma from the reaction gas. High-energy electrons in the plasma collide with the reaction gas molecules to excite or ionize them into active substances. These active substances react on the substrate surface and the side walls and top surfaces of the metal interconnect structure 11 to deposit and form a silicon-containing oxide layer.

[0059] For example, the reaction gas may be tetraethoxysilane (Tetraethyl Orthosilicate, TEOS for short) and ozone (O3), and TEOS reacts with ozone in the PECVD chamber to decompose and generate a high-purity silicon dioxide layer.

[0060] The embodiment of the present application does not specifically limit the thickness of the buffer material layer 20 formed in the above step S200. The thickness of the buffer material layer 20 can be adaptively set according to the process requirements in the actual embodiment. In some embodiments, the thickness of the buffer material layer 20 formed in step S200 may range from 300nm to 800nm, but is not limited thereto. Exemplarily, the thickness of the buffer material layer 20 may be 300nm, 450nm, 600nm, 750nm or 800nm, etc.

[0061] See also Figure 4 In step S300 , self-ion implantation is performed on the buffer material layer 20 to transform the buffer material layer 20 into the buffer layer 30 .

[0062] The self-ion implantation in step S300 is performed by implanting ions of the buffer material layer 20 itself. For example, silicon (Si) ions are implanted into the silicon-containing oxide layer. The self-ion implantation process can change the microstructure of the buffer material layer 20, so that the buffer material layer 20 is recrystallized and densified, thereby improving the physical and electrical properties of the buffer material layer 20, and transforming it into a buffer layer 30 with better performance and more density.

[0063] For example, the buffer layer 30 generated by injecting silicon (Si) ions into the silicon-containing oxide layer contains additional silicon elements compared to the silicon-containing oxide layer, and therefore can also be called a silicon-rich oxide layer. Since the silicon-rich oxide layer has a higher silicon content, it can have a higher refractive index and a lower band gap. At the same time, the silicon-rich oxide layer can effectively capture and suppress free fluorine ions. In the HDP-CVD process, the silicon-rich oxide layer can well protect the metal interconnect structure 11 from damage by plasma or ion bombardment.

[0064] The embodiment of the present application does not specifically limit the process conditions in the process of self-ion implantation of the buffer material layer 20 in step S300. The process conditions include substrate temperature, ion implantation energy, and ion implantation dose range.

[0065] In some embodiments, when the buffer material layer 20 is self-ion implanted, the substrate temperature range may include 25° C. to 50° C., but is not limited thereto. For example, when the buffer material layer 20 is self-ion implanted, the substrate temperature may be 25° C., 30° C., 40° C., 45° C., or 50° C., etc.

[0066] In the above preparation method, since the substrate temperature is controlled within a relatively low range (25°C to 50°C), the lattice structure of the substrate is subjected to less thermal stress, thereby effectively reducing the lattice dislocations and damage generated during the ion implantation process, which is beneficial to maintaining the structural integrity of the buffer material layer 20, avoiding excessive accumulation of lattice defects, and thereby improving the quality of the resulting buffer layer 30.

[0067] In addition, controlling the substrate temperature within a lower range (25°C to 50°C) is also beneficial for controlling the kinetic energy of ions, ensuring a more uniform distribution of ions in the buffer material layer 20. Uniform ion distribution is essential for forming a buffer layer 30 with stable performance, which helps the buffer layer 30 to play a better protective role in subsequent process steps.

[0068] In some embodiments, when the buffer material layer 20 is self-ion implanted, the ion implantation energy range may include 20KeV to 70KeV, but is not limited thereto. For example, when the buffer material layer 20 is self-ion implanted, the ion implantation energy may be 20KeV, 30KeV, 50KeV, 60KeV or 70KeV, etc.

[0069] In the above preparation method, the ion implantation energy is controlled between 20KeV and 70KeV, which can ensure that the ions have sufficient kinetic energy to overcome the potential barrier, so that they are accurately implanted into the appropriate depth of the buffer material layer 20, so that they are effectively transformed into the buffer layer 30. And under the premise of ensuring the good performance of the buffer layer 30, it is avoided that excessive ion implantation energy causes serious lattice dislocation or damage to the buffer material layer 20, which is conducive to improving the stability of the semiconductor structure and the production yield.

[0070] In some embodiments, when the buffer material layer 20 is self-ion implanted, the ion implantation dose range includes 1×10 15 cm -2 ~1×10 17 cm -2 For example, the ion implantation dose when the buffer material layer 20 is implanted with ions may be 1×10 15 cm -2 , 0.5×10 16 cm -2 , 1×10 16 cm -2 , 0.5×10 17 cm -2 or 1×10 17 cm -2 etc.

[0071] In the above preparation method, the ion implantation dose range is controlled within 1×10 15 cm -2 ~1×10 17 cm -2 In between, it can be ensured that a sufficient number of ions are injected into the buffer material layer, thereby effectively transforming the buffer material layer 20 into the buffer layer 30. And under the premise of ensuring good performance of the buffer layer 30, excessive lattice damage or other adverse effects caused by excessive ion implantation dose are avoided, which is conducive to improving the stability of the semiconductor structure and the production yield.

[0072] During the aforementioned self-ion implantation process, defects such as dislocations, vacancies, and interstitial atoms may be generated in the lattice of the buffer material layer 20 .

[0073] Considering this, in some embodiments, after the buffer material layer 20 has been transformed into the buffer layer 30 , the buffer layer 30 may also be annealed.

[0074] In the above preparation method, by annealing the buffer layer 30, defects introduced during the ion implantation process can be repaired, and defects existing on the buffer layer 30 can be healed and reorganized, thereby optimizing the structural integrity and quality of the buffer layer 30. Annealing the buffer layer 30 can also promote the uniform distribution of the implanted ions in the buffer layer 30, eliminate local ion-rich areas, and thus obtain a buffer layer 30 with better consistency and uniformity.

[0075] In addition, annealing the buffer layer 30 can also make the surface of the buffer layer 30 clearer and smoother through further reaction, improve the interface quality, and help provide a good foundation for subsequent process flows.

[0076] The embodiment of the present application does not specifically limit the process conditions during the annealing of the buffer layer 30. The process conditions include, for example, the annealing temperature and the annealing time.

[0077] In some embodiments, when annealing the buffer layer 30, the annealing temperature range may include 300°C to 500°C, but is not limited thereto. For example, when annealing the buffer layer 30, the annealing temperature may be 300°C, 350°C, 400°C, 450°C or 500°C, etc.

[0078] In the above preparation method, the annealing temperature is controlled within the range of 300°C to 500°C, which can provide sufficient thermal energy to activate the injected ions, further embedding them into the lattice position, while promoting the uniform distribution and diffusion of ions in the buffer layer 30, thereby improving the stability of the buffer layer 30.

[0079] If the annealing temperature is too low, the defects may not be completely repaired, while if the annealing temperature is too high, other thermal stresses or phase changes of the buffer material may be induced. The above preparation method optimizes the process stability and reliability while ensuring the quality and performance of the buffer layer 30 by controlling the annealing temperature within the range of 300°C to 500°C, thereby avoiding unnecessary material damage and process risks.

[0080] In some embodiments, when annealing the buffer layer 30, the annealing time ranges from 50 minutes to 70 minutes, but is not limited thereto. For example, when annealing the buffer layer 30, the annealing time can be 50 minutes, 55 minutes, 60 minutes, 65 minutes or 70 minutes, etc.

[0081] In the above preparation method, the annealing time is controlled within the range of 50 minutes to 70 minutes, which can ensure that the injected ions have enough time to be fully activated and occupy appropriate lattice positions.

[0082] Too short an annealing time may lead to insufficient ion activation, affecting the performance of the buffer layer 30, while too long an annealing time may lead to degradation of material properties, such as causing grain growth, interface oxidation or unnecessary material phase change. The above preparation method optimizes process stability and reliability while ensuring the quality and performance of the buffer layer 30 by controlling the annealing time within the range of 50 minutes to 70 minutes, thereby avoiding unnecessary material damage and process risks.

[0083] As an example, the process of annealing the buffer layer 30 may be specifically performed as follows:

[0084] The structure obtained in step S300 is placed in a furnace tube for annealing process; the temperature is started to rise, and when the process temperature reaches the annealing temperature (for example, 300°C to 500°C), the structure obtained in step S300 is subjected to constant temperature annealing treatment at the current temperature for a preset annealing time (for example, 50 minutes to 70 minutes); after the annealing is completed, the temperature in the furnace tube does not drop immediately, but is cooled to room temperature with the furnace. Cooling with the furnace can avoid unnecessary thermal stress caused by rapid temperature drop, which is beneficial to maintaining the stability of the semiconductor structure.

[0085] In the process of heating to the annealing temperature (e.g., 300°C to 500°C), it is also important to control the heating rate. Too high a heating rate may cause excessive thermal stress inside the semiconductor structure, resulting in cracks or other defects; while too low a heating rate will increase process time and cost.

[0086] Considering this, in some embodiments, at the beginning of annealing, the process temperature can be controlled to gradually increase at a heating rate of 5°C to 20°C per minute. In this way, a moderate heating rate can avoid excessive thermal stress inside the semiconductor structure due to too fast a heating rate, causing cracks or other defects, while ensuring annealing efficiency and avoiding an increase in process time or cost.

[0087] In addition, in some embodiments, an inert gas atmosphere may be provided during annealing of the buffer layer 30. Introducing an inert gas during the annealing process can effectively prevent oxidation, reduce the introduction of impurities, repair crystal defects, and improve annealing uniformity, thereby obtaining a buffer layer 30 of better quality.

[0088] As an example, the inert gas atmosphere provided may include argon, but is not limited thereto. Compared to nitrogen, argon is more chemically inert and will hardly react with other materials at high temperatures, which can effectively ensure the purity of the annealing environment. Compared to helium, argon is easy to obtain and has a lower cost, making it more economical. Choosing argon for the inert gas atmosphere can be both cost-effective and chemically inert, and no special modification of existing equipment is required, so that the preparation method can have a wide range of equipment compatibility.

[0089] As described above, the method for preparing the semiconductor structure is applied before a chemical vapor deposition process, for example, before a HDP-CVD process.

[0090] The technical effect of the preparation method will be further described below in conjunction with an embodiment in which the preparation method is applied to form an isolation dielectric layer 40 between adjacent metal interconnect structures 11 using a HDP-CVD process.

[0091] See also Figure 5 An isolation dielectric layer 40 may be formed between adjacent metal interconnect structures 11 to achieve electrical isolation between adjacent metal interconnect structures 11. Exemplarily, the constituent material of the isolation dielectric layer 40 may include but is not limited to a low dielectric constant material, which has high resistivity and low conductivity, and can effectively prevent current leakage and ensure electrical isolation between the metal interconnect structures 11.

[0092] In some embodiments, an HDP-CVD process is used to form an isolation dielectric layer 40 between adjacent metal interconnect structures 11. The HDP-CVD process generates a high-quality isolation dielectric layer 40 by performing chemical vapor deposition in a plasma environment. The high-energy ions in the plasma environment sputter the deposited material, and this sputtering effect can prevent the isolation dielectric material from accumulating too much on the top of the metal interconnect structure 11, thereby achieving uniform distribution of the isolation dielectric material.

[0093] During the HDP-CVD process, the material of the metal interconnect structure 11 is easily bombarded by high-energy plasma, resulting in plasma damage. However, by adopting the method for preparing the semiconductor structure provided by the present application, a buffer layer 30 can be formed in advance on the substrate surface and the sidewalls and top surfaces of the metal interconnect structure 11. The buffer layer 30 can serve as a protective barrier to protect the metal interconnect structure 11 during the subsequent HDP-CVD process, slowing down the direct impact of plasma on the material of the metal interconnect structure 11, preventing physical damage to the surface of the metal interconnect structure 11 material, and avoiding degradation of the electrical performance of the metal interconnect structure 11.

[0094] Based on the same inventive concept, the present application also provides a semiconductor structure. Figure 5 The semiconductor structure is prepared by the method for preparing the semiconductor structure provided in any of the above embodiments. Therefore, the technical effects that can be achieved by the above preparation methods can also be achieved by the semiconductor structure, and will not be described in detail here.

[0095] Those skilled in the art will understand that Figure 5 The structure shown in the figure is only a schematic diagram of a part of the structure related to the scheme of the present application. The specific semiconductor structure may include more or less structures than those shown in the figure, or combine certain structures, or have a different structural arrangement.

[0096] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0097] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: Before being applied to a chemical vapor deposition process, the method for preparing the semiconductor structure includes: Providing a substrate, on which a metal interconnection structure is formed; forming a buffer material layer on the substrate surface and the sidewalls and top surface of the metal interconnect structure; The buffer material layer is self-ion-implanted to transform the buffer material layer into a buffer layer.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: The buffer material layer includes a silicon-containing oxide layer.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that: The step of forming a buffer material layer on the substrate surface and the sidewalls and top surface of the metal interconnect structure comprises: The silicon-containing oxide layer is formed on the substrate surface and the sidewalls and top surface of the metal interconnect structure by a plasma enhanced chemical vapor deposition process to serve as the buffer material layer.

4. The method for preparing a semiconductor structure according to claim 2, characterized in that: The thickness of the buffer material layer ranges from 300 nm to 800 nm.

5. The method for preparing a semiconductor structure according to claim 1, characterized in that: When the buffer material layer is subjected to the self-ion implantation, the substrate temperature ranges from 25°C to 50°C.

6. The method for preparing a semiconductor structure according to claim 1, characterized in that: When the buffer material layer is subjected to the self-ion implantation, the ion implantation energy range includes 20 KeV to 70 KeV.

7. The method for preparing a semiconductor structure according to claim 1, characterized in that: When the buffer material layer is subjected to the self-ion implantation, the ion implantation dose range includes 1×10 15 cm -2 ~1×10 17 cm -2 .

8. The method for preparing a semiconductor structure according to claim 1, characterized in that: After the buffer material layer is transformed into the buffer layer, the method for preparing the semiconductor structure further includes: The buffer layer is annealed.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that: When the buffer layer is annealed, the annealing temperature ranges from 300° C. to 500° C., and / or the annealing time ranges from 50 minutes to 70 minutes.

10. A semiconductor structure, characterized in that: The semiconductor structure is prepared by the method for preparing a semiconductor structure according to any one of claims 1 to 9.

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