Packaging structure and semiconductor structure

Abstract

The invention provides a packaging structure and a semiconductor structure, and the structure comprises a packaging substrate, and the surface of the packaging substrate is provided with a signal pin array. The signal pin array comprises a plurality of clock pins used for carrying clock signals and a plurality of command address pins used for carrying command address signals, the clock pins are arranged in the first direction, and each clock pin is adjacent to one command address pin in the second direction.

Description

Technical Field

[0001] The present disclosure relates to the semiconductor field, and in particular to a packaging structure and a semiconductor structure. Background Art

[0002] An important purpose of packaging a microelectronic device (such as a chip) is to connect the device to a higher-level package of an electronic system. One aspect of packaging is to convert signals from relatively small features of a die (e.g., bonding pads or rewired bonding pads) to larger and more widely spaced connection locations of the next higher-level package (e.g., a circuit board). Specifically, the various input / output signals involved in the chip are packaged as an array of signal pins, and the pattern and spacing of the signal pin array are usually specified by industry-wide (i.e., JEDEC) standards. However, the update cycle of various types of chip upgrades is getting smaller and smaller, so it is necessary to provide a packaging structure that meets the needs of the new generation of memory chips. Summary of the invention

[0003] The present disclosure provides a packaging structure and a semiconductor structure.

[0004] The technical solution of the present disclosure is achieved as follows:

[0005] In a first aspect, an embodiment of the present disclosure provides a packaging structure, including a packaging substrate, a surface of which is provided with a signal pin array; the signal pin array includes a plurality of clock pins for carrying clock signals and a plurality of command address pins for carrying command address signals, the plurality of clock pins are arranged along a first direction, and each clock pin is adjacent to a command address pin along a second direction; wherein the first direction is a column extension direction of the signal pin array, and the second direction is a row extension direction of the signal pin array.

[0006] In some embodiments, the signal pin array further includes a plurality of chip select pins for carrying chip select signals; the plurality of chip select pins are arranged along a first direction; and each chip select pin is adjacent to a command address pin along a second direction.

[0007] In some embodiments, the signal pin array also includes multiple chip select pins for carrying chip select signals and multiple data pins for carrying data signals; one of the chip select pins is also adjacent to one data pin along the first direction; one of the clock pins is also adjacent to another command address pin along the first direction.

[0008] In some embodiments, the signal pin array also includes multiple chip select pins for carrying chip select signals and multiple data pins for carrying data signals; the signal pin array is divided into a first edge row, a data transmission area, a control transmission area and a second edge row in sequence along a first direction; multiple data pins are all located in the data transmission area, and any two data pins are not adjacent in a straight line; multiple command address pins, multiple clock pins and multiple chip select pins are all located in the control transmission area; and, in the first direction, at most 3 of the command address pins are allowed to be arranged continuously; in the second direction, at most 2 of the command address signals are allowed to be arranged continuously.

[0009] In some embodiments, the signal pin array is divided into a first longitudinal region, a center column, and a second longitudinal region in sequence along the second direction, the number of signal pins in the first longitudinal region is the same as the number of signal pins in the second longitudinal region, and the pins in the center column are removed; multiple data pins are located in the non-edge column of the first longitudinal region and the non-edge column of the second longitudinal region, and the data pins in the first longitudinal region are symmetrical with the data pins in the second longitudinal region about the center column; multiple command address pins are located in a portion of the first longitudinal region close to the center column and a portion of the second longitudinal region close to the center column, and the command address pins in the first longitudinal region are symmetrical with the command address pins in the second longitudinal region about the center column.

[0010] In some embodiments, a plurality of chip select pins are located in a first longitudinal region, and the chip select pins are located on a side of adjacent command address pins away from a central column; a plurality of clock signal pins are located in a second longitudinal region and adjacent to the central column.

[0011] In some embodiments, the data transmission area is divided into a first transmission area and a second transmission area along a first direction, the total number of pins in the first transmission area is greater than the total number of pins in the second transmission area, and the number of data pins in the first transmission area is the same as the number of data pins in the second transmission area; the data pins in the first transmission area are used to transmit high-order data signals, and the data pins in the second transmission area are used to transmit low-order data signals; or, the data pins in the first transmission area are used to transmit low-order data signals, and the data pins in the second transmission area are used to transmit high-order data signals.

[0012] In some embodiments, the signal pin array also includes two pairs of data selection pins carrying data selection signals, the first pair of data selection pins is located in the first transmission area, the second pair of data selection pins is located in the second transmission area, and the data selection pins are adjacent to the center column; the two pins of each pair of data selection pins are adjacent along the first direction, and the first pair of data selection pins and the second pair of data selection pins are not adjacent along the first direction; wherein, the first pin of each pair of data selection pins is linearly adjacent to at least one data pin, and the second pin of each pair of data selection pins is not linearly adjacent to any data pin.

[0013] In some embodiments, the data transmission area is also distributed with two pairs of first auxiliary control pins, the first pair of first auxiliary control pins are symmetrical with the first pair of data selection pins about the center column, and the second pair of first auxiliary control pins are symmetrical with the second pair of data selection pins about the center column; other pins in the data transmission area are power pins or ground pins.

[0014] In some embodiments, one pin of each pair of first auxiliary control pins is used to carry a mask control signal or a terminal data selection signal, and the other pin of each pair of first auxiliary control pins is used to transmit a ground signal or is used as a reserved signal pin.

[0015] In some embodiments, the control transmission area is also distributed with multiple second auxiliary control pins, multiple third auxiliary control pins, multiple fourth auxiliary control pins, a fifth auxiliary control pin and a sixth auxiliary control pin, and the multiple second auxiliary control pins and the multiple chip select pins are symmetrical about the center column; the multiple third auxiliary control pins and the multiple fourth auxiliary control pins are symmetrical about the center column, a third auxiliary control pin, a chip select pin and a command address pin are arranged continuously along the second direction, and a command address pin, a second auxiliary control pin and a fourth auxiliary control pin are arranged continuously along the second direction; the fifth auxiliary control pin and the sixth auxiliary control pin are symmetrical about the center column, the fifth auxiliary control pin and the third auxiliary control pin are in the same column, and the fifth auxiliary control pin is not adjacent to the third auxiliary control pin; the sixth auxiliary control pin and the fourth auxiliary control pin are in the same column, and the sixth auxiliary control pin is not adjacent to the fourth auxiliary control pin; other pins in the control transmission area are power pins or ground pins.

[0016] In some embodiments, the first edge row is distributed with local data pins carrying local data signals and local data selection pins carrying local data selection signals, and the local data pins and the local selection data pins are symmetrical about the center column, the local data pin is adjacent to a data pin along the first direction, and the local data selection pin is adjacent to a data pin along the first direction; the first edge row is also distributed with a seventh auxiliary control pin, the seventh auxiliary control pin is adjacent to the center column, and the seventh auxiliary control pin is adjacent to the data pin along the first direction; the other pins in the first edge row and the second edge row are all power pins or ground pins.

[0017] In some embodiments, there is at least one second auxiliary control pin for carrying a test mode enable signal, and at least one second auxiliary control pin is used as a reserved signal pin; there is at least one third auxiliary control pin for carrying a mirror mode enable signal, and at least one third auxiliary control pin is used to carry a verification error signal; there is at least one fourth auxiliary control pin for carrying a first protocol signal, and at least one fourth auxiliary control pin is used to carry a second protocol signal; a fifth auxiliary control pin is used to carry a termination signal, and a sixth auxiliary control pin is used to carry a reset signal; and a seventh auxiliary control pin is used to be a calibration pin for carrying an impedance calibration signal.

[0018] In some embodiments, the signal pin array has 14 rows, the first longitudinal region has 4 columns, and the second longitudinal region has 4 columns; the packaging form of each pin of the signal pin array is a ball grid, and in the first direction, the distance between the center points of two adjacent ball grids is a first value, and in the first direction, the distance between the center points of two adjacent ball grids is a second value, and the first value is smaller than the second value.

[0019] In a second aspect, an embodiment of the present disclosure provides a semiconductor structure, including a packaging structure and a chip as in the first aspect; wherein the data bit width of the chip is 4 bits, 8 bits or 16 bits.

[0020] The embodiments of the present disclosure provide a packaging structure and a semiconductor structure that are compatible with chips of different specifications, have strong adaptability, and have a small overall area. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A schematic diagram of a packaging structure provided by an embodiment of the present disclosure;

[0022] Figure 2 A schematic diagram of another packaging structure provided by an embodiment of the present disclosure;

[0023] Figure 3 A schematic diagram of a signal pin array provided in an embodiment of the present disclosure Figure 1 ;

[0024] Figure 4 A schematic diagram of a signal pin array provided in an embodiment of the present disclosure Figure 2 ;

[0025] Figure 5 A schematic diagram of a signal pin array provided in an embodiment of the present disclosure Figure 3 ;

[0026] Figure 6 A schematic diagram of a signal pin array provided in an embodiment of the present disclosure Figure 4 ;

[0027] Figure 7 is a schematic diagram of a signal pin array;

[0028] Figure 8 A schematic diagram of another signal pin array provided in an embodiment of the present disclosure;

[0029] Fig. 9 A schematic structural diagram of a semiconductor structure provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0030] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It is understood that the specific embodiments described herein are only used to explain the relevant application, not to limit the application. It should also be noted that, for the convenience of description, only the parts related to the relevant application are shown in the drawings. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by technicians in the technical field of the present disclosure. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure. In the following description, "some embodiments" are involved, which describe a subset of all possible embodiments, but it is understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict. It should be noted that the terms "first\second\third" involved in the embodiments of the present disclosure are only used to distinguish similar objects, and do not represent a specific order for the objects. It is understandable that "first\second\third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that shown or described.

[0031] Static Random-Access Memory (SRAM) semiconductor chip;

[0032] Dynamic Random Access Memory (DRAM) semiconductor chip;

[0033] Synchronous Dynamic Random Access Memory (SDRAM) semiconductor chip;

[0034] Double Data Rate SDRAM (DDR);

[0035] Fifth generation DDR (DDR5);

[0036] Sixth generation DDR (DDR6);

[0037] Two-wire bidirectional serial bus protocol (I3C);

[0038] Printed Circuit Board (PCB).

[0039] Before introducing the embodiments of the present disclosure, the three directions that may be used to describe the three-dimensional structure of the plane involved in the following embodiments are defined first. Taking the Cartesian coordinate system as an example, the three directions may include the X-axis, Y-axis and Z-axis directions (not involved in the embodiments of the present disclosure). The packaging structure may include a top surface on the front side and a bottom surface on the back side opposite to the front side; ignoring the flatness of the top surface and the bottom surface, the direction that intersects (for example, is perpendicular to) the top surface and the bottom surface of the packaging structure is defined as the third direction. In the directions of the top surface and the bottom surface of the packaging structure (that is, the plane where the packaging structure is located), two directions that intersect with each other are defined. For example, the column extension direction of the signal pin array can be defined as the first direction, and the row extension direction of the signal pin array can be defined as the second direction. The plane direction of the packaging structure can be determined based on the first direction and the second direction. In the embodiments of the present disclosure, the first direction and the second direction may be perpendicular to each other. In other embodiments, the first direction and the second direction may not be perpendicular.

[0040] In addition, the term "linearly adjacent" used herein in conjunction with the signal pin array means and includes the pins directly above, directly below, directly to the left, and directly to the right of a given pin when the signal pin array is parallel to the plane of the drawing; the term "diagonally arranged" used herein in conjunction with the signal pin array means and includes the pins directly to the upper right, lower right, upper left, and lower left of a given pin when the signal pin array is parallel to the plane of the drawing; the term "around the pin" used herein in conjunction with the signal pin array means and includes the pins directly above, directly below, directly to the left, directly to the right, upper right, lower right, upper left, and lower left of a given pin when the signal pin array is parallel to the plane of the drawing. The term "pin A is adjacent to pin B along a first direction" used herein in conjunction with the signal pin array only includes that pin A and pin B are adjacent when the signal pin array is parallel to the plane of the drawing, and pin A is directly above or directly below pin B. The term "pin A and pin B are adjacent along a second direction" used herein in conjunction with the signal pin array only includes that pin A and pin B are adjacent when the signal pin array is parallel to the plane of the drawing, and pin A is directly to the left or directly to the right of pin B.

[0041] In particular, the illustrations presented in this disclosure are not meant to be actual views of any particular microelectronic device package, signal pin array, or components thereof, but are merely idealized representations used to describe illustrative embodiments. The drawings are therefore not necessarily to scale.

[0042] Since the subsequent description of the embodiments of the present disclosure involves DDR6 chips with 4-bit data width (X4), 8-bit data width (X8), and 16-bit data width (X16), Table 1 is provided to illustrate the relevant signals and their number involved in the packaging of the above chips.

[0043] Table 1

[0044]

[0045]

[0046]

[0047] In particular, for the X8 chip, the terminal data selection signals tdqs_c and tdqs_t are required, while the X4 chip and the X16 chip do not need them, but the mask flip control signals dmu_n and dml_n are required. In particular, for the same design specification, the terminal data selection signal can share a signal pin with the mask flip control signal, that is, tdqs_c and dmu_n share a pin, and tdqs_t and dml_n share a pin.

[0048] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0049] In one embodiment of the present disclosure, see Figure 1 , which shows a schematic diagram of a packaging structure 10 provided by an embodiment of the present disclosure. Figure 1 As shown, the package structure 10 includes a package substrate 11 , and a signal pin array 20 (or referred to as a ball pin array) is disposed on the surface of the package substrate 11 .

[0050] It should be noted that the package structure 10 provided in the embodiment of the present disclosure can at least be applicable to DDR5 or DDR6, and can simultaneously support DDR5 or DDR6 chips with data bit widths of 4 bits, 8 bits, and 16 bits. Specifically, the DDR chip includes a device substrate, which includes a semiconductor material and a bonding pad coupled to the active surface of the device substrate, the package substrate is fixed to the device substrate, and the aforementioned package substrate 11 is configured to route signals to / from the bonding pad, and the signal pin array 20 is supported on the package substrate 11 and electrically connected thereto. In particular, the distribution position of the signal pin array 20 on the package substrate 11 is only for illustration and does not constitute a limitation. In fact, the surface of the package substrate 11 is not necessarily a completely regular rectangle, and the signal pin array 20 can be distributed in any area of ​​the surface of the package substrate 11.

[0051] In the following description, the first direction is the column extending direction of the signal pin array 20 , and the second direction is the row extending direction of the signal pin array 20 .

[0052] like Figure 1 As shown, the signal pin array 20 includes a plurality of clock pins (201, 202) for carrying clock signals and a plurality of command address pins (201, 202) for carrying command address signals. Figure 1Only a portion, namely 211 and 212, is shown. Multiple clock pins (201 and 202) are arranged along a first direction, and each clock pin is adjacent to a command address pin along a second direction. For example, clock pin 201 is adjacent to command address pin 211 along the second direction, and clock pin 202 is adjacent to command address pin 212 along the second direction.

[0053] That is, a plurality of clock pins are located in the same column and are adjacent to each other, and a clock pin and a command address pin are located in the same row and are adjacent to each other.

[0054] It should be noted that Figure 1 Two clock pins are shown, but there may be more or less in actual scenarios. Figure 1 For example, the clock pin 201 is specifically used to transmit the clock signal ck_t in Table 1, and the clock pin 202 is specifically used to transmit the clock signal ck_c in Table 1. The clock signal ck_t and the clock signal ck_c are a pair of differential signals.

[0055] Thus, in the embodiment of the present disclosure, the clock pin is allowed to be adjacent to the command address pin along the second direction, which can reduce the scale of the signal pin array 20 and save the substrate area. At the same time, since the clock pin is adjacent to the command address pin along the second direction, the time delay of the clock and the address can be better matched, the overall transmission path is closer, the integrity of the signal is improved, and the competitiveness of the overall product is enhanced.

[0056] In some embodiments, Figure 2 As shown, the signal pin array 20 also includes a plurality of chip select pins (231, 232) for carrying chip select signals, and the plurality of chip select pins (231, 232) are arranged along a first direction; each chip select pin is adjacent to a command address pin along a second direction, for example, the chip select pin 231 is adjacent to the command address pin 213 along the second direction.

[0057] That is, a plurality of chip select pins are located in the same column and are adjacent to each other, and a chip select pin and a command address pin are located in the same row and are adjacent to each other.

[0058] It should be noted that Figure 2 Two chip select pins are shown, but there may be more or less in actual scenarios. Figure 2 For example, the chip select pin 231 is specifically used to transmit the chip select signal cs_n[0] in Table 1, and the chip select pin 232 is specifically used to transmit the chip select signal cs_n[1] in Table 1. At most only one of the chip select signal cs_n[0] and the chip select signal cs_n[1] is valid.

[0059] Thus, in the disclosed embodiment, the chip select pins are allowed to be adjacent to the command address pins along the second direction, which can compress the number of rows occupied by the address signals in the signal pin array 20, further save space, and better match the timing between the clock and address signals.

[0060] In some embodiments, Figure 2 As shown, the signal pin array 20 also includes a plurality of data pins ( Figure 2 Only one is shown, namely 241); one of the chip select pins 232 is also adjacent to one data pin 241 along the first direction; one of the clock pins 202 is also adjacent to another command address pin 215 along the first direction.

[0061] Thus, in the disclosed embodiment, the chip select pin is allowed to be adjacent to the command address pin along the second direction, and the chip select pin is allowed to be adjacent to the data pin along the first direction; at the same time, the clock pin and the command address pin are allowed to be adjacent to each other in both the first direction and the second direction, so that the signal distribution is concentrated under the premise that the signal quality meets the requirements.

[0062] For ease of explanation, see Figure 3 , which is a schematic diagram of the arrangement of the signal pin array 20 for the specific application scenario of the DDR6 chip. Figure 3 In the embodiment, the signal pin array 20 has 14 rows (rows are numbered a to p) x 11 columns (columns are numbered 1 to 11), including 16 data pins DQ, 14 command address pins CA, 2 clock pins (CK_T and CK_C), and 2 chip select pins (CS_N[0] and CS_N[1]). It should be understood that Figure 3 This is only one specific implementation of the present disclosure. Without violating the following text description, the scale of the signal pin array 20, the number of different types of signals, and the detailed arrangement of each signal can be adaptively adjusted.

[0063] In some embodiments, Figure 3 As shown, the signal pin array 20 is divided into a first edge row, a data transmission area, a control transmission area, and a second edge row in sequence along a first direction; a plurality of data pins DQ are all located in the data transmission area, and any two data pins DQ are not adjacent in a straight line; a plurality of command address pins CA, a plurality of clock pins (CK_T and CK_C), and a plurality of chip select pins (CS_N[0] and CS_N[1]) are all located in the control transmission area.

[0064] It should be noted that for a data pin DQ, another data pin DQ is not allowed to be arranged directly above, directly below, directly to the left, or directly to the right; however, another data pin DQ is allowed to be arranged on the upper left, lower left, upper right, or lower right. That is, two data pins DQ can be arranged along a diagonal line, but cannot be adjacent to each other in a straight line, so as to improve the signal distortion problem caused by the superposition of magnetic fields.

[0065] It should be noted that Figure 3 The signal pin array 20 includes 16 data pins DQ in total, which can support chips with 4-bit, 8-bit, and 16-bit data widths. In simple terms, if the package structure 10 is applied to a chip with a 4-bit data width (X4), only 4 of the data pins are enabled, and the remaining 12 data pins are not connected; if the package structure 10 is applied to a chip with an 8-bit data width (X8), only 8 of the data pins are enabled, and the remaining 8 data pins are not connected; if the package structure 10 is applied to a chip with a 16-bit data width (X16), all the data pins are enabled.

[0066] In some embodiments, Figure 3 As shown, the signal pin array 20 is divided into a first longitudinal region, a central column, and a second longitudinal region in sequence along the second direction, and the number of signal pins in the first longitudinal region is the same as the number of signal pins in the second longitudinal region.

[0067] It should be noted that the pins in the center column are removed. That is, after the signal pin array 20 is completed, the pins in the center column need to be removed to facilitate PCB routing. Figure 3 The central column in contains 3 columns, but this is not a limitation and the central column can contain more or fewer columns. In particular, Figure 3 In the figure, the length of each column in the center column (ie, the 5th / 6th / 7th column) along the second direction is shorter, but this is only to save page space. In fact, the length of each column of the signal pin array 20 along the second direction is substantially the same.

[0068] See also Figure 3 , multiple data pins DQ are located in the non-edge columns of the first longitudinal region and the non-edge columns of the second longitudinal region, and the data pins DQ in the first longitudinal region and the data pins DQ in the second longitudinal region are symmetrical about the center column. In this way, the data pins DQ in the first longitudinal region and the second longitudinal region are mirror images of each other, so that vias can be shared when the front and back are designed on the PCB; in addition, the data pins DQ are not set in the first column and the last column (i.e., the edge column), thereby shortening the length of the data pins DQ along the second direction.

[0069] For example, Figure 3As shown, the even-numbered data pins DQ are distributed in columns 2, 3, and 4, and the odd-numbered data pins DQ are distributed in columns 8, 9, and 10. Alternatively, the even-numbered data pins DQ are distributed in columns 8, 9, and 10, and the odd-numbered data pins DQ are distributed in columns 2, 3, and 4.

[0070] See also Figure 3 , multiple command address pins CA are located in the portion of the first longitudinal region close to the center column and the portion of the second longitudinal region close to the center column, and the command address pins CA in the first longitudinal region and the command address pins CA in the second longitudinal region are symmetrical about the center column. In other words, the command address pins CA in the first longitudinal region and the second longitudinal region are mirror images of each other, so that vias can be shared when the front and back are designed on the PCB; in addition, the command address pins CA are not distributed in the first two columns and the last two columns, thereby shortening the length of the command address pins CA along the second direction.

[0071] For example, Figure 3 As shown, the even-numbered command address pins CA are distributed in columns 3 and 4, and the odd-numbered command address pins CA are distributed in columns 9 and 10. Alternatively, the even-numbered command address pins CA are distributed in columns 9 and 10, and the odd-numbered command address pins CA are in columns 3 and 4.

[0072] It should be noted that, in the first direction, at most three command address pins CA are allowed to be arranged continuously; in the second direction, at most two command address pins CA are allowed to be arranged continuously.

[0073] In this way, the data pins DQ are not arranged in a straight line adjacent to each other in the first direction and the second direction, so as to avoid the intensity and degree of overlap in the magnetic field generated by the carried data signal, thereby making the signal have higher quality and fidelity. In addition, the distribution of the command address pins CA is more compact, thereby reducing the area occupied by the overall signal pin array.

[0074] In some embodiments, multiple chip select pins (CS_N[0] and CS_N[1]) are located in the first longitudinal region, and the chip select pins are located on the side of the adjacent command address pins CA away from the center column; multiple clock signal pins are located in the second longitudinal region and adjacent to the center column.

[0075] In this way, multiple clock signal pins (CK_T and CK_C) are adjacent to the center column, which can be located in the 4th column or the 8th column, and the rows of multiple clock signal pins are adjacent, which is convenient for PCB or substrate wiring.

[0076] In some embodiments, see Figure 3The data transmission area is divided into a first transmission area and a second transmission area along a first direction, the total number of pins in the first transmission area is greater than the total number of pins in the second transmission area, and the number of data pins DQ in the first transmission area is the same as the number of data pins DQ in the second transmission area.

[0077] In the first possibility, the data pin DQ in the first transmission area is used to transmit the high-bit data signal (i.e., dqu[7:0] in Table 1), and the data pin DQ in the second transmission area is used to transmit the low-bit data signal (i.e., dql[7:0] in Table 1). At this time, for DDR6 with a 4-bit data width, only 4 data pins in the second transmission area are enabled; for DDR6 with an 8-bit data width, only 8 of the data pins are enabled, and only 8 data pins in the second transmission area are enabled; for DDR6 with a 16-bit data width, all data pins are enabled.

[0078] In the second possibility, the data pin DQ in the first transmission area is used to transmit the low-bit data signal (i.e., dql[7:0] in Table 1), and the data pin DQ in the second transmission area is used to transmit the high-bit data signal (i.e., dqu[7:0] in Table 1). At this time, for DDR6 with a 4-bit data width, only 4 data pins in the first transmission area are enabled; for DDR6 with an 8-bit data width, only 8 of the data pins are enabled, and only 8 data pins in the first transmission area are enabled; for DDR6 with a 16-bit data width, all data pins are enabled.

[0079] In this way, in the embodiment of the present disclosure, the transmission area of ​​the high-bit data signal and the transmission area of ​​the low-bit data signal are independent of each other, and the layout is more reasonable.

[0080] In some embodiments, Figure 3 As shown, the signal pin array 20 also includes two pairs of data strobe pins for carrying data strobe signals; the first pair of data strobe pins is identified as DQS0_T and DQS0_C, which transmit a pair of differential signals; the second pair of data strobe pins is identified as DQS1_T and DQS1_C, which also transmit a pair of differential signals. In other words, one pair of data strobe pins is used to transmit dqsl_t and dqsl_c in Table 1, and the other pair of data strobe pins is used to transmit dqsu_t and dqsu_c in Table 1.

[0081] The first pair of data strobe pins (DQS0_T, DQS0_C) are both located in the first transmission area, the second pair of data strobe pins (DQS1_T, DQS1_C) are located in the second transmission area, and all data strobe pins (DQS0_T, DQS0_C, DQS1_T, DQS1_C) are adjacent to the center column; the two pins of each pair of data strobe pins are adjacent along the first direction, that is, the data strobe pin DQS0_T and the data strobe pin DQS0_C are adjacent along the first direction, and the data strobe pin DQS1_T and the data strobe pin DQS1_C are adjacent along the first direction. The first pair of data strobe pins and the second pair of data strobe pins are not adjacent along the first direction; here, not adjacent means that there is at least one pin between the "first pair of data strobe pins" and the "second pair of data strobe pins". For example, in Figure 3 In the example, the data strobe pins DQS0_C and DQS1_T are separated by a power pin VDDQ.

[0082] In this way, each pair of data strobe pins can be located in the 4th column or the 8th column, and the rows where the two pins in each pair of data strobe pins are located are adjacent, thereby facilitating PCB or substrate wiring.

[0083] It should be noted that the first pin of each pair of data strobe pins is linearly adjacent to at least one data pin DQ, that is, one data pin DQ is respectively distributed directly above and directly to the left of the data strobe pin DQS0_T, and one data pin DQ is distributed directly to the left of the data strobe pin DQS1_C. At the same time, the second pin of each pair of data strobe pins is not linearly adjacent to any data pin DQ. Here, "not linearly adjacent" means that the data pin DQ is not allowed to be distributed directly above, directly below, directly to the left, and directly to the right of "the other pin of each pair of data strobe pins".

[0084] It should also be noted that in Figure 3 In some embodiments, all data strobe pins are in the same column. Figure 4 , the first pair of data strobe pins (DQS0_T, DQS0_C) are located in a column close to the center column in the first longitudinal region, and the second pair of data strobe pins (DQS0_T, DQS0_C) are located in a column close to the center column in the second longitudinal region. In some other embodiments, the first pair of data strobe pins (DQS0_T, DQS0_C) are located in a column close to the center column in the second longitudinal region, and the second pair of data strobe pins (DQS0_T, DQS0_C) are located in a column close to the center column in the first longitudinal region.

[0085] In some embodiments, please refer to Figure 3 or Figure 4The data transmission area is also provided with two pairs of first auxiliary control pins (301-304), the first pair of first auxiliary control pins (301, 302) and the first pair of data selection pins (DQS0_T, DQS0_C) are symmetrical about the center column, and the second pair of first auxiliary control pins (301, 302) and the second pair of data selection pins (DQS1_T, DQS1_C) are symmetrical about the center column; the other pins in the data transmission area are all power pins or ground pins VSS.

[0086] It should be noted that, depending on the function and / or voltage value, the power pins are marked as VDD, VDDQ, and VPP. In particular, each data pin DQ is surrounded by at least one ground pin and one power pin. Here, "surrounding the data pin DQ" includes the pins adjacent to the data pin DQ directly above, directly below, directly to the left, directly to the right, upper left, lower left, upper right, and lower right, which not only realizes the isolation function but also facilitates the generation of data signals.

[0087] In some embodiments, Figure 3 or Figure 4 As shown, the control transmission area is also distributed with multiple second auxiliary control pins (305, 306), multiple third auxiliary control pins (307, 308), multiple fourth auxiliary control pins (309, 310), a fifth auxiliary control pin 311 and a sixth auxiliary control pin 312.

[0088] First, the plurality of second auxiliary control pins (305, 306) and the plurality of chip select pins (CS_N[0] and CS_N[1]) are symmetrical about the center column.

[0089] Secondly, a plurality of third auxiliary control pins (307, 308) and a plurality of fourth auxiliary control pins (309, 310) are symmetrical about the central column, a third auxiliary control pin, a chip select pin and a command address pin CA are arranged continuously along the second direction, and a command address pin CA, a second auxiliary control pin and a fourth auxiliary control pin are arranged continuously along the second direction; Figure 3 As shown, the third auxiliary control pin 307, the chip select pin CS_N[0] and one command address pin CA are arranged continuously along the second direction, and the third auxiliary control pin 308, the chip select pin CS_N[1] and one command address pin CA are arranged continuously along the second direction; at the same time, one command address pin CA, the second auxiliary control pin 305 and the fourth auxiliary control pin 309 are arranged continuously along the second direction, and one command address pin CA, the second auxiliary control pin 306 and the fourth auxiliary control pin 310 are arranged continuously along the second direction.

[0090] Finally, the fifth auxiliary control pin 311 and the sixth auxiliary control pin 312 are symmetrical about the central column, the fifth auxiliary control pin 311 and the third auxiliary control pin (307 and 308) are located in the same column, and the fifth auxiliary control pin 311 and the third auxiliary control pin (307 and 308) are not adjacent; the sixth auxiliary control pin 312 and the fourth auxiliary control pin (309 and 310) are located in the same column, and the sixth auxiliary control pin 312 and the fourth auxiliary control pin (309 and 310) are not adjacent;

[0091] The other pins in the control transmission area are power pins or ground pins, that is, the other pins in the control transmission area are either power pins or ground pins.

[0092] In some embodiments, see Figure 5 , the first edge row is also distributed with a local data pin LBDQ carrying a local data signal lbdq and a local data strobe pin LBDQS carrying a local data strobe signal lbdqs, and the local data pin LBDQ and the local strobe data pin LBDQS are symmetrical about the central column, the local data pin LBDQ is adjacent to a data pin DQ along the first direction, and the local data strobe pin LBDQS is adjacent to a data pin DQ along the first direction;

[0093] The first edge row is also distributed with a seventh auxiliary control pin 313, which is adjacent to the center column, and the seventh auxiliary control pin 313 is adjacent to the data pin DQ along the first direction; the other pins in the first edge row and the second edge row are all power pins or ground pins, and in particular, the power pin VPP coincides with another power pin VPP after being rotated 180 degrees along the center of the signal array.

[0094] It should be noted that in Figure 5 In the embodiment, the seventh auxiliary control pin 313 and the local data selection pin LBDQS are located on the same side of the center column; in other embodiments, the seventh auxiliary control pin 313 and the local data pin LBDQ may also be located on the same side of the center column, and the position of the power pin VPP needs to be adjusted accordingly.

[0095] For the 13 auxiliary control pins mentioned above, they are relatively flexibly used to transmit the following signals: mask control signal (dml, dmu) or terminal data selection signal (tdqs_t, tdqs_c), test mode enable signal ten (used to control the chip to enter / not enter the test mode), reserved signal rfu (each manufacturer can customize its use), mirror mode enable signal mir (used to control the chip to enter / not enter the mirror mode), check error signal (used to prompt that an error is detected during the cyclic redundancy check operation) alert_n, the first protocol signal msda (I3C related signal), the second protocol signal mscl (I3C related signal), termination signal ca_odt, reset signal reset, impedance calibration signal zq.

[0096] It should be noted that the above signals can be transmitted relatively flexibly using any auxiliary control pins, which mainly depends on the structure of the internal circuit and the routing requirements. The following is only provided for illustration and does not constitute a specific limitation.

[0097] In this way, the signal pin array 20 can support the transmission of all signals in Table 1, thereby being compatible with X4, X8 and X16 chips.

[0098] In a specific embodiment, please refer to Figure 5 , one of the pins DM of each pair of first auxiliary control pins is used to carry the mask control signal (dml, dmu) or the terminal data selection signal (tdqs_t, tdqs_c), and the other pin (VSS, RFU) of each pair of first auxiliary control pins is used to transmit the ground signal vss or be used as a reserved signal pin; there is at least one second auxiliary control pin TEN for carrying the test mode enable signal ten, and there is at least one second auxiliary control pin RFU used as a reserved signal pin; there is at least one third auxiliary control pin MIR for carrying the mirror mode enable signal mir, and there is at least one third auxiliary control pin ALERT_n for carrying the check error signal alert_n; there is at least one fourth auxiliary control pin MSDA for carrying the first protocol signal msda, and there is at least one fourth auxiliary control pin MSCL for carrying the second protocol signal mscl; the fifth auxiliary control pin CA_ODT is used to carry the termination signal ca_odt, the sixth auxiliary control pin Reset is used to carry the reset signal reset, and the seventh auxiliary control pin ZQ is used to carry the impedance calibration signal zq.

[0099] In this way, some signals that are not sensitive to length can be preferentially transmitted through auxiliary control signals in edge rows or edge columns, and the layout is reasonable.

[0100] In another embodiment, if Figure 6As shown, one of the pins DM of each pair of first auxiliary control pins is used to carry the mask control signal (dml, dmu) or the terminal data selection signal (tdqs_t, tdqs_c), and the other pin (VSS, RFU) of each pair of first auxiliary control pins is used to transmit the ground signal or be used as a reserved signal pin; there is at least one second auxiliary control pin TEN carrying the mirror mode enable signal MIR, and there is at least one second auxiliary control pin RFU used as a reserved signal pin; there is at least one third auxiliary control pin MSDA for carrying the first protocol signal msda,, and there is at least one third auxiliary control pin MSCL for carrying the second protocol signal mscl; there is at least one fourth auxiliary control pin ALERT_n for carrying the check error signal alert_n, and there is at least one fourth auxiliary control pin TEN for carrying the test mode enable signal ten; the fifth auxiliary control pin ZQ is used to carry the impedance calibration signal zq, the sixth auxiliary control pin CA_ODT is used to carry the termination signal ca_odt, and the seventh auxiliary control pin RESET is used to carry the reset signal reset.

[0101] In addition, in the embodiment of the present disclosure, the ground pin VSS and the power pin (VDD / VDDQ) need to be staggered and evenly distributed. In particular, the ground pin VSS is not adjacent in the first direction, and the power pin (VDD / VDDQ) is not adjacent in the first direction.

[0102] In some embodiments, the signal pin array 20 has 14 rows, the first longitudinal region has 4 columns, and the second longitudinal region has 4 columns; the packaging form of each pin of the signal pin array 20 is a ball grid, and in the first direction, the distance between the center points of two adjacent ball grids is a first value, and in the first direction, the distance between the center points of two adjacent ball grids is a second value, and the first value is smaller than the second value.

[0103] like Figure 3 to Figure 6 As shown, the center column has 3 columns, so the scale of the signal pin array 20 is 14 rows × 11 columns, that is, the number of pins in the first direction is more, and the number of pins in the second direction is less, so the distance between the center points of two adjacent ball grids in the first direction can be reduced, thereby reducing the size of the signal pin array 20 as a whole.

[0104] In a specific embodiment, the first value is 750 micrometers and the second value is 800 micrometers, so that the size of the entire signal pin array 20 is 10 mm×11 mm, and a total of 14×8=112 pins are provided.

[0105] See also Figure 7 (a) in FIG. 1 shows a schematic diagram of a package structure of a chip with a 4-bit / 8-bit data width. Figure 7(b) in FIG. 1 shows a schematic diagram of a package structure of a chip with a 16-bit data width. Since the number of signal pins of an X4 / X8 chip is different from that of an X16 chip, Figure 7 As shown in (a) of FIG. 1 , for an X4 / X8 chip, the chip has a total of 13×6 signal pins, and at the four corners there are 4 pins without signal connections (only for support), and the overall size is 10 mm×11 mm; Figure 7 As shown in (b), for the X16 chip, the chip has a total of 17×6 signal pins, and at the four corners there are 4 pins without signal connection (only for support), and the overall size is 10 mm×14 mm. In other words, compared with the X4 / X8 chip, the X16 chip is larger in size, not only requiring more substrate area, but also causing the X4 / X8 / X16 to be incompatible with the same specification of dual-inline-memory-modules (DIMMs).

[0106] From the above, it can be seen that by using the packaging structure 10 provided by the present disclosure, X4, X8, and X16 can share a substrate, and the substrate size can be close to Figure 7 The size of (a) in the figure allows more chip units to be cut out from a substrate to reduce costs. At the same time, it can reduce the design cycle and no longer need to design different substrates for chips with different bit widths. At the same time, it has been found through testing that compared Figure 7 In (a), the signal pin array 20 provided by the present disclosure has a longer solder joint life, smaller plastic strain and longer fatigue life.

[0107] In another embodiment of the present disclosure, a signal pin array 30 is disposed on the surface of the package substrate 11. Figure 8 , which shows a schematic diagram of the structure of a signal pin array 30 provided by an embodiment of the present disclosure. Figure 8 As shown, the signal pin array 30 includes a plurality of data pins DQ, and the data pins DQ are used to transmit data signals; in the second direction, at most two data pins DQ are allowed to be arranged adjacent to each other.

[0108] It should be noted that, in the first direction, at most one data pin DQ is allowed to be arranged adjacently; and, at most one row of two adjacent rows has data pins DQ distributed therein, or, in other words, there is at most one data pin DQ around each data pin DQ (directly above, directly below, directly left, directly right, upper left, upper right, lower left, lower right), thereby improving the signal distortion problem while ensuring the transmission quality.

[0109] In particular, the signal pin array 30 provided in the present disclosure can also support X4, X8, and X16 chips.

[0110] In some embodiments, see Figure 8 For the data pins DQ of the first part, they are located in the edge row of the signal pin array, and any data pin DQ of the first part is not adjacent to other data pins DQ; for the data pins DQ of the second part, they are located in the non-edge row and non-edge column of the signal pin array 30, and every two data pins DQ of the second part are adjacent along the second direction; wherein, in the first direction, data pins DQ of different rows are separated by one row of pins.

[0111] In some embodiments, see Figure 8 The signal pin array 30 also includes a plurality of command address pins CA, which are used to transmit command address signals; for the command address pins CA of the first part, they are located at the edge rows of the signal pin array 30, and any command address pin CA of the first part is not adjacent to other command address pins CA; for the command address pins CA of the second part, they are located at non-edge rows and non-edge columns of the signal pin array 30, and at most 2 command address pins CA of the second part are allowed to be arranged continuously in the second direction, and at most 3 command address pins CA of the second part are allowed to be arranged continuously in the first direction, and the first direction refers to the column extension direction of the signal pin array 30.

[0112] In this way, the signal pin array 30 allows the data pins DQ to be located at the edge row, allows two data pins DQ to be arranged continuously adjacent to each other, and allows the command address pins CA to be located at the edge row, which can reduce the area of ​​the signal pin array and reduce chip cost.

[0113] In some embodiments, see Figure 8 The signal pin array 30 has a total of N rows, the data pins DQ of the first part are located in the 1st row, the data pins DQ of the second part are all located in the 2nd to A rows, the command address pins CA of the second part are all located in the Bth to (N-1)th rows, and the command address pins CA of the first part are located in the Nth row; A, B and N are all positive integers, A is less than B, and B is less than N-1.

[0114] In particular, Figure 8 Only N=13, A=7, and B=9 are taken as an example for illustration.

[0115] In some embodiments, see Figure 8 , the data pins DQ located in the 1st to (C-1) rows are used to transmit high-order data signals; the data pins DQ located in the (C+1)th to A rows are used to transmit low-order data signals; wherein, C=(A+1) / 2; or, the data pins DQ located in the 1st to C rows are used to transmit low-order data signals; the data pins DQ located in the C+1th to A rows are used to transmit high-order data signals; the pins located in the Cth row are all ground pins or power pins, and the ground pins are used to transmit ground signals, and the power pins are used to transmit power signals.

[0116] In some embodiments, see Figure 8 , in the second direction, the signal pin array 30 is divided into a first array, a central array, and a second array, the first array, the central array, and the second array are distributed along the second direction, the number of pins in the first array is the same as the number of pins in the second array, and all pins in the central array are removed;

[0117] The data pins DQ in the first array and the data pins DQ in the second array are symmetrical about the central array, and the command address pins CA in the first array and the command address pins CA in the second array are symmetrical about the central array.

[0118] In some embodiments, see Figure 8 , the signal pin array 30 further includes four data strobe pins (DQS_T, DQS_C), the data strobe pins are used to transmit data strobe signals; in the second direction, each data strobe pin is adjacent to the central array, and a portion of the data strobe pins is adjacent to the data pin DQ;

[0119] In the first direction, one data pin DQ, the first data strobe pin, the second data strobe pin, one ground pin or a power pin, the third data strobe pin, and the fourth data strobe pin are continuously and adjacently arranged along the first direction.

[0120] In some embodiments, see Figure 8 The signal pin array 30 also includes two first auxiliary control pins DM, the first auxiliary control pins are used to transmit mask flip control signals or terminal data selection signals; one first auxiliary control pin and one data selection pin are symmetrical about the center array.

[0121] In some embodiments, the signal pin array 30 further includes 1 local data strobe pin LBDQS, 1 local data pin LBDQ and a ZQ seventh auxiliary control pin;

[0122] The local data strobe pin LBDQS is located in an edge column, and the local data strobe pin LBDQS is adjacent to one data pin DQ along the second direction;

[0123] The local data strobe pin LBDQS and the local data pin LBDQ are symmetrical about the central array;

[0124] The seventh auxiliary control pin ZQ is adjacent to the local data strobe pin LBDQS along the first direction;

[0125] Among them, the local data pin LBDQ is used to transmit the local data signal, the local data selection pin LBDQS is used to transmit the local data selection signal, and the seventh auxiliary control pin ZQ is used to transmit the impedance calibration signal zq.

[0126] In some embodiments, see Figure 8 The signal pin array 30 also includes two chip select pins (CS_N[0], CS_N[1]) adjacent along the first direction, and the chip select pins are used to transmit chip select signals; the first chip select pin is adjacent to a data pin DQ along the first direction; the second chip select pin is adjacent to a command address pin CA along the second direction, and is adjacent to another command address pin CA along the first direction.

[0127] In some embodiments, the signal pin array 30 also includes two clock pins (CK_C, CK_T) adjacent to each other along a first direction, and the clock pins are used to transmit clock signals; the first clock pin is not adjacent to any command address pin CA; the second clock pin is adjacent to one command address pin CA along the second direction, and is adjacent to another command address pin CA along the first direction.

[0128] In some embodiments, see Figure 8 , 2 chip select pins are located in the first array and are adjacent to the edge column of the signal pin array 30; 2 clock pins are located in the second array and are adjacent to the center array; the first chip select pin and the first clock pin are located in the same row, and the second chip select pin and the second clock pin are located in the same row.

[0129] In some embodiments, see Figure 8 , the signal pin array 30 further includes two third auxiliary control pins (MIR, ALERT_n), and the two third auxiliary control pins are both located at the edge column of the signal pin array 30; the first third auxiliary control pin MIR is adjacent to the first chip select pin along the second direction; the second third auxiliary control pin ALERT_n is adjacent to the second chip select pin along the second direction;

[0130] The first third auxiliary control pin MIR is at least used to transmit a mirror mode enable signal, and the second third auxiliary control pin ALERT_n is used to transmit a check error indication signal.

[0131] In some embodiments, see Figure 8 , the signal pin array 30 also includes two reserved pins RFU, one second auxiliary control pin TEN and two fourth auxiliary control pins (MSCL, MSDA), the second auxiliary control pin TEN is used to transmit the test mode enable signal, and the fourth auxiliary control pin is used to transmit the protocol control signal;

[0132] The 2 reserved pins and the 2 chip select pins are symmetrical about the central array; the second fourth auxiliary control pin MSCL and a third auxiliary control pin MIR are symmetrical about the central array, the second auxiliary control pin TEN and another third auxiliary control pin ALERT_n are symmetrical about the central array, and the first fourth auxiliary control pin MSDA, the second fourth auxiliary control pin MSCL and the second auxiliary control pin TEN are arranged continuously along the first direction.

[0133] In some embodiments, see Figure 8 The signal pin array 30 also includes a fifth auxiliary control pin CA_ODT and a sixth auxiliary control pin RESET. The fifth auxiliary control pin CA_ODT and the sixth auxiliary control pin RESET are located at the edge columns of the signal pin array 30; the fifth auxiliary control pin CA_ODT and the sixth auxiliary control pin RESET are symmetrical about the central array; the straight-line adjacent pins of the fifth auxiliary control pin CA_ODT are all ground pins and / or power pins, and the straight-line adjacent pins of the sixth auxiliary control pin are all ground pins and / or power pins, the fifth auxiliary control pin CA_ODT is in the same row with at least one command address pin CA, and the sixth auxiliary control pin RESET is in the same row with at least one command address pin CA; wherein, the fifth auxiliary control pin CA_ODT is used to transmit a termination signal, and the sixth auxiliary control pin RESET is used to transmit a reset signal.

[0134] It should be noted that the signals transmitted by the above auxiliary control pins are only an example and do not constitute a corresponding limitation. That is to say, for the auxiliary control pins mentioned above, they are relatively flexible for transmitting the following signals: mask control signal (dml, dmu) or terminal data selection signal (tdqs_t, tdqs_c), test mode enable signal ten (used to control the chip to enter / not enter the test mode), mirror mode enable signal mir (used to control the chip to enter / not enter the mirror mode), check error signal (used to prompt that an error is detected in the cyclic redundancy check operation) alert_n, first protocol signal msda (I3C related signal), second protocol signal mscl (I3C related signal), termination signal ca_odt, reset signal reset, impedance calibration signal zq. At the same time, the position of the reserved pin can also be exchanged with the position of the auxiliary control pin.

[0135] In some embodiments, see Figure 8 The signal pin array 30 has 13 rows, the first array has 4 columns, and the second array has 4 columns, providing a total of 104 signal pins; A=7, B=9.

[0136] In another embodiment of the present disclosure, see Fig. 9 , which shows a schematic diagram of the composition structure of a semiconductor structure 60 provided by an embodiment of the present disclosure. Fig. 9As shown, the semiconductor structure 60 at least includes the aforementioned package structure 10 and a chip, and the data bit width of the chip is 4 bits, 8 bits or 16 bits.

[0137] Here, the chip may be placed on the packaging structure 10 , and the chip may be electrically connected to a signal pin array on the packaging substrate, so that various signals related to the chip are output / input through the packaging structure 10 .

[0138] In summary, the packaging structure 10 provided in the embodiment of the present disclosure is compatible with chips of X4, X8, and X16 specifications, so that chips of different bit widths can share the same substrate; and the substrate size is smaller, thereby controlling costs, and the overall performance is better.

[0139] The above are only preferred embodiments of the present disclosure and are not intended to limit the scope of protection of the present disclosure. It should be noted that in the present disclosure, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such a process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes one..." does not exclude the presence of other identical elements in the process, method, article or device including the element. The above serial numbers of the embodiments of the present disclosure are only for description and do not represent the advantages and disadvantages of the embodiments. The methods disclosed in several method embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments. The features disclosed in several product embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in several method or device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments. The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A packaging structure, characterized in that: It comprises a packaging substrate, a surface of which is provided with a signal pin array; The signal pin array includes a plurality of clock pins for carrying clock signals and a plurality of command address pins for carrying command address signals, the plurality of clock pins are arranged along a first direction, and each of the clock pins is adjacent to one of the command address pins along a second direction; The first direction is a column extension direction of the signal pin array, and the second direction is a row extension direction of the signal pin array.

2. The packaging structure according to claim 1, characterized in that: The signal pin array also includes a plurality of chip select pins for carrying chip select signals; A plurality of the chip select pins are arranged along a first direction; each of the chip select pins is adjacent to a command address pin along a second direction.

3. The packaging structure according to claim 1 or 2, characterized in that: The signal pin array further includes a plurality of chip select pins for carrying chip select signals and a plurality of data pins for carrying data signals; One of the chip select pins is also adjacent to one of the data pins along the first direction; One of the clock pins is also adjacent to another of the command address pins along the first direction.

4. The packaging structure according to any one of claims 1 to 3, characterized in that: The signal pin array further includes a plurality of chip select pins for carrying chip select signals and a plurality of data pins for carrying data signals; The signal pin array is divided into a first edge row, a data transmission area, a control transmission area, and a second edge row in sequence along a first direction; The plurality of data pins are all located in the data transmission area, and any two of the data pins are not adjacent to each other in a straight line; The plurality of command address pins, the plurality of clock pins and the plurality of chip select pins are all located in the control transmission area; and, in the first direction, at most 3 command address pins are allowed to be arranged continuously; and in the second direction, at most 2 command address pins are allowed to be arranged continuously.

5. The packaging structure according to claim 4, characterized in that: The signal pin array is divided into a first longitudinal region, a central column, and a second longitudinal region in sequence along a second direction, the number of signal pins in the first longitudinal region is the same as the number of signal pins in the second longitudinal region, and the pins in the central column are removed; A plurality of the data pins are located in a non-edge column of the first longitudinal region and a non-edge column of the second longitudinal region, and the data pins in the first longitudinal region and the data pins in the second longitudinal region are symmetrical about the center column; The plurality of command address pins are located in a portion of the first longitudinal region close to the central column and a portion of the second longitudinal region close to the central column, and the command address pins in the first longitudinal region are symmetrical with the command address pins in the second longitudinal region about the central column.

6. The packaging structure according to claim 5, characterized in that: A plurality of the chip select pins are located in the first longitudinal region, and the chip select pins are located on a side of the adjacent command address pins away from the central column; A plurality of the clock signal pins are located in the second longitudinal region and adjacent to the central column.

7. The packaging structure according to claim 5 or 6, characterized in that: The data transmission area is divided into a first transmission area and a second transmission area along a first direction, the total number of pins in the first transmission area is greater than the total number of pins in the second transmission area, and the number of data pins in the first transmission area is the same as the number of data pins in the second transmission area; The data pins in the first transmission area are used to transmit high-order data signals, and the data pins in the second transmission area are used to transmit low-order data signals; or, the data pins in the first transmission area are used to transmit low-order data signals, and the data pins in the second transmission area are used to transmit high-order data signals.

8. The packaging structure according to claim 7, characterized in that: The signal pin array further includes two pairs of data strobe pins for carrying data strobe signals, the first pair of data strobe pins being located in the first transmission area, the second pair of data strobe pins being located in the second transmission area, and the data strobe pins being adjacent to the center column; The two pins of each pair of the data strobe pins are adjacent along the first direction, and the first pair of the data strobe pins and the second pair of the data strobe pins are not adjacent along the first direction; The first pin of each pair of the data strobe pins is linearly adjacent to at least one of the data pins, and the second pin of each pair of the data strobe pins is not linearly adjacent to any of the data pins.

9. The packaging structure according to claim 8, characterized in that: The data transmission area is further provided with two pairs of first auxiliary control pins, the first pair of the first auxiliary control pins and the first pair of the data strobe pins are symmetrical about the central column, and the second pair of the first auxiliary control pins and the second pair of the data strobe pins are symmetrical about the central column; Other pins in the data transmission area are power pins or ground pins.

10. The packaging structure according to claim 9, characterized in that: One of the pins in each pair of the first auxiliary control pins is used to carry a mask control signal or a terminal data selection signal, and the other pin in each pair of the first auxiliary control pins is used to transmit a ground signal or is used as a reserved signal pin.

11. The packaging structure according to any one of claims 5 to 10, characterized in that: The control transmission area is also distributed with a plurality of second auxiliary control pins, a plurality of third auxiliary control pins, a plurality of fourth auxiliary control pins, a fifth auxiliary control pin and a sixth auxiliary control pin. The plurality of the second auxiliary control pins and the plurality of the chip selection pins are symmetrical about the central column; The plurality of third auxiliary control pins and the plurality of fourth auxiliary control pins are symmetrical about the central column, one third auxiliary control pin, one chip select pin and one command address pin are arranged continuously along the second direction, and one command address pin, one second auxiliary control pin and one fourth auxiliary control pin are arranged continuously along the second direction; The fifth auxiliary control pin and the sixth auxiliary control pin are symmetrical about the central column, the fifth auxiliary control pin and the third auxiliary control pin are located in the same column, and the fifth auxiliary control pin is not adjacent to the third auxiliary control pin; the sixth auxiliary control pin and the fourth auxiliary control pin are located in the same column, and the sixth auxiliary control pin is not adjacent to the fourth auxiliary control pin; The other pins in the control transmission area are power pins or ground pins.

12. The packaging structure according to claim 11, characterized in that: The first edge row is distributed with local data pins carrying local data signals and local data strobe pins carrying local data strobe signals, and the local data pins and the local strobe data pins are symmetrical about the central column, the local data pins are adjacent to one of the data pins along the first direction, and the local data strobe pins are adjacent to one of the data pins along the first direction; A seventh auxiliary control pin is further distributed on the first edge row, the seventh auxiliary control pin is adjacent to the central column, and the seventh auxiliary control pin is adjacent to the data pin along a first direction; The other pins in the first edge row and the second edge row are power pins or ground pins.

13. The packaging structure according to claim 12, characterized in that: There is at least one second auxiliary control pin for carrying a test mode enable signal, and at least one second auxiliary control pin is used as a reserved signal pin; At least one of the third auxiliary control pins carries a mirror mode enable signal, and at least one of the third auxiliary control pins carries a check error signal; At least one of the fourth auxiliary control pins is used to carry the first protocol signal, and at least one of the fourth auxiliary control pins is used to carry the second protocol signal; The fifth auxiliary control pin is used to carry a termination signal, and the sixth auxiliary control pin is used to carry a reset signal; The seventh auxiliary control pin is a calibration pin for carrying an impedance calibration signal.

14. The packaging structure according to any one of claims 5 to 13, characterized in that: The signal pin array has 14 rows, the first longitudinal region has 4 columns, and the second longitudinal region has 4 columns; The packaging form of each pin of the signal pin array is a ball grid. In the first direction, the distance between the center points of two adjacent ball grids is a first value. In the first direction, the distance between the center points of two adjacent ball grids is a second value. The first value is smaller than the second value.

15. A semiconductor structure, characterized in that: It comprises a packaging structure and a chip as described in any one of claims 1 to 14; wherein the data bit width of the chip is 4 bits, 8 bits or 16 bits.

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