Stacked structure of SiC module and manufacturing process thereof

Abstract

The invention discloses a stacked structure of a SiC module and a manufacturing process of the stacked structure. The module forms a full-bridge circuit topology through four SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) chips. A stacked structure is adopted, four SiC MOSFET chips are divided into two groups to form an upper layer and a lower layer, namely an upper bridge arm and a lower bridge arm of a circuit, the upper layer chip and the lower layer chip are connected through a welding ball and are welded to an upper lining plate and a lower lining plate respectively, a direct-current bus terminal is led out from the upper layer to be connected with an external direct-current power source positive electrode, and a direct-current bus terminal is led out from the lower layer to be connected with an external direct-current power source negative electrode. A direct-current bus terminal is led out from the lower layer to be connected with a negative electrode of an external direct-current power supply, two alternating-current output terminals are led out from a solder ball joint, and a laminated structure reduces a commutation path to obtain low parasitic inductance; the upper lining plate and the lower lining plate of the stacked structure are both connected to the radiator to form a double-face heat dissipation structure, in addition, the upper lining plate and the lower lining plate are connected through the copper columns, low heat resistance is obtained, and the heat reliability problem of the module is solved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a stacked structure of a SiC module and a manufacturing process thereof. Background Art

[0002] A power module is a high-density power electronic device that packages multiple power electronic components together according to certain functions. According to different functions, there are half-bridge modules, full-bridge modules, three-phase bridges, PIM modules, etc. Silicon carbide (SiC) materials have received widespread attention in recent years due to their advantages such as high temperature stability, high frequency characteristics and low on-resistance, and have become the preferred material for manufacturing high-performance power electronic devices. Using SiC devices instead of traditional silicon (Si) devices in power modules can increase power density and reduce power loss. The performance of SiC modules depends not only on the semiconductor material SiC inside them, but also on their packaging technology. Packaging technology plays a vital role in improving the performance, reliability and service life of power modules.

[0003] Traditional power modules are packaged in a planar structure, where Si devices are welded to the upper copper layer of the liner, and electrical interconnection between devices is achieved through bonding wires. This structure introduces significant parasitic inductance in the module package, where the typical value of the parasitic inductance of the wiring copper layer, bonding wire and power connection terminal can exceed 40 nanohenries (nH). For SiC devices, this level of parasitic inductance far exceeds the required nanosecond switching rate requirements, limiting its performance in high-frequency applications. In order to give full play to the performance of SiC, the prior art has reduced the parasitic inductance to a certain extent by optimizing the layout position of the power chip and the DC bus terminal, but the reduction is limited. There is also a flat structure that uses copper sheets, copper strips, flexible PCBs and other connections to replace bonding wires, but the manufacturing process is complicated. In Chinese patent application 202111057400.2, Bao Jie et al. obtained a low multi-unit power integrated module parasitic packaging structure by stacking two layers of chips and two liner boards on the upper and lower sides of the lead frame, but the chip power density of this solution is large, and the thermal management problem is actually still a big challenge.

[0004] Therefore, in order to give full play to the performance advantages of fast switching of SiC devices, the present invention proposes a SiC module stacking structure. This structure significantly reduces parasitic inductance by optimizing the electrical connection path, thereby improving the overall electrical performance of the module. In addition, the present invention further adopts double-sided heat dissipation to solve the thermal management challenges of high power density brought by stacking. Summary of the invention

[0005] In order to overcome the above-mentioned deficiencies of the prior art, the present invention provides a stacked structure of SiC modules and a manufacturing process thereof. The present invention vertically stacks the upper bridge arm and the lower bridge arm in the SiC full-bridge topology circuit to provide a SiC module stacked structure with a compact structure, high thermal efficiency and excellent electrical performance to meet the needs of high power conversion applications.

[0006] In order to achieve the above-mentioned purpose, firstly, the present invention comprises four SiC MOSFET chips to form a full-bridge circuit topology, and the four SiC MOSFET chips are divided into two groups, respectively constituting the first layer component and the second layer component. The stacked structure of the present invention comprises from top to bottom: a first heat sink, a first thermal grease layer, a first liner, a first interconnection layer, a first layer component, a third interconnection layer, a second layer component, a second interconnection layer, a second liner, a second thermal grease layer, and a second heat sink; the first liner comprises three layers, which are, from top to bottom, a first metal layer, a first insulating layer, and a first wiring layer; the second liner comprises three layers, which are, from top to bottom, a second wiring layer, a second insulating layer, and a second metal layer; the upper surface of the first layer component is mounted on the first wiring layer through the first interconnection layer, the lower surface of the second layer component is mounted on the second wiring layer through the second interconnection layer, and the lower surface of the first layer component and the upper surface of the second layer component are connected to the corresponding position of the third interconnection layer.

[0007] Specifically, the full-bridge circuit topology is composed of four SiC MOSFET chips, and the four SiC chips are divided into two groups to form a first-layer component and a second-layer component. The first-layer component includes two upper bridge arms, and the second-layer component includes two lower bridge arms. The source electrodes of the two chips of the upper bridge arm are connected to the first wiring layer through the first interconnection layer, and the drain electrodes of the two chips of the lower bridge arm are connected to the second wiring layer through the second interconnection layer. The drain electrodes of the two chips of the upper bridge arm are respectively connected to the source electrodes of the two chips of the lower bridge arm through the middle third interconnection layer; the first wiring layer is connected to the positive electrode of the external DC bus power supply, and the second wiring layer is connected to the negative electrode of the external DC bus power supply; the upper and lower bridge arms are interconnected to form two half bridges, and the two half bridges form a full-bridge circuit topology through the parallel connection of the first wiring layer and the second wiring layer, and the full bridge leads out two pin electrodes of alternating current respectively through the middle lead frame; the gate electrodes of the four chips are connected to the external gate lead-out terminal to receive the drive signal.

[0008] Specifically, the bus terminal of the first wiring layer connected to the positive pole of the external DC power supply adopts a double-terminal structure, which is respectively led out from the middle position where the two chips of the upper bridge arm are connected to the first wiring layer; the bus terminal of the second wiring layer connected to the negative pole of the external DC power supply adopts a double-terminal structure, which is respectively led out from the middle position where the two chips of the lower bridge arm are connected to the second wiring layer; the upper and lower groups of bus terminals are parallel to each other.

[0009] Specifically, a copper column is provided between the first liner and the second liner for thermal connection, and the metal layer in contact with the upper and lower ends of the copper column has no electrical connection with other parts of the first wiring layer and the second wiring layer.

[0010] Specifically, the third interconnection layer uses a solder ball array structure to connect the first layer components and the second layer components.

[0011] Specifically, the two upper bridge arm chips of the first layer assembly are in a flip-chip form, and the front side of the chip is connected to the first wiring layer. The two upper bridge arm chips of the second layer assembly are in a face-up form, and the back side of the chip is connected to the second wiring layer.

[0012] The present invention also discloses a manufacturing process of the stacked structure of the SiC module, and the specific steps are as follows:

[0013] Step 1, prepare a first liner with an insulating layer in the middle and metal layers on the upper and lower surfaces, pattern the metal layer on the lower surface of the first liner to produce a first wiring layer, produce a first interconnection layer on the first wiring layer at a position corresponding to the first layer component, and mount the first layer component; lead out two busbar terminals connected to the positive pole of an external DC power supply from the corresponding positions of the first wiring layer, and lead out two external drive signal gate terminals from the corresponding positions of the first wiring layer;

[0014] Step 2, prepare a second liner with an insulating layer in the middle and metal layers on the upper and lower surfaces, pattern the metal layer on the upper surface of the second liner to produce a second wiring layer, produce a second interconnection layer at a position corresponding to the second layer component on the second wiring layer, and mount the second layer component; place a copper column on the metal layer that is separately isolated in the second wiring layer, and the copper column has no electrical connection with other parts on the second wiring layer; lead out two busbar terminals connected to the negative electrode of the external DC power supply from the corresponding position of the second wiring layer;

[0015] Step 3, make a third interconnection layer, i.e., an array of solder balls with equal spacing, in the source region on the front side of the second-layer component, and interconnect the solder ball array with the drain region on the back side of the first-layer component; connect the copper pillars to the metal layers in the first wiring layer that have no electrical connection with other parts; lead out two terminals of AC output from the two groups of solder ball arrays respectively; lead out two gate terminals of external drive signals from the gate region on the front side of the second-layer component;

[0016] Step 4: Weld the first lining plate and the second lining plate in the structure obtained in step 3 to the first heat sink and the second heat sink through the first thermal grease layer and the second thermal grease layer.

[0017] Specifically, the height of the copper column is the sum of the thicknesses of the first interconnection layer, the first layer component, the third interconnection layer, the second layer component, and the second interconnection layer; the cross-section of the copper column can be elliptical or rectangular.

[0018] Specifically, the number of solder balls on a single chip in the third interconnection layer is no less than 20.

[0019] Compared with the prior art, the present invention has the following beneficial effects:

[0020] 1. High power density design: The SiC module of the present invention achieves higher power density by optimizing the stacking structure, so that the module can withstand and convert greater power while being smaller in size, meeting the requirements of modern power electronic equipment for miniaturization and high efficiency.

[0021] 2. Low parasitic inductance design: The stacked structure not only eliminates the traditional bonding wires and shortens the commutation path, but also reduces the parasitic inductance of the commutation loop through the carefully designed positive and negative pole layout of the DC bus power supply. This optimization not only reduces electromagnetic interference, but also improves the switching speed and efficiency of the module.

[0022] 3. Excellent thermal management performance: The use of copper pillars and double-sided heat dissipation significantly improves the heat dissipation capacity of the module. This design helps to maintain the stable operation of the module under long-term high-load operation and prolongs the service life of the module.

[0023] 4. Enhanced electrical connection stability: The stability and reliability of electrical connections are improved by adopting a solder ball array structure and a dual-terminal busbar terminal design. The solder ball array structure provides more connection points, while the dual-terminal design provides redundant connections, reducing the risk of failure of the entire module due to a single connection point failure. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 Schematic diagram of the stacked structure of the SiC module of the present invention.

[0025] Figure 2 It is a circuit schematic diagram of the present invention.

[0026] Figure 3 FIG. 4 is a pin layout diagram of an embodiment of the present invention.

[0027] Figure 4 FIG. 4 is an internal chip layout diagram of an embodiment of the present invention.

[0028] Figure 5 1 is a planar structural diagram of a first wiring layer and a second wiring layer according to an embodiment of the present invention. DETAILED DESCRIPTION

[0029] The present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0030] The schematic diagram of the stacked structure of the SiC module proposed in the present invention is as follows Figure 1As shown. The module structure from top to bottom is the first heat sink 11, the first thermal grease layer 21, the first metal layer 31, the first insulating layer 41, the first wiring layer 51, the first interconnection layer 61, the first layer component 71, the third interconnection layer 8, the second layer component 72, the second interconnection layer 62, the second wiring layer 52, the second insulating layer 42, the second metal layer 32, and the second heat sink 12; wherein the first metal layer 31, the first insulating layer 41, and the first wiring layer 51 constitute the first liner; the second wiring layer 52, the second insulating layer 42, and the second metal layer 32 constitute the second liner. A double-sided heat dissipation structure of the first heat sink and the second heat sink is adopted, and a copper column 9 is arranged between the first liner and the second liner for thermal connection to improve the heat dissipation efficiency of the upper and lower layer components, thereby extending the service life of the SiC module.

[0031] like Figure 2 As shown in FIG. 3 , the SiC module of the embodiment of the present invention is a full-bridge circuit composed of four SiC MOSFETs, each of which has a parasitic body diode to improve the freewheeling path. The two SiC MOSFETs on the left are connected in series to form the first half-bridge, the two SiC MOSFETs on the right are connected in series to form the second half-bridge, and the two half-bridges are connected in parallel to form a full-bridge. The two SiC MOSFETs on the top form the upper bridge arm, and the two SiC MOSFETs on the bottom form the lower bridge arm.

[0032] Figure 4 The second layer component 72 is shown in a top view. The second layer component 72 corresponds to Figure 2 The lower bridge arm in the circuit schematic diagram includes two SiC MOSFET chips, whose back drain is soldered to the second wiring layer 52 in the second substrate through the second interconnect layer 62, and whose front source region 722 is connected to the third interconnect layer 8 (i.e., a uniformly distributed solder ball array), and the upper surface of the solder ball array is connected to the back drain region of the first layer component 71 of the upper bridge arm in the corresponding circuit schematic diagram, and its front gate region 721 is connected to the external gate pin.

[0033] The third interconnection layer 8 uses a solder ball array instead of traditional bonding wires, providing more connection points and reducing the risk of failure of the entire module due to a single connection point failure. In addition, the first layer component 71 and the second layer component 72 form an upper and lower stacking structure through the solder ball array, and the solder ball height is small, which improves the power density on the one hand, shortens the power circuit commutation path on the other hand, and reduces the parasitic inductance of the commutation circuit.

[0034] Figure 2The circuit schematic diagram shows the external pins. The drain of the upper bridge arm is connected to the positive pole DC+ of the external DC voltage source, and the source of the lower bridge arm is connected to the negative pole DC- of the external DC voltage source. The pin electrodes AC1 and AC2 are led out through the connection point of the upper and lower bridge arms (i.e. the source of the upper bridge arm and the drain of the lower bridge arm), and the output AC signal is added to the external load. The gate pins G1, G2, G3, and G4 of the four SiC MOSFETs are connected to the external drive signal to control the opening and closing of the SiC MOSFET.

[0035] Figure 3 The positive pole DC+ of the external DC power supply is led out from the first wiring layer 51, and the negative pole DC- of the external DC power supply is led out from the second wiring layer 52. The DC bus terminal adopts a double-terminal structure, which provides a redundant design and improves electrical stability on the one hand, and the two terminals are symmetrically arranged on the other hand, thereby ensuring the symmetry of the power circuit structure of the two half bridges and avoiding the imbalance problem of parasitic inductance and parasitic resistance in the package layout. The AC output terminals AC1 and AC2 are respectively led out from two groups of solder ball arrays, and the gates G1 and G3 of the upper bridge arm are led out through the first wiring layer 51, and the gates of the lower bridge arm are led out from the second wiring layer 52.

[0036] The embodiment of the present invention also provides a manufacturing process of the stacked structure of the SiC module, and the specific steps are as follows:

[0037] Step 1: Prepare the first liner (with an insulating layer in the middle and metal layers on the upper and lower surfaces), and pattern the metal layer on the lower surface of the first liner to produce the first wiring layer 51, with a thickness ranging from 18μm to 20μm, and a planar structure such as Figure 5 As shown by the solid line. A ring area is etched in the middle of the first wiring layer 51, and there is no metal layer in the ring area. The metal layer inside the ring area is used to connect the copper column 9. The first interconnection layer 61 is made at a position corresponding to the first layer component 71, and 75μm to 80μm nano silver glue or 95μm to 100μm lead-free solder paste can be used. The front of the first layer component 71 is mounted on the first interconnection layer 61; two bus terminals DC+ for the positive pole of the external DC power supply are led out from the first wiring layer 51, as well as two external drive signal gate terminals G1 and G3.

[0038] Step 2: prepare a second substrate (with an insulating layer in the middle and metal layers on the upper and lower surfaces), and pattern the metal layer on the upper surface of the second substrate to produce a second wiring layer 52 with a thickness ranging from 18 μm to 20 μm. Figure 5As shown by the solid line, the second interconnection layer 62 is made at the position corresponding to the second layer component 72. The back of the second layer component 72 can be mounted on the second interconnection layer 62 using 75μm to 80μm nano silver paste or 95μm to 100μm lead-free solder paste. Two bus terminals DC- connected to the negative pole of the external DC power supply and two external drive signal gate terminals G2 and G4 are led out from the second wiring layer 52. An annular area is etched in the middle of the second wiring layer 52. There is no metal layer in the annular area. A copper column 9 is placed on the metal layer inside the annular area.

[0039] The height of the copper pillar is the sum of the thickness of the first interconnection layer 61, the first layer component 71, the third interconnection layer 8, the second layer component 72, and the second interconnection layer 2. The cross section of the copper pillar 9 can be elliptical or rectangular. If it is elliptical, the length of its minor axis is 2mm to 5mm, and if it is rectangular, its width is 2mm to 5mm. The annular area is used to isolate the metal layer connected to the copper pillar 9, so that the copper pillar 9 has no electrical connection with other parts on the first wiring layer 51 and the second wiring layer 52. The shape of the annular area is designed according to needs.

[0040] There is no requirement for the order between the above steps 1 and 2. There can be one or more copper pillars 9, which are arranged in the middle of the liner or near the heating point.

[0041] Step 3, make a third interconnection layer 8, that is, an array of solder balls with equal spacing, in the source area on the front side of the second layer component 72, and interconnect the solder ball array with the drain area on the back side of the first layer component 71. The embodiment uses a 6×6 array with a total of 36 solder balls, using a lead-tin alloy with a size of 0.2mm to 1.3mm. Connect the copper pillar 9 to the metal layer in the middle annular area of ​​the first wiring layer 51; lead out the two terminals AC1 and AC2 of the AC output from the two groups of solder ball arrays respectively; connect the gate area on the front side of the second layer component 72 to the gate area of ​​the second wiring layer 52 through bonding wires.

[0042] Step 4: Weld the first liner plate and the second liner plate in the structure obtained in step 3 to the first heat sink 11 and the second heat sink 12 through the first thermal grease layer 21 and the second thermal grease layer 22. The thickness of the thermal grease is 0.05 mm to 0.1 mm. The first heat sink 11 and the second heat sink 12 can be made of copper or aluminum heat sink blocks, or pin-fin heat sinks, fin heat sinks, water-cooled heat sinks, etc.

[0043] The stacked structure of the SiC module proposed in the present invention meets the needs of modern power electronic equipment for miniaturization and high efficiency with its high power density design. At the same time, through the low parasitic inductance design, the commutation path is optimized, the electromagnetic interference is reduced, and the switching speed and efficiency are improved. In addition, the excellent thermal management performance benefits from the innovative application of copper pillars and double-sided heat dissipation, ensuring the stable operation and long life of the module under high load. Enhanced electrical connection stability is achieved through the solder ball array structure and the dual-terminal busbar terminal design, which provides more connection points and redundant connections, significantly reducing the risk of module failure. These combined advantages enable the SiC module of the present invention to exhibit excellent performance and reliability in high power conversion applications.

[0044] The present invention is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention shall be included in the protection scope of the present invention.

Claims

1. A stacked structure of SiC modules, using four SiC MOSFET chips to form a full-bridge circuit topology, characterized in that: The four SiC MOSFET chips are divided into two groups, respectively constituting a first layer assembly (71) and a second layer assembly (72); the stacked structure comprises, from top to bottom, a first heat sink (11), a first thermal grease layer (21), a first liner, a first interconnection layer (61), a first layer assembly (71), a third interconnection layer (8), a second layer assembly (72), a second interconnection layer (62), a second liner, a second thermal grease layer (22), and a second heat sink (12); the first liner comprises three layers, from top to bottom, a first metal layer (31), a first insulation layer (32), and a second heat sink (12); The invention relates to a first wiring layer (51) and a second wiring layer (51); the second substrate comprises three layers, which are, from top to bottom, a second wiring layer (52), a second insulating layer (42), and a second metal layer (32); the upper surface of the first layer component (71) is mounted on the first wiring layer (51) through the first interconnection layer (61), and the lower surface of the second layer component (72) is mounted on the second wiring layer (52) through the second interconnection layer (62); the lower surface of the first layer component (71) and the upper surface of the second layer component (72) are connected to corresponding positions of the third interconnection layer (8).

2. The stacked structure of SiC modules according to claim 1, characterized in that: In the full-bridge circuit topology, the first-layer component (71) includes two upper bridge arms, and the second-layer component (72) includes two lower bridge arms. The source electrodes of the two chips in the upper bridge arm are connected to the first wiring layer (51) through the first interconnection layer (61), and the drain electrodes of the two chips in the lower bridge arm are connected to the second wiring layer (52) through the second interconnection layer (62). The drain electrodes of the two chips in the upper bridge arm are respectively connected to the source electrodes of the two chips in the lower bridge arm through the middle third interconnection layer (8); the first wiring layer (51) is connected to the positive electrode of the external DC bus power supply, and the second wiring layer (52) is connected to the negative electrode of the external DC bus power supply; the upper and lower bridge arms are interconnected to form two half bridges, and the two half bridges are then connected in parallel through the first wiring layer (51) and the second wiring layer (52) to form a full-bridge circuit topology, and the full bridge leads out two pin electrodes of alternating current through the middle lead frame; the gate electrodes of the four chips are connected to the external gate lead-out terminal to receive the drive signal.

3. The stacked structure of SiC modules according to claim 2, characterized in that: The busbar terminals of the first wiring layer (51) connected to the positive electrode of the external DC power supply adopt a double terminal structure and are respectively led out from the middle position where the two chips of the upper bridge arm are connected to the first wiring layer (51); the busbar terminals of the second wiring layer (52) connected to the negative electrode of the external DC power supply adopt a double terminal structure and are respectively led out from the middle position where the two chips of the lower bridge arm are connected to the second wiring layer (52); the upper and lower groups of busbar terminals are parallel to each other.

4. The stacked structure of SiC modules according to claim 1, characterized in that: A copper column (9) is arranged between the first liner and the second liner for thermal connection, and the metal layer in contact with the upper and lower ends of the copper column (9) has no electrical connection with other parts of the first wiring layer (51) and the second wiring layer (52).

5. The stacked structure of SiC modules according to claim 1, characterized in that: The third interconnection layer (8) adopts a solder ball array structure to connect the first layer component (71) and the second layer component (72).

6. The stacked structure of SiC modules according to claim 1, characterized in that: The two upper bridge arm chips included in the first layer component (71) are in a flip-chip form, and the front side of the chip is connected to the first wiring layer (51) of the first substrate. The two upper bridge arm chips included in the second layer component (72) are in a face-up form, and the back side of the chip is connected to the second wiring layer (52) of the second substrate.

7. A manufacturing process for a stacked structure of SiC modules, characterized in that: The following steps are involved: Step 1, preparing a first liner with an insulating layer in the middle and metal layers on the upper and lower surfaces, patterning the metal layer on the lower surface of the first liner to produce a first wiring layer (51), producing a first interconnection layer (61) at a position corresponding to the first layer component (71) on the first wiring layer (51), and mounting the first layer component (71); leading out two bus terminals for externally connected DC positive power supply and two gate terminals for externally connected drive signals from corresponding positions of the first wiring layer (51); Step 2, preparing a second liner with an insulating layer in the middle and metal layers on the upper and lower surfaces, patterning the metal layer on the upper surface of the second liner to produce a second wiring layer (52), producing a second interconnection layer (62) at a position corresponding to the second layer component (72) on the second wiring layer (52), and mounting the second layer component (72); placing a copper pillar (9) on the metal layer that is separately isolated from the second wiring layer (52), and the copper pillar (9) has no electrical connection with other parts on the second wiring layer (52); and leading out two busbar terminals connected to the negative pole of an external DC power supply from corresponding positions of the second wiring layer (52); Step 3, fabricating a third interconnection layer (8), i.e., an array of solder balls distributed at equal intervals, in the front source region of the second layer component (72), interconnecting the solder ball array with the back drain region of the first layer component (71); connecting the copper pillars (9) to the metal layers in the first wiring layer (51) that have no electrical connection with other parts; respectively leading out two terminals of AC output from the two groups of solder ball arrays; leading out two gate terminals of external drive signals from the front gate region of the second layer component (72); Step 4: Weld the first lining plate and the second lining plate in the structure obtained in step 3 to the first heat sink (11) and the second heat sink (12) respectively through the first thermal grease layer (21) and the second thermal grease layer (22).

8. The manufacturing process of a stacked structure of SiC modules according to claim 7, characterized in that: The height of the copper pillar (9) is the sum of the thicknesses of the first interconnection layer (61), the first layer assembly (71), the third interconnection layer (8), the second layer assembly (72), and the second interconnection layer (62); the cross section of the copper pillar (9) is elliptical or rectangular.

9. The manufacturing process of a stacked structure of SiC modules according to claim 7, characterized in that: The number of solder balls on a single chip in the third interconnection layer (8) is not less than 20.

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