A switched capacitor common mode feedback circuit

Abstract

The present invention discloses a switched capacitor type common mode feedback circuit, and relates to the field of common mode feedback circuits. The present invention uses a switched capacitor type common mode feedback circuit with higher linearity and lower power consumption to detect and correct the output common mode level, and outputs a stable and accurate common mode feedback voltage with an effective clock; and fully considers the adverse effects caused by common charge injection and clock feedthrough in switched capacitor circuits, adopts a partially complementary switch structure, and reduces the error caused by clock feedthrough and charge injection in the switched capacitor circuit structure; and adopts a virtual switch at a relevant position to release the residual charge in the channel caused by the clock, thereby improving the accuracy of circuit detection and calibration. The present invention reduces the adverse effects of clock feedthrough and charge injection on the existing circuit during clock conversion, thereby solving the problem of limiting the operating frequency, clock frequency and dynamic range of the circuit to a certain extent.

Description

Technical Field

[0001] The present invention relates to the field of common mode feedback circuits, and in particular to a switched capacitor type common mode feedback circuit. Background Art

[0002] In scenarios where high-gain op amps are required, fully differential op amps are usually used. The characteristic of this type of op amp is that the common-mode output level is prone to drift due to device mismatch. At this time, a common-mode feedback circuit is required, that is, by detecting the output common-mode level of the fully differential op amp, the detected common-mode level value is compared with the given reference voltage and calibrated. There are two common common-mode feedback circuits: continuous-time common-mode feedback and switched capacitor common-mode feedback. The continuous-time common-mode feedback circuit usually detects the output common-mode voltage through a resistor, and continuously detects and calibrates the output common-mode voltage. Therefore, its structural advantage is that the detection is more accurate and stable, but its disadvantages are that the output impedance changes; the output swing is small; and the power consumption is large. The switched capacitor common-mode feedback circuit calibrates the output common-mode voltage based on charge distribution, does not introduce new zeros and poles, has a large output range and has high linearity. The existing switched capacitor common-mode feedback circuit uses clock control to sample and hold the capacitor. The influence of clock feedthrough and charge injection during clock conversion will limit the operating frequency, clock frequency and dynamic range of the circuit. Summary of the invention

[0003] In view of the above-mentioned deficiencies in the prior art, a switched capacitor common-mode feedback circuit provided by the present invention reduces the adverse effects of clock feedthrough and charge injection on the prior art circuit during clock conversion, thereby solving the problem of limiting the operating frequency, clock frequency and dynamic range of the circuit to a certain extent.

[0004] In order to achieve the above-mentioned purpose of the invention, the technical solution adopted by the present invention is: a switched capacitor common-mode feedback circuit, comprising:

[0005] a first complementary switch, the first complementary switch comprising an NMOS tube M2 and a PMOS tube M3, the gate of the NMOS tube M2 being connected to the clock CKB, the drain thereof being connected to the voltage OUTP, the source thereof being respectively connected to one end of the capacitor C3, the drain of the PMOS tube M3 and the source of the NMOS tube M10, the source of the PMOS tube M3 being connected to the voltage OUTP, the gate thereof being connected to CKB', the gate of the NMOS tube M10 being connected to the clock CK, the drain thereof being grounded, and the CKB' being a signal of the clock CKB passing through an inverter;

[0006] a second complementary switch, the second complementary switch comprising an NMOS tube M4 and a PMOS tube M5, wherein the gate of the NMOS tube M4 is connected to CKB, the source thereof is connected to the voltage OUTP, the drain thereof is respectively connected to the drain of the PMOS tube M11, one end of the capacitor C4 and the source of the PMOS tube M5, the drain of the PMOS tube M5 is connected to the voltage OUTP, the gate thereof is connected to CKB', the source of the PMOS tube M11 is connected to the power supply voltage VDD, and the gate thereof is connected to CK', wherein CK' is a signal of the clock CK passing through an inverter;

[0007] a third complementary switch, the third complementary switch comprising an NMOS tube M6 and a PMOS tube M7, the gate of the NMOS tube M6 being connected to the clock CKB, the source of the NMOS tube M6 being respectively connected to one end of the capacitor C5, the drain of the PMOS tube M7 and the source of the NMOS tube M12, the drain of which being connected to the voltage OUTN, the source of the PMOS tube M7 being connected to the voltage OUTN, the gate of which being connected to CKB', the drain of the NMOS tube M12 being grounded, and the gate of which being connected to the clock CK;

[0008] a fourth complementary switch, the fourth complementary switch comprising an NMOS tube M8 and a PMOS tube M9, the gate of the NMOS tube M8 being connected to the clock CKB, the drain of the NMOS tube M8 being respectively connected to the drain of the PMOS tube M13, one end of the capacitor C6 and the source of the PMOS tube M9, the source of the NMOS tube M8 being connected to the voltage OUTN, the source of the PMOS tube M13 being connected to the power supply voltage VDD, the gate of the PMOS tube M9 being connected to CK', the gate of the PMOS tube M9 being connected to CKB', and the drain of the PMOS tube M9 being connected to the voltage OUTN;

[0009] The other end of the capacitor C3 is respectively connected to the drain of the NMOS tube M14, the other end of the capacitor C4 and the drain of the NMOS tube M16, the gate of the NMOS tube M14 is connected to the clock CKB, and its source is connected to the drain of the NMOS tube M15, the gate of the NMOS tube M15 is connected to the clock CKB, and its source is respectively connected to the other end of the capacitor C5, the other end of the capacitor C6 and the source of the NMOS tube M17, the gate of the NMOS tube M17 is connected to the clock CK, and the drain of the NMOS tube M17 is connected to the source of the NMOS tube M16, and the voltage at this point is the input bias voltage V b , the gate of the NMOS tube M16 is connected to the clock CK.

[0010] Furthermore, the clock CK and the clock CKB are a set of clocks with opposite phases.

[0011] Furthermore, the switched capacitor common-mode feedback circuit also includes a virtual switch, which includes an NMOS tube M1, a gate of which is connected to the clock CK, a drain and a source of which are connected, and are simultaneously connected to one end of the capacitor C1, one end of the capacitor C2, a source of the NMOS tube M14, and a drain of the NMOS tube M15, the other end of the capacitor C1 is connected to the voltage OUTP, and the other end of the capacitor C2 is connected to the voltage OUTN.

[0012] Furthermore, the voltage at the connection point between the drain and the source of the NMOS tube M1 is the output common-mode feedback voltage V CMFB .

[0013] Furthermore, the phase of the switched capacitor common-mode feedback circuit includes two situations: clock CK=1, clock CKB=0 and clock CK=0, clock CKB=1.

[0014] Furthermore, when the clock CK=1 and the clock CKB=0, the charge charged by the capacitor is:

[0015] ΔQ 3、4、5、6 =b×C b

[0016] ΔQ 1、2 =a0×C a

[0017] b=V CM -V b

[0018] Among them, ΔQ 3、4、5、6 is the charge of capacitors C3, C4, C5 and C6, ΔQ 1、2 is the charge of capacitors C1 and C2, b is the difference between the set ideal common-mode voltage and the input bias voltage, C b is the capacitance value of capacitors C3, C4, C5 and C6, a0 is the output common mode level V in the 0th cycle out and the output common-mode feedback voltage V CMFB The difference, C a is the capacitance value of capacitor C1 and capacitor C2, V CM is the ideal common-mode voltage, V b is the input bias voltage.

[0019] Furthermore, when the clock CK=0 and the clock CKB=1, the charge charged by the capacitor is:

[0020] ΔQ 3、4、5、6 =a1×C b

[0021] ΔQ 1、2=a1×C a

[0022] Where a1 is the output common mode level V in the first cycle out and the output common-mode feedback voltage V CMFB The difference.

[0023] Furthermore, as the effective clock is turned on and off, the output common-mode level V out Detect and output the calibrated output common-mode feedback voltage V CMFB , the formula is:

[0024] V out [∞]-V CMFB [∞]=V CM -V b

[0025] Among them, V out [∞] is the output common mode level of the clock CK in an infinite cycle, V CMFB [∞] is the output common-mode feedback voltage V of the clock CK in an infinite cycle CMFB .

[0026] The beneficial effects of the present invention are as follows: the present invention proposes a new switched capacitor common-mode feedback circuit, which aims to reduce the change of the common-mode level caused by non-ideal factors such as device mismatch, and improve the stability of the output common-mode level in the differential amplifier. The present invention changes the traditional continuous common-mode feedback structure and adopts a switched capacitor common-mode feedback circuit with higher linearity and lower power consumption to detect and correct the output common-mode level, and outputs a stable and accurate common-mode feedback voltage with the effective clock. In addition, the adverse effects caused by common charge injection and clock feedthrough in the switched capacitor circuit are fully considered, and the structure of a partial complementary switch is adopted to reduce the error caused by clock feedthrough and charge injection in the switched capacitor circuit structure; in addition, a virtual switch is used at the relevant position to release the residual charge in the channel caused by the clock, thereby improving the accuracy of circuit detection and calibration. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 This is a schematic diagram of a switched capacitor common-mode feedback circuit.

[0028] Figure 2 This is the equivalent circuit schematic diagram when clock CK=1 and clock CKB=0.

[0029] Figure 3 This is the equivalent circuit schematic diagram when clock CK=0 and clock CKB=1. DETAILED DESCRIPTION

[0030] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

[0031] like Figure 1 As shown, a switched capacitor common-mode feedback circuit comprises:

[0032] a first complementary switch, the first complementary switch comprising an NMOS tube M2 and a PMOS tube M3, the gate of the NMOS tube M2 being connected to the clock CKB, the drain thereof being connected to the voltage OUTP, the source thereof being respectively connected to one end of the capacitor C3, the drain of the PMOS tube M3 and the source of the NMOS tube M10, the source of the PMOS tube M3 being connected to the voltage OUTP, the gate thereof being connected to CKB', the gate of the NMOS tube M10 being connected to the clock CK, the drain thereof being grounded, and the CKB' being a signal of the clock CKB passing through an inverter;

[0033] a second complementary switch, the second complementary switch comprising an NMOS tube M4 and a PMOS tube M5, wherein the gate of the NMOS tube M4 is connected to CKB, the source thereof is connected to the voltage OUTP, the drain thereof is respectively connected to the drain of the PMOS tube M11, one end of the capacitor C4 and the source of the PMOS tube M5, the drain of the PMOS tube M5 is connected to the voltage OUTP, the gate thereof is connected to CKB', the source of the PMOS tube M11 is connected to the power supply voltage VDD, and the gate thereof is connected to CK', wherein CK' is a signal of the clock CK passing through an inverter;

[0034] a third complementary switch, the third complementary switch comprising an NMOS tube M6 and a PMOS tube M7, the gate of the NMOS tube M6 being connected to the clock CKB, the source of the NMOS tube M6 being respectively connected to one end of the capacitor C5, the drain of the PMOS tube M7 and the source of the NMOS tube M12, the drain of which being connected to the voltage OUTN, the source of the PMOS tube M7 being connected to the voltage OUTN, the gate of which being connected to CKB', the drain of the NMOS tube M12 being grounded, and the gate of which being connected to the clock CK;

[0035] a fourth complementary switch, the fourth complementary switch comprising an NMOS tube M8 and a PMOS tube M9, the gate of the NMOS tube M8 being connected to the clock CKB, the drain of the NMOS tube M8 being respectively connected to the drain of the PMOS tube M13, one end of the capacitor C6 and the source of the PMOS tube M9, the source of the NMOS tube M8 being connected to the voltage OUTN, the source of the PMOS tube M13 being connected to the power supply voltage VDD, the gate of the PMOS tube M9 being connected to CK', the gate of the PMOS tube M9 being connected to CKB', and the drain of the PMOS tube M9 being connected to the voltage OUTN;

[0036] The other end of the capacitor C3 is respectively connected to the drain of the NMOS tube M14, the other end of the capacitor C4 and the drain of the NMOS tube M16, the gate of the NMOS tube M14 is connected to the clock CKB, and its source is connected to the drain of the NMOS tube M15, the gate of the NMOS tube M15 is connected to the clock CKB, and its source is respectively connected to the other end of the capacitor C5, the other end of the capacitor C6 and the source of the NMOS tube M17, the gate of the NMOS tube M17 is connected to the clock CK, and the drain of the NMOS tube M17 is connected to the source of the NMOS tube M16, and the voltage at this point is the input bias voltage V b , the gate of the NMOS tube M16 is connected to the clock CK.

[0037] For a common switched capacitor common-mode feedback circuit, since the circuit requires clock control, the non-ideal factors caused by clock feedthrough and charge injection have a great impact on the circuit performance.

[0038] The present invention adopts a partially complementary switch structure, and combines M2 / M3, M4 / M5, M6 / M7, and M8 / M9 into four groups of complementary switches. Since each group of switches combines NMOS with PMOS, the error of the clock feedthrough coupled to the output end through the parasitic capacitance between the gate and the source and drain is offset, and at the same time, the opposite charges introduced by the charge injection are offset by the two channels, thereby reducing the error caused by the clock feedthrough and the charge injection in the switch capacitor circuit structure.

[0039] The clock CK and the clock CKB are a set of clocks with opposite phases.

[0040] The switched capacitor common-mode feedback circuit also includes a virtual switch, which includes an NMOS tube M1. The gate of the NMOS tube M1 is connected to the clock CK, and its drain and source are connected, and are simultaneously connected to one end of the capacitor C1, one end of the capacitor C2, the source of the NMOS tube M14, and the drain of the NMOS tube M15. The other end of the capacitor C1 is connected to the voltage OUTP, and the other end of the capacitor C2 is connected to the voltage OUTN.

[0041] The present invention adopts a virtual switch M1 at the relevant position. When M14 and M15 are disconnected, M1 is turned on, and the charge deposited on the former channel is absorbed by the latter to establish the latter channel, thereby weakening the charge injection effect and improving the detection and calibration accuracy of the circuit.

[0042] The voltage at the connection between the drain and source of the NMOS tube M1 is the output common-mode feedback voltage V CMFB .

[0043] Circuit V CMFB V is the voltage applied to the gate of the preamplifier tail current source after being detected and calibrated by the common-mode feedback circuit.CM To set the ideal common mode voltage, this circuit is set to V b is the ideal gate value of the tail current source MOS tube in the preamplifier. Set the capacitance values ​​of C1 and C2 to C a ; The capacitance values ​​of C3, C4, C5, and C6 are set to C b . And introduce two parameters:

[0044] a n =V out [n]-V CMFB [n]

[0045] b=V CM -V b

[0046] Due to the existence of the clock, the parameter n indicates that the clock is in the nth cycle.

[0047] The phase of the switched capacitor common mode feedback circuit includes two situations: clock CK=1, clock CKB=0 and clock CK=0, clock CKB=1.

[0048] like Figure 2 As shown in the figure, when the clock CK = 1 and the clock CKB = 0, the four groups of MOS complementary switches composed of M2, M3, M4, M5, M6, M7, M8, and M9 are disconnected in this phase, and the output voltages of OUTP and OUTN are AC coupled by C1 and C2, and the differential components are offset. The common-mode feedback output voltage is provided by point X, which can act on the gate of the tail current source MOS tube of the preamplifier. However, due to the existence of coupling capacitors C1 and C2, the output common-mode feedback voltage is not stable. C3, C4, C5, and C6 can be regarded as With V b Charge it. At this time, the charge charged by the capacitor is:

[0049] ΔQ 3、4、5、6 =b×C b

[0050] ΔQ 1、2 =a0×C a

[0051] Among them, ΔQ 3、4、5、6 is the charge of capacitors C3, C4, C5 and C6, ΔQ 1、2 is the charge of capacitors C1 and C2, b is the difference between the set ideal common-mode voltage and the input bias voltage, C b is the capacitance value of capacitors C3, C4, C5 and C6, a0 is the output common mode level V in the 0th cycle out and the output common-mode feedback voltage V CMFB The difference, Ca is the capacitance value of capacitor C1 and capacitor C2.

[0052] like Figure 3 As shown in the figure, when the clock CK=0 and the clock CKB=1, the four groups of MOS complementary switches composed of M2, M3, M4, M5, M6, M7, M8 and M9 are closed in this phase. At this time, the output voltages of OUTP and OUTN are AC coupled by C1, C2, C3, C4, C5 and C6, and the common-mode feedback voltage V is provided by point X. CMFB , acting on the gate of the MOS tube of the tail current source of the front operational amplifier for correction. At this time, the charge charged by the capacitor is:

[0053] ΔQ 3、4、5、6 =a1×C b

[0054] ΔQ 1、2 =a1×C a

[0055] Where a1 is the output common mode level V in the first cycle out and the output common-mode feedback voltage V CMFB The difference.

[0056] According to the law of charge conservation, we can get:

[0057] b×C b +a0×C a =a1×(C a +C b )

[0058] From this we can infer:

[0059] b×C b +a1×C a =a2×(C a +C b )

[0060] …

[0061] We can get:

[0062]

[0063] a n The expression for a0 is:

[0064]

[0065]

[0066] Therefore:

[0067]

[0068] so:

[0069] V out [∞]-V CMFB [∞]=V CM -V b

[0070] Among them, V out [∞] is the output common mode level of the clock CK in an infinite cycle, V CMFB [∞] is the output common-mode feedback voltage V of the clock CK in an infinite cycle CMFB .

[0071] That is, as the effective clock is turned on and off, the output common-mode level V out Detect and output the calibrated output common-mode feedback voltage V CMFB .

[0072] In order to reduce the impact of clock feedthrough and charge injection, this circuit adopts special processing in two places. First, the circuit adds a virtual switch M1 tube. The gate of M1 tube is controlled by CK, and its source and drain are connected. The source of M14 and the drain of M15 are connected to this place. The gates of M14 and M15 are controlled by CKB. When M14 and M15 are disconnected, M1 is turned on, and the charge deposited on the channel of the former is absorbed by the latter to establish the channel of the latter, weakening the impact of charge injection. The second place is to combine M2 / M3, M4 / M5, M6 / M7, M8 / M9 into four groups of complementary switches. Since each group of switches combines NMOS with PMOS, the error of clock feedthrough coupled to the output end through the parasitic capacitance between the gate and the source and drain is offset. At the same time, the opposite charge introduced by charge injection is offset by the two channels, reducing clock feedthrough and charge redistribution, and reducing the adverse effects of signal and intermodulation on the circuit.

[0073] Those skilled in the art will appreciate that the embodiments described herein are intended to help readers understand the principles of the present invention, and should be understood that the protection scope of the present invention is not limited to such specific statements and embodiments. Those skilled in the art can make various other specific variations and combinations that do not deviate from the essence of the present invention based on the technical revelations disclosed by the present invention, and these variations and combinations are still within the protection scope of the invention.

Claims

1. A switched capacitor common mode feedback circuit, characterized in that: include: a first complementary switch, the first complementary switch comprising an NMOS tube M2 and a PMOS tube M3, the gate of the NMOS tube M2 being connected to the clock CKB, the drain thereof being connected to the voltage OUTP, the source thereof being respectively connected to one end of the capacitor C3, the drain of the PMOS tube M3 and the source of the NMOS tube M10, the source of the PMOS tube M3 being connected to the voltage OUTP, the gate thereof being connected to CKB', the gate of the NMOS tube M10 being connected to the clock CK, the drain thereof being grounded, and the CKB' being a signal of the clock CKB passing through an inverter; a second complementary switch, the second complementary switch comprising an NMOS tube M4 and a PMOS tube M5, wherein the gate of the NMOS tube M4 is connected to CKB, the source thereof is connected to the voltage OUTP, the drain thereof is respectively connected to the drain of the PMOS tube M11, one end of the capacitor C4 and the source of the PMOS tube M5, the drain of the PMOS tube M5 is connected to the voltage OUTP, the gate thereof is connected to CKB', the source of the PMOS tube M11 is connected to the power supply voltage VDD, and the gate thereof is connected to CK', wherein CK' is a signal of the clock CK passing through an inverter; a third complementary switch, the third complementary switch comprising an NMOS tube M6 and a PMOS tube M7, the gate of the NMOS tube M6 being connected to the clock CKB, the source of the NMOS tube M6 being respectively connected to one end of the capacitor C5, the drain of the PMOS tube M7 and the source of the NMOS tube M12, the drain of which being connected to the voltage OUTN, the source of the PMOS tube M7 being connected to the voltage OUTN, the gate of which being connected to CKB', the drain of the NMOS tube M12 being grounded, and the gate of which being connected to the clock CK; a fourth complementary switch, the fourth complementary switch comprising an NMOS tube M8 and a PMOS tube M9, the gate of the NMOS tube M8 being connected to the clock CKB, the drain of the NMOS tube M8 being respectively connected to the drain of the PMOS tube M13, one end of the capacitor C6 and the source of the PMOS tube M9, the source of the NMOS tube M8 being connected to the voltage OUTN, the source of the PMOS tube M13 being connected to the power supply voltage VDD, the gate of the PMOS tube M9 being connected to CK', the gate of the PMOS tube M9 being connected to CKB', and the drain of the PMOS tube M9 being connected to the voltage OUTN; The other end of the capacitor C3 is respectively connected to the drain of the NMOS tube M14, the other end of the capacitor C4 and the drain of the NMOS tube M16, the gate of the NMOS tube M14 is connected to the clock CKB, and its source is connected to the drain of the NMOS tube M15, the gate of the NMOS tube M15 is connected to the clock CKB, and its source is respectively connected to the other end of the capacitor C5, the other end of the capacitor C6 and the source of the NMOS tube M17, the gate of the NMOS tube M17 is connected to the clock CK, and the drain of the NMOS tube M17 is connected to the source of the NMOS tube M16, and the voltage at this point is the input bias voltage V b , the gate of the NMOS tube M16 is connected to the clock CK.

2. The switched capacitor common mode feedback circuit according to claim 1, characterized in that: The clock CK and the clock CKB are a set of clocks with opposite phases.

3. The switched capacitor common mode feedback circuit according to claim 2, characterized in that: The switched capacitor common-mode feedback circuit also includes a virtual switch, which includes an NMOS tube M1. The gate of the NMOS tube M1 is connected to the clock CK, and its drain and source are connected, and are simultaneously connected to one end of the capacitor C1, one end of the capacitor C2, the source of the NMOS tube M14, and the drain of the NMOS tube M15. The other end of the capacitor C1 is connected to the voltage OUTP, and the other end of the capacitor C2 is connected to the voltage OUTN.

4. The switched capacitor common mode feedback circuit according to claim 3, characterized in that: The voltage at the connection between the drain and source of the NMOS tube M1 is the output common-mode feedback voltage V CMFB .

5. The switched capacitor common mode feedback circuit according to claim 4, characterized in that: The phase of the switched capacitor common mode feedback circuit includes two situations: clock CK=1, clock CKB=0 and clock CK=0, clock CKB=1.

6. The switched capacitor common mode feedback circuit according to claim 5, characterized in that: When the clock CK=1 and the clock CKB=0, the charge on the capacitor is: ΔQ 3、4、5、6 =b×H b ΔQ 1、2 =a0×C a b=V CM -V b Among them, ΔQ 3、4、5、6 is the charge of capacitors C3, C4, C5 and C6, ΔQ 1、2 is the charge of capacitors C1 and C2, b is the difference between the set ideal common-mode voltage and the input bias voltage, C b is the capacitance value of capacitors C3, C4, C5 and C6, a0 is the output common mode level V in the 0th cycle out and the output common-mode feedback voltage V CMFB The difference, C a is the capacitance value of capacitor C1 and capacitor C2, V CM is the ideal common-mode voltage, V b is the input bias voltage.

7. The switched capacitor common mode feedback circuit according to claim 6, characterized in that: When the clock CK = 0 and the clock CKB = 1, the charge on the capacitor is: ΔQ 3、4、5、6 =a1×C b ΔQ 1、2 =a1×C a Where a1 is the output common mode level V in the first cycle out and the output common-mode feedback voltage V CMFB The difference.

8. The switched capacitor common mode feedback circuit according to claim 7, characterized in that: As the effective clock turns on and off, the output common-mode level V out Detect and output the calibrated output common-mode feedback voltage V CMFB , the formula is: V out [∞]-V CMFB [∞]=V CM -V b Among them, V out [∞] is the output common mode level of the clock CK in an infinite cycle, V CMFB [∞] is the output common-mode feedback voltage V of the clock CK in an infinite cycle CMFB .

Images