Vcm-based capacitor switch sequence circuit and method

Abstract

The invention discloses a Vcm-based capacitor switch sequential circuit and a Vcm-based capacitor switch sequential method. A first array first capacitor bank, a second array first capacitor bank,..., an ith array first capacitor bank, a first array second capacitor bank, a second array second capacitor bank,..., a jth array second capacitor bank, a first array dummy capacitor bank and a second array dummy capacitor bank in the switch sequence circuit respectively comprise two capacitors which are connected in parallel and have the same capacitance value, according to the improved capacitor array structure, each capacitor is divided into two equal capacitors, the two equal capacitors can be connected with different potentials through a lower electrode plate to achieve three different voltage connection methods, namely Vref, 1 / 2 Vref and GND, the equivalent circuit structure of the capacitor array structure is basically consistent with Vcm-based, but Vcm is equal to 1 / 2 Vref through the arrangement of the two equal capacitors, and the equivalent circuit structure of the capacitor array structure is not equal to GND. The improved Vcm-based capacitor switch time sequence does not need an additional circuit to generate a common-mode level Vcm, does not need a complex bootstrap switch structure, reduces the power consumption and the area, and is suitable for the design of a low-voltage SAR ADC (Synthetic Aperture Radar Analog to Digital Converter).

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit design, and relates to a Vcm-based capacitor switch timing circuit and method. Background Art

[0002] With the development of integrated circuits, people have higher demands for high-precision and low-power analog-to-digital converters. In order to meet market demand, the Successive Approximation Register (SAR) ADC is well suited to the evolution of modern integrated circuit technology due to its advantages such as simple structure, obvious digital characteristics, few analog modules, low power consumption, and generally no need for linear gain module units. It has gradually become a hot spot in the ADC research field. The basic structural block diagram of SAR ADC is shown in the figure below. Figure 1 As shown in the figure. The basic modules of SAR ADC include differential capacitor DAC, comparator and SAR logic. Among them, the power consumption of capacitor array is the most important factor determining the overall power consumption of SAR ADC. In recent years, researchers at home and abroad have proposed a variety of efficient capacitor switching schemes such as energy-saving capacitor switching timing, monotonic capacitor switching timing and Vcm-based capacitor switching timing, which significantly reduce the switching power consumption of capacitor array.

[0003] Among them, for Vcm-based capacitor switching timing, due to its small number of unit capacitors, this reduces hardware cost and circuit complexity. In addition, during the conversion process, since the lower plates of all capacitors are adjusted relative to Vcm after sampling, the common-mode level remains unchanged, reducing the input offset and noise sensitivity of the comparator. At the same time, due to its reduction of unnecessary switching operations and capacitor charging and discharging times, the average power consumption of Vcm-based timing is reduced by 87% compared with traditional timing, which has outstanding advantages. However, for Vcm-based capacitor switching timing, an accurate common-mode voltage Vcm needs to be provided, which increases the complexity and cost of the design, and since the voltage connected to the switch tube is Vcm (not Vref or gnd), when the power supply voltage is low, the on-resistance of ordinary CMOS switch tubes will become very large, unless a bootstrap switch structure is used, but the power consumption and area overhead of the bootstrap switch structure are relatively large, so the Vcm-based method is not suitable for SAR ADC design with low power supply voltage. Summary of the invention

[0004] In view of the problems existing in the prior art, the present invention provides a Vcm-based capacitor switch timing circuit and method, thereby solving the technical problem that the Vcm-based capacitor switch timing circuit in the prior art cannot be used under low power supply voltage conditions.

[0005] The present invention is achieved through the following technical solutions:

[0006] A Vcm-based capacitor switch timing circuit includes: a first capacitor array, a second capacitor array, a first input terminal Vip, a second input terminal Vin and a comparator;

[0007] The first capacitor array comprises an array-first capacitor group, an array-second capacitor group, ..., an array-j-th capacitor group and an array-first dummy capacitor group connected in parallel in sequence; the lower plates of the array-first capacitor group, the array-second capacitor group, ..., the array-j-th capacitor group and the array-first dummy capacitor group are connected to Vref and / or GND, and the upper plates are connected to the first input terminal Vip and the in-phase input terminal of the comparator;

[0008] The second capacitor array comprises a first capacitor group of array 2, a second capacitor group of array 2, ..., a j-th capacitor group of array 2 and a dummy capacitor group of array 2, which are sequentially connected in parallel; the lower plates of the first capacitor group of array 2, the second capacitor group of array 2, ..., the j-th capacitor group of array 2 and the dummy capacitor group of array 2 are connected to Vref and / or GND, and the upper plates are connected to the second input terminal Vin and the inverting input terminal of the comparator;

[0009] The first capacitor group of array one, the second capacitor group of array one, ... the i-th capacitor group of array one, the first capacitor group of array two, the second capacitor group of array two, ... the j-th capacitor group of array two, the dummy capacitor group of array one and the dummy capacitor group of array two all include two capacitors of equal capacitance connected in parallel.

[0010] Preferably, the array-a dummy capacitor group includes a capacitor CP1 and a capacitor CP2 connected in parallel, and the capacitance of the capacitor CP1 and the capacitor CP2 are both 1 / 2C.

[0011] Preferably, the second dummy capacitor group of the array includes a capacitor CN1 and a capacitor CN2 connected in parallel, and the capacitance of the capacitor CN1 and the capacitor CN2 are both 1 / 2C.

[0012] Preferably, the array first i-th capacitor group includes capacitor CP i1 And the capacitor CP i2 , the capacitance CP i1 And capacitor CP i2 The capacitance value is 2 N-3 C, where N=i, 3≤i≤8.

[0013] Preferably, the second j-th capacitor group of the array includes capacitor CP j1 And the capacitor CP j2 , the capacitance CP j1 And capacitor CP j2The capacitance value is 2 N-3 C, where N=j, 3≤j≤8.

[0014] Preferably, the Vcm-based capacitor switch timing circuit also includes a first switch group, and the lower plates of the array-one first capacitor group, the array-one second capacitor group, ..., the array-one j-th capacitor group and the array-one dummy capacitor group can be connected and disconnected with the Vref and / or GND through the first switch group.

[0015] Preferably, the Vcm-based capacitor switch timing circuit also includes a second switch group, and the lower plates of the array second first capacitor group, array second second capacitor group, ..., array second jth capacitor group and array second dummy capacitor group can be connected and disconnected with the Vref and / or GND through the second switch group.

[0016] Preferably, the Vcm-based capacitor switch timing circuit further includes a SAR logic circuit; the input end of the SAR logic circuit is electrically connected to the output end of the comparator, and the SAR logic circuit communicates with the first switch group and the second switch group.

[0017] Preferably, i=j=8.

[0018] In addition, the present invention also discloses a Vcm-based capacitor switch timing method. During sampling, the lower plate of one capacitor in the first capacitor group of array 1, the second capacitor group of array 1, ... the jth capacitor group of array 1, and the dummy capacitor group of array 1 is connected to Vref, and the other is connected to GND;

[0019] The lower plate of a corresponding capacitor in the first capacitor group of array 2, the second capacitor group of array 2, ... the jth capacitor group of array 2 and the dummy capacitor group of array 2 is connected to GND, and the other corresponding capacitor is connected to Vref.

[0020] Compared with the prior art, the present invention has the following beneficial technical effects:

[0021] The present invention discloses a Vcm-based capacitor switch timing circuit. In the switch timing circuit, the first capacitor group of array 1, the second capacitor group of array 1, ... the i-th capacitor group of array 1, the first capacitor group of array 2, the second capacitor group of array 2, ... the j-th capacitor group of array 2, the dummy capacitor group of array 1 and the dummy capacitor group of array 2 all include two capacitors with equal capacitance values ​​connected in parallel. The improved capacitor array structure divides each capacitor into two to form two equal capacitors. The two equal capacitors can realize three different voltage connection methods by connecting the lower plate to different potentials, namely Vref, 1 / 2Vref and GND. The equivalent circuit structure is basically consistent with that of Vcm-based. However, by setting two equal capacitors, Vcm=1 / 2Vref, that is, the improved Vcm-based capacitor switch timing does not require an additional circuit to generate a common mode level Vcm, does not require a complex bootstrap switch structure, reduces power consumption and area, and is suitable for low-voltage SAR ADC design. In summary, the Vcm-based capacitor switch timing circuit reduces unnecessary circuit components and power sources, making the overall ADC more energy efficient; secondly, the Vcm generation circuit is removed, which simplifies the overall circuit layout and wiring, and reduces the design complexity and cost; in addition, by accurately controlling the voltage connection method of the capacitor group, the stability and anti-interference ability of the ADC are improved.

[0022] Furthermore, the array one dummy capacitor group includes a capacitor CP1 and a capacitor CP2 connected in parallel, and the capacitance of the capacitor CP1 and the capacitor CP2 are both 1 / 2C; the array two dummy capacitor group includes a capacitor CN1 and a capacitor CN2 connected in parallel, and the capacitance of the capacitor CN1 and the capacitor CN2 are both 1 / 2C. This setting can firstly simplify the circuit structure and reduce the dependence on external circuits. Since the two capacitors of the dummy capacitor group have equal capacitance and are half of the total capacitance C, they can jointly simulate an equivalent Vcm=1 / 2Vref effect, thereby eliminating the additional Vcm generating circuit, which not only simplifies the overall structure of the circuit, but also reduces the design complexity and cost.

[0023] Furthermore, the array first i-th capacitor group includes capacitor CP i1 And capacitor CP i2 , the capacitance CP i1 And capacitor CP i2 The capacitance value is 2 N-3 C, where N = i, 3≤i≤8; the second j-th capacitor group of the array includes capacitor CP j1 And capacitor CP j2 , the capacitance CP j1 And capacitor CP j2 The capacitance value is 2 N-3C, where N = j, 3 ≤ j ≤ 8. First, this setting improves the flexibility of capacitance configuration. Using the capacitance configuration method of 2^(N-3)*C, the capacitance of the capacitor can be easily changed by adjusting N (i.e., the serial number of the capacitor group), thereby achieving weight distribution of different precisions. This flexibility is essential for designing high-precision and high-performance circuits such as SAR ADC. At the same time, this setting can reduce the impact of capacitor mismatch. In applications such as SAR ADC, the mismatch between capacitors is one of the key factors affecting accuracy. By adopting precise capacitor matching technology and process control, the mismatch between capacitors can be minimized. In addition, using larger capacitors (such as capacitor groups with higher serial numbers) can reduce the impact of relative mismatch, because larger capacitors contribute more to the total capacitance, while relatively small mismatches have less impact on it.

[0024] Furthermore, the Vcm-based capacitor switch timing circuit also includes a first switch group, and the lower plates of the first capacitor group of array one, the second capacitor group of array one, ..., the jth capacitor group of array one, and the dummy capacitor group of array one can be connected and disconnected with the Vref and / or GND through the first switch group; the Vcm-based capacitor switch timing circuit also includes a second switch group, and the lower plates of the first capacitor group of array two, the second capacitor group of array two, ..., the jth capacitor group of array two, and the dummy capacitor group of array two can be connected and disconnected with the Vref and / or GND through the second switch group. This setting can perform flexible voltage configuration. Through the first switch group and the second switch group, the connection between the lower plate of each capacitor group in array one and array two and Vref (reference voltage) and / or GND (ground) can be independently controlled. This flexibility enables the voltage of the capacitor group to be accurately configured as needed during the sampling, holding and conversion stages, thereby optimizing the dynamic range and accuracy of the ADC. At the same time, switching noise can be reduced. The design of the switch group allows the connection state of the capacitor group to be switched at the appropriate time, thereby minimizing the noise caused by the switching action. This low noise characteristic is particularly important for high-precision ADCs because it can reduce quantization errors and improve the signal-to-noise ratio (SNR). At the same time, this setting can optimize power consumption. The precise control of the switch group means that switching actions are performed only when necessary, thereby reducing unnecessary power consumption. In addition, the overall power consumption is further reduced by removing the additional Vcm generation circuit, which is particularly important for portable devices and battery-powered applications. In summary, the settings of the first switch group and the second switch group play a key role in the Vcm-based capacitor switch timing circuit. They not only improve the performance and flexibility of the ADC, but also reduce power consumption, enhance stability and reliability, and simplify circuit design and wiring.

[0025] Further, the Vcm-based capacitor switch timing circuit also includes a SAR logic circuit; the input end of the SAR logic circuit is electrically connected to the output end of the comparator, the SAR logic circuit communicates with the first switch group and the second switch group, and the SAR logic circuit is a core component of a SAR ADC (successive approximation analog-to-digital converter). It gradually approaches the analog value of the input signal through logical judgment according to the comparison result output by the comparator, and finally converts it into a digital output. In each comparison cycle, the SAR logic circuit receives the output signal of the comparator, and determines how to adjust the voltage configuration of the capacitor array (by controlling the first switch group and the second switch group) according to the signal to approximate the voltage value of the input signal. This process is repeated until the required conversion accuracy is achieved. The SAR logic circuit realizes a fast successive approximation conversion process through efficient algorithms and logic control. This conversion method is faster than a traditional parallel ADC while maintaining a high accuracy. By accurately controlling the voltage configuration of the capacitor array and the comparison process of the comparator, the SAR logic circuit can reduce the influence of quantization errors and other non-ideal factors, thereby improving the conversion accuracy of the ADC.

[0026] Further, i=j=8, in the Vcm-based capacitor switch timing circuit, setting i=j=8 means that array one and array two each contain 8 capacitor groups, including dummy capacitor groups. Usually, dummy capacitor groups do not directly participate in signal conversion, but are used for matching and calibration. The setting of i=j=8 first improves the resolution. Each capacitor group (including dummy capacitor groups) usually represents a digital code output by the ADC. Therefore, when i=j=8, if only the capacitor group for signal conversion is considered, the resolution of the ADC can theoretically reach 8 bits, which is very suitable for applications requiring medium-precision measurement. In addition, this setting can optimize power consumption and area, balance performance and resources, and the setting of 8 capacitor groups finds a relatively balanced point between resolution, power consumption and chip area. Compared with the setting of more capacitor groups, it reduces the number of switches required, control logic and wiring complexity, thereby reducing power consumption and chip area. At the same time, it still provides sufficient resolution to meet the needs of many applications. At the same time, this setting can also simplify the design and reduce complexity. Fewer capacitor groups mean fewer control signals and logic circuits, which simplifies the design and implementation of the overall circuit and makes it easier to optimize the switch timing, control logic, and calibration process to improve the performance and reliability of the ADC. In addition, this setting can improve stability and reduce parasitic effects. Fewer capacitor groups and switches reduce the parasitic capacitance and inductance effects in the circuit, which may cause signal distortion and increased noise. By reducing these parasitic effects, the stability and signal-to-noise ratio (SNR) of the ADC can be improved. Moreover, for many applications, 8-bit resolution is a reasonable compromise point, which is neither too expensive nor too limited. Therefore, the setting of i=j=8 provides a cost-effective solution that can reduce manufacturing costs without sacrificing too much performance. In summary, the setting of i=j=8 can improve resolution, optimize power consumption and area, simplify design, improve stability and cost-effectiveness in Vcm-based capacitor switch timing circuits.

[0027] At the same time, the present invention also discloses a Vcm-based capacitor switch timing method. During sampling, the lower plate of one capacitor in the first capacitor group of array one, the second capacitor group of array one, ... the jth capacitor group of array one, and the dummy capacitor group of array one is connected to Vref, and the other is connected to GND; the lower plate of one corresponding capacitor in the first capacitor group of array two, the second capacitor group of array two, ... the jth capacitor group of array two, and the dummy capacitor group of array two is connected to GND, and the other corresponding capacitor is connected to Vref. In the Vcm-based capacitor switch timing method disclosed by the present invention, a specific connection setting is performed on the capacitor groups of array one and array two during the sampling stage, that is, the two lower plates of the capacitors in each capacitor group (including the dummy capacitor group) of array one and array two are connected to Vref and GND respectively, but the connection method is symmetrical between array one and array two. This setting can first reduce the change of common-mode voltage. In the sampling stage, by connecting the capacitor groups of array one and array two to Vref and GND respectively, the common-mode voltage (Vcm) at the input of the comparator can be kept relatively stable during the sampling process, which helps to reduce the comparator offset and nonlinear errors caused by the change of common-mode voltage. Secondly, it can improve signal integrity. The stable common-mode voltage helps to maintain signal integrity and reduce signal distortion and noise during transmission, which is crucial to improving the overall performance of the ADC. It can also support differential input, because array one and array two represent the positive and negative ends of the differential signal respectively. Through differential input, the ADC can improve the ability to suppress common-mode noise and further improve the accuracy of signal conversion. At the same time, this setting is also beneficial to the subsequent conversion stage. After the sampling stage, when entering the conversion stage, the voltage value of the input signal can be gradually approached by changing the connection relationship of the lower plate of the capacitor. Since the sampling stage has laid a good foundation for the conversion stage (i.e., stable common-mode voltage and differential input), the conversion stage can be carried out more efficiently and accurately. At the same time, the linearity and dynamic range of the ADC are improved. By precisely controlling the connection mode and switching timing of the capacitor group, the linearity and dynamic range of the ADC can be optimized, which is very important for applications that require high-precision and high-dynamic range measurements. In addition, since the switching actions in the sampling stage and the conversion stage are all based on precise timing control, the switching frequency and power consumption of the switch can be optimized. In addition, by reducing unnecessary switching actions and reducing the power consumption of the control circuit, the overall power consumption of the ADC can be further reduced. In addition, this method can also be applied to higher-bit ADC designs to achieve higher resolution and accuracy.In summary, the Vcm-based capacitor switching timing method disclosed in the present invention brings significant beneficial effects in reducing common-mode voltage changes, improving signal integrity, simplifying switching logic, supporting differential input, improving ADC linearity and dynamic range, reducing power consumption, and enhancing design flexibility and scalability through a specific sampling phase setting. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0029] Figure 1 It is a basic structural block diagram of SAR ADC in the prior art;

[0030] Figure 2 The capacitor array structure of the SAR ADC with a traditional differential structure;

[0031] Figure 3 A capacitor array structure for a monotonic differential SAR ADC;

[0032] Figure 4 Capacitor array structure for Vcm-based differential SAR ADC;

[0033] Figure 5 is the capacitance structure of the Vcm-based switch in the present invention;

[0034] Figure 6 Schematic diagram of capacitor equivalent circuit in the present invention;

[0035] Figure 7 Schematic diagram of the equivalent circuit structure of the Vcm-based capacitor array in the present invention;

[0036] Figure 8 is the switch state of the capacitor switch in the timing sampling phase of the present invention;

[0037] Fig. 9 is a schematic diagram of the equivalent circuit structure;

[0038] Fig.10 Figure 2 is a schematic diagram of the switching power consumption of a 3-bit SAR ADC using an improved capacitor switching timing.

[0039] Wherein: 1. first capacitor array, 2. second capacitor array, 3. first switch group, 4. second switch group, 5. comparator, 6. SAR logic circuit. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0041] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0042] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0043] In the description of the embodiments of the present invention, it should be noted that if the terms "upper", "lower", "horizontal", "inner", etc. indicate an orientation or positional relationship based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the product of the invention is usually placed when in use, it is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In addition, the terms "first", "second", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0044] In addition, if the term "horizontal" appears, it does not mean that the component must be absolutely horizontal, but can be slightly tilted. For example, "horizontal" only means that its direction is more horizontal than "vertical", which does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0045] In the description of the embodiments of the present invention, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal connection of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0046] The present invention is further described in detail below in conjunction with the accompanying drawings:

[0047] Example 1

[0048] The successive approximation analog-to-digital converter (SAR ADC) is very suitable for low-power applications. It uses a successive approximation algorithm to continuously convert analog input into digital output codes. The basic structure diagram of the SAR ADC is shown in the figure below. Figure 1 As shown. In order to improve the common-mode noise suppression capability and conversion accuracy, ADC usually adopts a differential structure. The basic modules of SAR ADC include differential capacitor DAC, comparator and SAR logic. The DAC capacitor array determines the accuracy of the entire SAR ADC. Generally speaking, the differential capacitor DAC is composed of a group of binary weighted capacitor arrays, which aims to improve the matching between bit capacitors and reduce the impact of parasitic effects. For SAR ADCs using capacitive DAC structure, the DAC itself also integrates the sampling and holding functions. The comparator module compares the analog output of the differential capacitor DAC under the control of the clock signal and passes the comparison result to the SAR control logic. The SAR logic obtains the digital code in turn according to the comparator output and latches it for unified output after the conversion is completed. At the same time, the control signal is generated through the corresponding logic to control the differential capacitor DAC to complete the successive approximation process.

[0049] The main sources of power consumption for SAR ADC are capacitor arrays, comparators, and SAR logic. The development of CMOS technology has further reduced the power consumption of digital circuits. For SAR ADCs using full-dynamic comparators, the power consumption of the comparator is mainly determined by noise and sampling rate. Therefore, the power consumption of the capacitor array is the most important factor determining the overall power consumption of the SAR ADC. Obviously, from the perspective of power consumption, the unit capacitance value of the capacitor array should be as small as possible, but the minimum value of the unit capacitance is determined by noise and capacitor mismatch. Generally speaking, capacitor mismatch plays a major role. At present, the main capacitor switching solutions include energy-saving capacitor switching timing, monotonic capacitor switching timing, and Vcm-based capacitor switching timing, which significantly reduce the switching power consumption of the capacitor array.

[0050] The traditional differential structure of N-bit SAR ADC is as follows: Figure 2 For traditional capacitor switching timing, an N-bit differential SAR ADC requires 2 N+1Unit capacitors. The traditional capacitor switch timing uses the lower plate sampling, and its working process is as follows: In the sampling stage, the upper plates of all capacitors are connected to the common mode voltage Vcm, and the lower plates sample the input signal at the same time. After the sampling is completed, the sampling switch is disconnected, and the highest capacitor of the capacitor array connected to the positive input of the comparator is connected to Vref, and the remaining capacitors are grounded. The capacitor array connected to the negative input of the comparator is connected in the opposite way, that is, the highest capacitor is grounded, and the remaining capacitors are connected to Vref. Then the comparator starts the first comparison. If Vip is greater than Vin, MSB = 1; otherwise MSB = 0, and the highest capacitor at the positive input is grounded, and the highest capacitor at the negative input is connected to Vref. Then the second highest capacitor at the positive input is connected to Vref, and the second highest capacitor at the negative input is grounded. The comparator starts the second comparison and obtains the second highest digital code. This process is repeated until the LSB is determined. The common mode level of the traditional capacitor switch timing does not change, and the total number of capacitors is 2 N+1 , the average energy consumption is higher.

[0051] The N-bit SAR ADC with monotonic capacitor switching timing is as follows: Figure 3 For monotonic capacitor switching timing, an N-bit differential SAR ADC requires 2 N The number of unit capacitors required is reduced by half compared with the traditional capacitor switching timing. The monotonic capacitor switching timing adopts upper plate sampling. During the sampling stage, the lower plates of all capacitors are connected to the reference voltage Vref, and the upper plate samples the input signal. After the sampling is completed, the sampling switch is disconnected, and the comparator directly performs the first comparison. This step does not consume switching energy. The maximum capacitor of the capacitor array connected to the positive input of the comparator is connected to Vref, and the remaining capacitors are grounded. If Vip is greater than Vin, MSB = 1, and the maximum capacitor of the capacitor array connected to the positive input of the comparator is grounded; otherwise MSB = 0, and the maximum capacitor of the capacitor array connected to the negative input of the comparator is grounded, and the connection of the remaining capacitors remains unchanged. Then the comparator starts the second comparison, obtains the MSB-1 bit digital code, and grounds the corresponding bit capacitor at the higher end of the comparator input voltage according to the comparator output. This process is repeated until the LSB is determined. Compared with the traditional capacitor switching timing, its common mode level changes, the total capacitance is reduced by half, and the average power consumption is reduced by 81%.

[0052] An N-bit SAR ADC using Vcm-based capacitor switching timing is shown in Figure 2. Figure 4 For Vcm-based capacitor switching timing, an N-bit differential SAR ADC only needs 2 NUnit capacitors are connected, which is the same as the monotonic capacitor switching timing. During the sampling phase, the lower plates of all capacitors are connected to Vcm, and the upper plates sample the input signal. After the sampling is completed, the sampling switch is disconnected, and the comparator directly performs the first comparison. If Vip is greater than Vin, MSB = 1, and the lower plate of the maximum capacitor at the positive input of the comparator is grounded, and the lower plate of the maximum capacitor at the negative input of the comparator is connected to Vref; otherwise MSB = 0, and the lower plate of the maximum capacitor at the positive input of the comparator is connected to Vref, and the lower plate of the maximum capacitor at the negative input of the comparator is grounded. Then the comparator starts the second comparison and obtains the MSB-1 bit digital code. This process is repeated until the LSB is determined. Compared with the traditional capacitor switching timing, the common mode level of the Vcm-based capacitor switching timing does not change, and the average power consumption is reduced by 87%. However, the Vcm-based switching method requires a third reference voltage Vcm, and because the voltage connected to the switch tube is Vcm (not Vref or gnd), when the power supply voltage is low, the on-resistance of the ordinary CMOS switch tube will become very large, unless a bootstrap switch structure is used. However, the power consumption and area overhead of the bootstrap switch structure are relatively large. Therefore, the Vcm-based method is not suitable for SAR ADC design with low power supply voltage.

[0053] like Figure 5 As shown, based on the Vcm-based capacitor switching timing, the present invention proposes an improved capacitor switching timing scheme. For the improved capacitor switching timing, an N-bit differential SAR ADC requires 2 N The number of unit capacitors required is reduced by half compared to the traditional capacitor switching sequence, which is the same as the monotonic capacitor switching sequence and the Vcm-based capacitor switching sequence. Compared with the Vcm-based, the improved capacitor array structure divides each bit of capacitor into two, forming two equal capacitors. These two equal capacitors can achieve three different voltage connections by connecting the lower plate to different potentials, namely Vref, 1 / 2Vref and GND.

[0054] Specifically, Figure 5 As shown, the present invention discloses a Vcm-based capacitor switch timing circuit, comprising: a first capacitor array 1, a second capacitor array 2, a first input terminal Vip, a second input terminal Vin and a comparator 5;

[0055] The first capacitor array 1 comprises an array-first capacitor group, an array-second capacitor group, ..., an array-j-th capacitor group and an array-dummy capacitor group connected in parallel in sequence; the lower plates of the array-first capacitor group, the array-second capacitor group, ..., the array-j-th capacitor group and the array-dummy capacitor group are connected to Vref or GND, and the upper plates are connected to the first input terminal Vip and the in-phase input terminal of the comparator 5;

[0056] The second capacitor array 2 includes an array second first capacitor group, an array second second capacitor group, ..., an array second j-th capacitor group and an array second dummy capacitor group, which are sequentially connected in parallel; the lower plates of the array second first capacitor group, the array second second capacitor group, ..., the array second j-th capacitor group and the array second dummy capacitor group are connected to Vref or GND, and the upper plates are connected to the second input terminal Vin and the inverting input terminal of the comparator 5;

[0057] The array one first capacitor group, array one second capacitor group, ... array one i-th capacitor group, array two first capacitor group, array two second capacitor group, ... array two j-th capacitor group, array one dummy capacitor group and array two dummy capacitor group all include two capacitors of equal capacitance connected in parallel.

[0058] In a preferred embodiment, the array-a dummy capacitor group includes a capacitor CP1 and a capacitor CP2 connected in parallel, and the capacitance of the capacitor CP1 and the capacitor CP2 are both 1 / 2C.

[0059] More preferably, the second dummy capacitor group of the array includes a capacitor CN1 and a capacitor CN2 connected in parallel, and the capacitance of the capacitor CN1 and the capacitance of the capacitor CN2 are both 1 / 2C.

[0060] Furthermore, the array first i-th capacitor group includes capacitor CP i2 And capacitor CP i1 , the capacitance CP i2 And capacitor CP i1 The capacitance value is 2 N-3 C, where N=i, 3≤i≤8. The second j-th capacitor group of the array includes capacitor CP j2 And capacitor CP j1 , the capacitance CP j2 And capacitor CP j1 The capacitance value is 2 N-3 C, where N=j, 3≤j≤8.

[0061] In addition, the Vcm-based capacitor switch timing circuit also includes a first switch group 3, and the lower plates of the array 1 first capacitor group, array 1 second capacitor group, ... array 1 jth capacitor group and array 1 dummy capacitor group can be connected to the Vref or GND through the first switch group 3. The Vcm-based capacitor switch timing circuit also includes a second switch group 4, and the lower plates of the array 2 first capacitor group, array 2 second capacitor group, ... array 2 jth capacitor group and array 2 dummy capacitor group can be connected to the Vref or GND through the second switch group 4.

[0062] The Vcm-based capacitor switch timing circuit further includes a SAR logic circuit 6 ; an input end of the SAR logic circuit 6 is electrically connected to an output end of the comparator 5 , and the SAR logic circuit 6 communicates with the first switch group 3 and the second switch group 4 .

[0063] In a preferred embodiment, i=j=8.

[0064] Example 2

[0065] In order to illustrate the scheme of the present invention, it is explained by the following examples:

[0066] With 2 N-3 C capacitor group is taken as an example to explain the specific principle of the technical solution of the present invention:

[0067] The sampling phase, such as Figure 6 As shown, the first two capacitors of the capacitor array connected to the negative input of the comparator N-3 The lower plate of capacitor C is grounded, and the second 2 N-3 The lower plate of capacitor C is connected to Vref; the upper plate is connected to the input terminal of Vin. N-3 The capacitor C can be equivalent to an upper plate connected to Vin and a lower plate connected to Vcm = 1 / 2Vref. N-2 The capacitance of C is calculated below to verify the rationality of the equivalence:

[0068] For the circuit on the left, the charge Q1 stored on the capacitor is:

[0069] Q1=2 N-3 C×(Vin-Vref)+2 N-3 C×Vin=2 N-2 C×Vin-2 N-3 C×Vref

[0070] For the circuit on the right, the charge Q2 stored on the capacitor is:

[0071]

[0072] It can be seen that Q1=Q2, so the rationality of the equivalent circuit is verified.

[0073] The improved Vcm-based capacitor array in the present invention is equivalent to the equivalent circuit as shown in FIG. Figure 7 As shown, it can be seen that its structure is basically the same as that of Vcm-based, Vcm = 1 / 2Vref. However, it does not require an additional common-mode voltage generation circuit, is suitable for low power supply voltage design, and solves the problem of Vcm-based capacitor switching timing.

[0074] During the sampling phase, the states of all switches are as follows: Figure 8 As shown in the figure, the lower plates of the same group of capacitors are connected to Vref and GND respectively, and the upper plates sample the input signal at the same time. In the sampling stage, the equivalent circuit structure diagram is as follows Fig. 9 As shown, it is equivalent to that the lower plates of all capacitors are connected to Vcm, and the upper plates sample the input signal. After the sampling is completed, the sampling switch is disconnected, and the comparator directly performs the first comparison. If Vip is greater than Vin, MSB = 1, and at the same time, the lower plates of the largest capacitor array at the positive input end of the comparator are all grounded. In the improved structure, it is equivalent to that the lower plates of the same group of capacitor arrays are all grounded; the lower plate of the largest capacitor at the negative input end of the comparator is connected to Vref, and in the improved structure, it is equivalent to that the lower plates of the same group of capacitor arrays are all connected to Vref (the same below); otherwise MSB = 0, and at the same time, the lower plate of the largest capacitor array at the positive input end of the comparator is connected to Vref, and the lower plate of the largest capacitor at the negative input end of the comparator is grounded. Then the comparator starts the second comparison and obtains the MSB-1 bit digital code. This process is repeated until the LSB is determined. Compared with the Vcm-based capacitor switching timing, the improved Vcm-based capacitor switching timing does not require additional circuits to generate the common-mode level Vcm, does not require a complex bootstrap switch structure, reduces power consumption and area, and is suitable for low-voltage SAR ADC design.

[0075] The present invention divides the bit capacitance in the Vcm-based capacitor switch timing into two equal capacitances and realizes the function of generating a common-mode level inside the circuit by setting a suitable switch state, thereby reducing the complexity of the circuit. Compared with the Vcm-based capacitor switch timing, the switch control structure is simplified and no common-mode voltage generation circuit is required, thereby reducing the power consumption and area of ​​the capacitor array. The capacitor switch timing is easy to combine with the existing technology, has high maturity, and has broad application prospects in high-precision, low-power successive approximation analog-to-digital converter circuits.

[0076] Example 3

[0077] In order to further explain the technical solution of the present invention, it is described by the following examples:

[0078] Fig.10 The following figure shows the possible conversion conditions of a 3-bit SAR A / D converter using the improved capacitor switching timing, and the switching energy consumed in each case is marked. A 3-bit differential SAR ADC only requires 8 unit capacitors, which is the same as the Vcm-based capacitor switching timing. During the sampling phase, the switching states of all capacitors are as follows: Fig.10 As shown in (a) in the figure. After sampling, the sampling switch is disconnected and the comparator directly performs the first comparison. If Vip is greater than Vin, then MSB = 1, and the switch states of all capacitors are as follows: Fig.10 As shown in (b), the switching consumption Otherwise, MSB=0, and the switch states of all capacitors are as follows: Fig.10 As shown in (c), the switching consumption Then the comparator starts the second comparison. If MSB = 1 and Vip is greater than Vin, then MSB-1 = 1, and the switch states of all capacitors are as follows: Fig.10 As shown in (d), the switching consumption Otherwise, MSB-1=0, and the switch states of all capacitors are as follows: Fig.10 As shown in (e), the switching consumption If MSB=0, and Vip is greater than Vin, then MSB-1=1, and the switching states of all capacitors are as follows: Fig.10 As shown in (f), the switching consumption Otherwise, MSB-1=0, and the switch states of all capacitors are as follows: Fig.10 As shown in (g), the switching consumption After that, a third comparison is performed based on the current capacitor switch state to determine the LSB value. In this way, the quantization process of the 3-bit SAR A / D converter using the improved capacitor switch timing is completed, and the next quantization can be performed after the capacitor switch is reset.

[0079] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A Vcm-based capacitor switch timing circuit, characterized in that: include: A first capacitor array (1), a second capacitor array (2), a first input terminal Vip, a second input terminal Vin and a comparator (5); The first capacitor array (1) comprises an array-first capacitor group, an array-second capacitor group, ..., an array-jth capacitor group and an array-dummy capacitor group, which are sequentially connected in parallel; the lower plates of the array-first capacitor group, the array-second capacitor group, ..., the array-jth capacitor group and the array-dummy capacitor group are connected to Vref and / or GND, and the upper plates are connected to the first input terminal Vip and the in-phase input terminal of the comparator (5); The second capacitor array (2) comprises a first capacitor group of array 2, a second capacitor group of array 2, ..., a j-th capacitor group of array 2 and a dummy capacitor group of array 2, which are sequentially connected in parallel; the lower plates of the first capacitor group of array 2, the second capacitor group of array 2, ..., the j-th capacitor group of array 2 and the dummy capacitor group of array 2 are connected to Vref and / or GND, and the upper plates are connected to the second input terminal Vin and the inverting input terminal of the comparator (5); The first capacitor group of array one, the second capacitor group of array one, ... the i-th capacitor group of array one, the first capacitor group of array two, the second capacitor group of array two, ... the j-th capacitor group of array two, the dummy capacitor group of array one and the dummy capacitor group of array two all include two capacitors of equal capacitance connected in parallel.

2. A Vcm-based capacitor switch timing circuit according to claim 1, characterized in that: The array-a dummy capacitor group includes a capacitor CP1 and a capacitor CP2 connected in parallel, and the capacitance of the capacitor CP1 and the capacitor CP2 are both 1 / 2C.

3. A Vcm-based capacitor switch timing circuit according to claim 1, characterized in that: The second dummy capacitor group of the array includes a capacitor CN1 and a capacitor CN2 connected in parallel, and the capacitance of the capacitor CN1 and the capacitance of the capacitor CN2 are both 1 / 2C.

4. A Vcm-based capacitor switch timing circuit according to claim 1, characterized in that: The array first i-th capacitor group includes a capacitor CP i1 And the capacitor CP i2 , the capacitance CP i1 And the capacitor CP i2 The capacitance value is 2 N-3 C, where N=i, 3≤i≤8.

5. The Vcm-based capacitor switch timing circuit according to claim 1, characterized in that: The second j-th capacitor group of the array includes a capacitor CP j1 And capacitor CP j2 , the capacitance CP j1 And capacitor CP j2 The capacitance value is 2 N-3 C, where N=j, 3≤j≤8.

6. A Vcm-based capacitor switch timing circuit according to claim 1, characterized in that: The Vcm-based capacitor switch timing circuit also includes a first switch group (3), and the lower plates of the array 1 first capacitor group, the array 1 second capacitor group, ..., the array 1 jth capacitor group and the array 1 dummy capacitor group are connected to the Vref and / or GND in an on-off manner through the first switch group (3).

7. A Vcm-based capacitor switch timing circuit according to claim 6, characterized in that: The Vcm-based capacitor switch timing circuit also includes a second switch group (4), and the lower plates of the first capacitor group of array 2, the second capacitor group of array 2, ..., the jth capacitor group of array 2, and the dummy capacitor group of array 2 are connected and disconnected to the Vref and / or GND through the second switch group (4).

8. A Vcm-based capacitor switch timing circuit according to claim 7, characterized in that: The Vcm-based capacitor switch timing circuit further comprises a SAR logic circuit (6); an input end of the SAR logic circuit (6) is electrically connected to an output end of the comparator (5), and the SAR logic circuit (6) communicates with the first switch group (3) and the second switch group (4).

9. The Vcm-based capacitor switch timing circuit according to claim 1, characterized in that: Said i=j=8.

10. A Vcm-based capacitor switch timing method, characterized in that: During sampling, the lower plate of one capacitor in the first capacitor group of array 1, the second capacitor group of array 1, ... the jth capacitor group of array 1 and the dummy capacitor group of array 1 is connected to Vref, and the other is connected to GND; The lower plate of a corresponding capacitor in the first capacitor group of array 2, the second capacitor group of array 2, ... the jth capacitor group of array 2 and the dummy capacitor group of array 2 is connected to GND, and the other corresponding capacitor is connected to Vref.

Images