Semiconductor device, method of manufacturing the same, and electronic apparatus

Abstract

The invention provides a semiconductor device, a manufacturing method thereof and an electronic device. The manufacturing method of the semiconductor device comprises the following steps: providing a wafer; forming a gate material layer, wherein the gate material layer covers all the surfaces of the wafer; oxidizing the surface of the gate material layer to form a protective layer; performing ion etching on the first surface of the wafer based on the mask layer defined with the gate pattern; and removing the protective layer to form a grid electrode on the first surface of the wafer. According to the invention, the smoothness of the gate material layer at the chamfer on the back of the wafer is improved, so that the binding force of subsequent deposited metal and chemical plating at the chamfer can be enhanced, and the risk of metal stripping is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof and an electronic device. Background Art

[0002] In the related art, after a gate material layer covering the entire wafer is deposited on the surface of the wafer, the surface of the gate material layer is oxidized to form an oxide layer, and then the oxide layer is removed by a wet process to repair the surface damage of the gate material layer. Then, a mask layer with a gate is defined on the front side of the wafer, and dry etching is performed in a plasma atmosphere to form a gate on the surface of the wafer.

[0003] However, due to the unstable plasma atmosphere at the junction of the side and back of the wafer, the gate material layer at the chamfer on the back of the wafer will be unevenly etched during plasma dry etching to form a bumpy morphology, and the subsequent metal deposition and chemical plating here are prone to peeling.

[0004] In view of the above technical problems, the present invention provides a new semiconductor device and a manufacturing method thereof and an electronic device. Summary of the invention

[0005] A series of simplified concepts are introduced in the Summary of the Invention, which will be further described in detail in the Detailed Description of the Invention. The Summary of the Invention does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.

[0006] In view of the existing problems, the present invention provides a method for manufacturing a semiconductor device, the manufacturing method comprising:

[0007] Provide wafers;

[0008] forming a gate material layer, wherein the gate material layer covers a first surface and a second surface opposite to each other, and a side surface of the wafer;

[0009] Oxidizing the surface of the gate material layer to form a protective layer;

[0010] Performing ion etching on the first surface of the wafer based on a mask layer defining a gate pattern;

[0011] The protection layer is removed to form a gate on the first surface of the wafer.

[0012] Another aspect of the present invention provides a method for manufacturing a semiconductor device, the method comprising:

[0013] Provide wafers;

[0014] forming a gate material layer, wherein the gate material layer covers a first surface and a second surface opposite to each other, and a side surface of the wafer;

[0015] Performing ion etching on the first surface of the wafer based on a mask layer defining a gate pattern to form a gate on the first surface of the wafer;

[0016] At least the surface of the gate material layer at the junction between the side surface of the wafer and the second surface is oxidized to repair the surface damage of the gate material layer at the junction.

[0017] In some embodiments of the present application, the gate material includes polysilicon.

[0018] In some embodiments of the present application, the step of performing ion etching on the first surface of the wafer based on the mask layer having the gate pattern defined thereon comprises:

[0019] forming a patterned mask layer on the first surface of the wafer, wherein the mask layer defines a pattern of the gate to be formed;

[0020] Ion etching is performed based on the mask layer to form a gate on the first surface of the wafer.

[0021] In some embodiments of the present application, when ion etching is performed, the interface between the side surface and the second surface of the wafer is in an unstable plasma atmosphere.

[0022] In some embodiments of the present application, removing the protective layer includes:

[0023] The protective layer on the surface of the gate material layer on the second surface and the side surface of the wafer and the protective layer on the surface of the gate are removed simultaneously by a wet etching process.

[0024] In some embodiments of the present application, the method for manufacturing a semiconductor device further comprises, after the oxidation step, using a wet etching process to remove the oxide layer formed in the oxidation step.

[0025] Another aspect of the present invention provides a semiconductor device manufactured by any one of the aforementioned methods for manufacturing a semiconductor device.

[0026] In some embodiments of the present application, the semiconductor device includes an insulated gate bipolar transistor.

[0027] Another aspect of the present invention provides an electronic device, comprising the aforementioned semiconductor device.

[0028] The method for manufacturing a semiconductor device of the present invention improves the smoothness of the gate material layer at the chamfered corner of the back side of the wafer, thereby enhancing the bonding strength of subsequent metal deposition and chemical plating at this location and reducing the risk of metal peeling. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The following drawings of the present invention are used to understand the present invention as part of the present invention. The embodiments of the present invention are shown in the drawings and the description thereof is used to explain the principle of the present invention.

[0030] In the attached figure:

[0031] Figures 1A to 1F The cross-sectional schematic diagram shows a structure obtained by sequentially implementing a method for manufacturing a semiconductor device in the related art.

[0032] Figure 2 A flowchart showing a method for manufacturing a semiconductor device according to a specific embodiment of the present invention is shown.

[0033] FIG. 3A to FIG. 3F A cross-sectional schematic diagram of a structure obtained by sequentially implementing a method for manufacturing a semiconductor device according to a specific embodiment of the present invention is shown.

[0034] Figure 4 A flow chart showing a method for manufacturing a semiconductor device according to another specific embodiment of the present invention.

[0035] Figure 5 A schematic diagram of an electronic device according to a specific embodiment of the present invention is shown. DETAILED DESCRIPTION

[0036] In the following description, a large number of specific details are provided to provide a more thorough understanding of the present invention. However, it is apparent to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present invention, some technical features well known in the art are not described.

[0037] It should be understood that the present invention can be implemented in different forms and should not be construed as being limited to the embodiments presented herein. On the contrary, providing these embodiments will make the disclosure thorough and complete and fully convey the scope of the present invention to those skilled in the art. In the accompanying drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. The same reference numerals throughout represent the same elements.

[0038] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0039] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0040] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present invention. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0041] In order to fully understand the present invention, detailed steps and structures will be presented in the following description to illustrate the technical solution proposed by the present invention. The preferred embodiments of the present invention are described in detail below, but in addition to these detailed descriptions, the present invention may also have other implementations.

[0042] In related technologies, such as Figure 1A to Figure 1F As shown, a wafer 111 is first provided, and then a gate material layer 112 is deposited on the surface of the wafer 111 to cover the entire wafer 111. The surface of the gate material layer 112 is then oxidized to form an oxide layer 113. The oxide layer 113 is then removed by a wet process to repair surface damage of the gate material layer 112. A mask layer with a gate 114 is defined on the front side of the wafer 111, and dry etching is performed in a plasma atmosphere to form a gate 114 on the surface of the wafer 111.

[0043] However, due to the unstable plasma atmosphere at the junction of the side and back of the wafer 111, the gate material layer 112 at the chamfer on the back of the wafer 111 will be unevenly etched during plasma dry etching to form a bumpy morphology. The subsequent metal deposited and chemical plating here are prone to peeling, resulting in abnormal wafer test circuits. Production personnel are required to manually scrape off the edge metal wire, which seriously affects product quality and delivery efficiency.

[0044] Therefore, in view of the existence of the above-mentioned technical problems, the present invention proposes a method for manufacturing a semiconductor device, such as Figure 2 As shown, including:

[0045] Step S11, providing a wafer;

[0046] Step S12, forming a gate material layer, wherein the gate material layer covers all surfaces of the wafer;

[0047] Step S13, oxidizing the surface of the gate material layer to form a protective layer;

[0048] Step S14, performing ion etching on the first surface of the wafer based on the mask layer defining the gate pattern;

[0049] Step S15, removing the protective layer to form a gate on the first surface of the wafer.

[0050] The manufacturing method of the semiconductor device of the present invention forms a protective layer on the surface of the gate material layer, first performs ion etching on the first surface of the wafer based on a mask layer defining a gate pattern, and then removes the protective layer. Therefore, when performing ion etching, the protective layer can protect the junction between the side and back of the gate material layer, ensuring that the gate material layer at the chamfer of the back side of the wafer is not damaged. Therefore, the gate material layer at the chamfer of the back side of the wafer will not be unevenly etched, and will not form a bumpy morphology, thereby improving the smoothness of the gate material layer at the chamfer of the back side of the wafer, and further enhancing the bonding strength of the subsequent metal deposition and chemical plating here, reducing the risk of metal peeling, thereby avoiding abnormal wafer test circuits, and eliminating the need for production personnel to manually scrape off edge metal wires, thereby improving product yield and shipment efficiency.

[0051] Embodiment 1

[0052] Below, reference FIG. 3A to FIG. 3F The method for manufacturing a semiconductor device of the present invention is described in detail, wherein: FIG. 3A to FIG. 3F A cross-sectional schematic diagram of a spreading resistance test sample obtained by sequentially implementing a preparation method according to a specific embodiment of the present invention is shown.

[0053] Exemplarily, the method for manufacturing a semiconductor device of the present invention comprises the following steps:

[0054] First, perform step 1, such as Figure 3A As shown, a wafer 211 is provided.

[0055] Among them, wafer 211 can be any suitable semiconductor wafer, such as a bulk silicon wafer, and it can also be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), or it can also be double-sided polished silicon wafers (Double Side Polished Wafers, DSP), or it can be ceramic wafers such as alumina, quartz or glass wafers, etc.

[0056] Next, execute step 2, such as Figure 3B As shown, a gate material layer 212 is formed, and the gate material layer 212 covers the first surface and the second surface opposite to each other, and the side surfaces of the wafer 211 .

[0057] Specifically, the wafer 211 may have a first surface and a second surface opposite to each other, and a side surface. In this embodiment, a gate material layer 212 is formed to cover the first surface and the second surface opposite to each other, and the side surface of the wafer 211, so that the gate material layer 212 covers all surfaces of the wafer 211. The first surface may refer to the front side of the wafer, and the second surface may refer to the back side of the wafer.

[0058] In this embodiment, gate material can be deposited on the first surface and the second surface relative to each other, and the side of the wafer 211 by any suitable deposition method to form a gate material layer 212 covering the first surface and the second surface relative to each other, and the side of the wafer 211, such as a physical vapor deposition method, a chemical vapor deposition method, an atomic layer deposition method, etc., without limitation.

[0059] In some embodiments, the gate material may be polysilicon, or may be any other suitable gate material such as a metal gate material, which is not limited thereto.

[0060] Next, execute step 3, such as Figure 3C As shown, the surface of the gate material layer 212 is oxidized to form a protection layer 213 .

[0061] The surface of the gate material layer 212 may be oxidized by heat treatment to form a protective layer 213 on the surface of the gate material layer 212. The specific heat treatment process may be as follows: at high temperature, the wafer 211 with all surfaces covered with the gate material layer 212 obtained after step 2 is exposed to oxygen or water vapor, so that the surface of the gate material layer 212 is oxidized at high temperature to form an oxide layer, which may also be referred to as a protective layer 213. Taking the gate material as polysilicon as an example, after the surface of the gate material layer 212 is oxidized, the protective layer 213 formed is a silicon dioxide layer.

[0062] In step 2, since the surface of the gate material layer 212 formed by deposition often has certain damage, in this embodiment, the protective layer 213 is first formed by oxidizing the surface of the gate material layer 212, and then the protective layer 213 on the surface of the gate material layer 212 is removed in combination with subsequent steps, thereby repairing the surface damage of the gate material layer 212. In addition, the formed protective layer 213 can protect the junction between the side and back of the gate material layer 212, so as to ensure that the gate material layer 212 at the chamfer of the back of the wafer 211 is not damaged when ion etching is performed in the subsequent steps.

[0063] Next, execute step 4, such as Figure 3D and Figure 3E As shown, ion etching is performed on the first surface of the wafer 211 based on the mask layer defining the pattern of the gate 214 .

[0064] In some embodiments, performing ion etching on the first surface of the wafer 211 based on the mask layer defining the pattern of the gate 214 may include the following steps S411 to S412:

[0065] In step S411 , a patterned mask layer is formed on the first surface of the wafer 211 , wherein the mask layer defines the pattern of the gate 214 to be formed.

[0066] In actual preparation, a photoresist mask layer may be formed on the first surface of the wafer 211 , and the photoresist mask layer may be patterned through processes such as exposure and development to form a mask layer that defines the pattern of the gate 214 to be formed.

[0067] In step S412 , ion etching is performed based on the mask layer to form a gate 214 on the first surface of the wafer 211 .

[0068] In actual preparation, plasma can be used to dry-etch the first surface of the wafer 211, and the protective layer 213 and the gate material layer 212 that are not blocked by the mask layer are removed by plasma, thereby leaving the protective layer 213 and the gate material layer 212 blocked by the mask layer, and removing the mask layer, that is, forming the gate 214 on the first surface of the wafer 211. The protective layer 213 remains on the surface of the formed gate 214.

[0069] It is worth noting that although the junction between the side and the back of the wafer 211 is an unstable plasma atmosphere when ion etching is performed, since a protective layer 213 is formed on the surface of the gate material layer 212, the protective layer 213 can protect the junction between the side and the back of the gate material layer 212, thereby ensuring that the gate material layer 212 at the chamfer on the back side of the wafer 211 is not damaged. Therefore, it can be ensured that the gate material layer 212 at the chamfer on the back side of the wafer 211 will not be unevenly etched, and will not form a bumpy morphology, thereby improving the smoothness of the gate material layer 212 at the chamfer on the back side of the wafer 211, thereby enhancing the bonding strength of the subsequent metal deposition and chemical plating here, and reducing the risk of metal peeling.

[0070] In some embodiments, in step S411 , the mask layer may define a pattern of a plurality of spaced gates 214 to be formed. Accordingly, after step S412 is performed, a plurality of spaced gates 214 are formed on the first surface of the wafer 211 .

[0071] Next, execute step 5, such as Figure 3F As shown, the protection layer 213 is removed to form a gate 214 on the first surface of the wafer 211 .

[0072] Specifically, the protective layer 213 on the surface of the gate material layer 212 and the protective layer 213 on the surface of the gate 214 on the second surface and side of the wafer 211 can be removed simultaneously by a wet etching process, thereby leaving the gate 214 on the first surface of the wafer 211 and leaving the gate material layer 212 on the second surface and part of the side of the wafer 211, and the remaining gate material layer 212 covers the chamfer of the second surface of the wafer 211.

[0073] In addition, in step 4, if a plurality of gates 214 with a protective layer 213 are formed on the first surface of the wafer 211 at intervals, after removing the protective layer 213 in step 5, a plurality of gates 214 with intervals can be formed on the first surface of the wafer 211.

[0074] It is worth mentioning that the order of the above steps is only an example. Under the premise of no conflict, the order of the above steps can also be swapped or performed alternately.

[0075] This completes the introduction to the key manufacturing method of the semiconductor device of the present invention. The production of a complete device requires other preceding steps, intermediate steps or subsequent steps, such as the subsequent steps of forming the source and drain, the steps of forming a metal chemical plating layer, etc., which will not be repeated here.

[0076] In summary, the manufacturing method of the semiconductor device of the present invention forms a protective layer 213 on the surface of the gate material layer 212, first performs ion etching on the first surface of the wafer 211 based on the mask layer defining the pattern of the gate 214, and then removes the protective layer 213. Therefore, when performing ion etching, the protective layer 213 can protect the junction between the side and back of the gate material layer 212 to ensure that the gate material layer 212 at the chamfer of the back side of the wafer 211 is not damaged. Therefore, the gate material layer 212 at the chamfer of the back side of the wafer 211 will not be unevenly etched, and will not form a bumpy morphology, thereby improving the smoothness of the gate material layer 212 at the chamfer of the back side of the wafer 211, thereby enhancing the bonding strength of the subsequent metal deposition and chemical plating here, and reducing the risk of metal peeling.

[0077] Embodiment 2

[0078] The present invention also provides a method for manufacturing a semiconductor device, such as Figure 4 As shown, including:

[0079] Step S21, providing a wafer;

[0080] Step S22, forming a gate material layer, wherein the gate material layer covers all surfaces of the wafer;

[0081] Step S23, performing ion etching on the first surface of the wafer based on the mask layer having the gate pattern defined thereon, so as to form a gate on the first surface of the wafer;

[0082] Step S24, oxidizing at least the surface of the gate material layer at the junction between the side surface and the second surface of the wafer to repair surface damage of the gate material layer at the junction.

[0083] The manufacturing method of the semiconductor device of the present invention forms a gate on the first surface of the wafer first, and then oxidizes the surface of the gate material layer at the junction of the side surface and the second surface of the wafer to repair the surface damage of the gate material layer at the junction, thereby improving the smoothness of the gate material layer at the chamfer of the back side of the wafer, and further enhancing the bonding strength of the subsequent metal deposition and chemical plating at this location, reducing the risk of metal peeling, thereby avoiding abnormal wafer test circuits, eliminating the need for production personnel to manually scrape off edge metal wires, and improving product yield and shipment efficiency.

[0084] In the following, the manufacturing method of the semiconductor device of the present invention is described in detail. To avoid repetition, the same components and structures as those in the first embodiment are only briefly described, and the specific explanation and description thereof can refer to the description in the first embodiment.

[0085] Exemplarily, the method for manufacturing a semiconductor device of the present invention comprises the following steps:

[0086] First, perform step 1 to provide a wafer.

[0087] Among them, the wafer can be any suitable semiconductor wafer, such as a bulk silicon wafer, and it can also be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), or it can also be double-sided polished silicon wafers (Double Side Polished Wafers, DSP), or it can be ceramic wafers such as alumina, quartz or glass wafers, etc.

[0088] Next, step 2 is performed to form a gate material layer, wherein the gate material layer covers the first surface and the second surface opposite to each other, as well as the side surfaces of the wafer.

[0089] Specifically, the wafer may have a first surface and a second surface opposite to each other, and a side surface. In this embodiment, a gate material layer is formed to cover the first surface and the second surface opposite to each other, and the side surface of the wafer, so that the gate material layer covers all surfaces of the wafer. The first surface may refer to the front side of the wafer, and the second surface may refer to the back side of the wafer.

[0090] In this embodiment, gate material can be deposited on the first surface and the second surface relative to each other, and the side of the wafer by any suitable deposition method to form a gate material layer covering the first surface and the second surface relative to each other, and the side of the wafer, such as a physical vapor deposition method, a chemical vapor deposition method, an atomic layer deposition method, etc., without limitation.

[0091] In some embodiments, the gate material may be polysilicon, or may be any other suitable gate material such as a metal gate material, which is not limited thereto.

[0092] Next, step three is performed to perform ion etching on the first surface of the wafer based on the mask layer defining the gate pattern, so as to form a gate on the first surface of the wafer.

[0093] In some embodiments, performing ion etching on the first surface of the wafer based on the mask layer having the gate pattern defined thereon may include the following steps S311 to S312:

[0094] Step S311 , forming a patterned mask layer on the first surface of the wafer, wherein the mask layer defines a pattern of a gate to be formed.

[0095] In actual preparation, a photoresist mask layer may be formed on the first surface of the wafer, and the photoresist mask layer may be patterned through processes such as exposure and development to form a mask layer that defines the pattern of the gate to be formed.

[0096] In step S312 , ion etching is performed based on the mask layer to form a gate on the first surface of the wafer.

[0097] In actual preparation, plasma can be used to dry etch the first surface of the wafer, and the gate material layer not blocked by the mask layer can be removed by plasma, thereby leaving the gate material layer blocked by the mask layer, and removing the mask layer to form a gate on the first surface of the wafer.

[0098] It is worth mentioning that due to the unstable plasma atmosphere at the junction of the side and back of the wafer, the gate material layer at the chamfer on the back of the wafer will be unevenly etched during plasma dry etching to form a bumpy morphology. The subsequent metal deposited and chemical plating here are prone to peeling, resulting in abnormal wafer test circuits. Production personnel are required to manually scrape off the edge metal wire, which seriously affects product quality and delivery efficiency.

[0099] In addition, in step three, a plurality of gates spaced apart from each other may be formed on the first surface of the wafer.

[0100] Next, step four is performed to oxidize at least the surface of the gate material layer at the junction between the side surface of the wafer and the second surface to repair the surface damage of the gate material layer at the junction.

[0101] The surface of the gate material layer may be oxidized by heat treatment to form an oxide layer on the surface of the gate material layer. The specific heat treatment process may be as follows: at high temperature, the device obtained after step 3 is exposed to oxygen or water vapor, so that the surface of the gate material layer is oxidized at high temperature to form an oxide layer. Taking the gate material as polysilicon as an example, after the surface of the gate material layer is oxidized, the protective layer formed is a silicon dioxide layer.

[0102] It should be noted that, in addition to the surface of the gate material layer being oxidized into an oxide layer, the surface of the gate may also be oxidized into an oxide layer.

[0103] In step three, since the junction between the side and the back of the wafer is an unstable plasma atmosphere, the gate material layer at the chamfer of the back of the wafer will be unevenly etched to form a bumpy morphology during plasma dry etching. In this embodiment, by oxidizing the surface of the gate material layer at the junction of the side and the second surface of the wafer, and then removing the oxide layer, the surface damage of the gate material layer can be repaired, and the smoothness of the gate material layer at the chamfer of the back of the wafer can be improved.

[0104] Among them, after the oxidation step, a wet etching process can be used to remove the oxide layer formed in the oxidation step, thereby leaving a gate on the first surface of the wafer and leaving a gate material layer on the second surface and part of the side of the wafer, and the remaining gate material layer covers the chamfer of the second surface of the wafer.

[0105] This completes the introduction to the key manufacturing method of the semiconductor device of the present invention. The production of a complete device requires other preceding steps, intermediate steps or subsequent steps, such as the subsequent steps of forming the source and drain, the steps of forming a metal chemical plating layer, etc., which will not be repeated here.

[0106] In summary, the manufacturing method of the semiconductor device of the present invention first forms a gate on the first surface of the wafer, and then oxidizes the surface of the gate material layer at the junction of the side and the second surface of the wafer to repair the surface damage of the gate material layer at the junction, thereby improving the smoothness of the gate material layer at the chamfer on the back side of the wafer, and further enhancing the bonding strength of the subsequent metal deposition and chemical plating here, reducing the risk of metal peeling, thereby avoiding abnormal wafer test circuits, and eliminating the need for production personnel to manually scrape off edge metal wires, thereby improving product yield and shipment efficiency.

[0107] Embodiment 3

[0108] The present invention also provides a semiconductor device, which can be prepared by the method in the above-mentioned embodiment 1 or 2.

[0109] Below, reference Figure 3F The semiconductor device of the present invention is introduced and described in detail. It is worth mentioning that in order to avoid repetition, only a brief description is given for the same components and structures as in the aforementioned embodiment one or two. For specific explanations and descriptions, reference can be made to the description in embodiment one.

[0110] Specifically, Figure 3F As shown, the semiconductor device of the present invention includes a wafer 211 , a gate 214 is formed on the first surface of the wafer 211 , a gate material layer 212 is formed on the second surface of the wafer 211 , and the gate material layer 212 covers the chamfer of the second surface of the wafer 211 .

[0111] In some embodiments, a plurality of gates 214 are formed on the first surface of the wafer 211 and are spaced apart from each other.

[0112] In some embodiments, the semiconductor device may include an insulated gate bipolar transistor (IGBT). Of course, this embodiment does not limit the semiconductor device and may also include other types of devices, which is not limited.

[0113] According to the semiconductor device of the present invention, the method of embodiment one or two is adopted to prepare the gate material layer 212 at the chamfer on the back side of the wafer 211, thereby improving the smoothness of the gate material layer 212, thereby enhancing the bonding strength of the subsequent metal deposition and chemical plating at this location, reducing the risk of metal peeling, thereby avoiding abnormal wafer test circuits, eliminating the need for production personnel to manually scrape off the edge metal wires, and improving product yield and shipment efficiency.

[0114] Embodiment 4

[0115] Another embodiment of the present invention provides an electronic device, comprising the aforementioned semiconductor device, wherein the semiconductor device is manufactured according to the aforementioned method.

[0116] The electronic device of this embodiment can be any electronic product or device such as a mobile phone, a tablet computer, a laptop computer, a netbook, a game console, a television, a VCD, a DVD, a navigator, a digital photo frame, a camera, a video camera, a voice recorder, an MP3, an MP4, a PSP, etc., or any intermediate product including a circuit. The electronic device of the embodiment of the present invention has better performance because the above-mentioned semiconductor device is used.

[0117] in, Figure 5 An example of a mobile phone handset is shown. The mobile phone handset 400 is provided with a display portion 402 included in a housing 401, operation buttons 403, an external connection port 404, a speaker 405, a microphone 406, and the like.

[0118] The mobile phone comprises the semiconductor device described in the third embodiment. For the introduction of the semiconductor device, reference can be made to the description in the third embodiment, which will not be repeated here.

[0119] The present invention has been described by the above embodiments, but it should be understood that the above embodiments are only for the purpose of example and description, and are not intended to limit the present invention to the scope of the described embodiments. In addition, it can be understood by those skilled in the art that the present invention is not limited to the above embodiments, and more variations and modifications can be made according to the teachings of the present invention, and these variations and modifications all fall within the scope of the protection claimed by the present invention. The protection scope of the present invention is defined by the attached claims and their equivalents.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: The manufacturing method comprises: Provide wafers; forming a gate material layer, wherein the gate material layer covers a first surface and a second surface opposite to each other, and a side surface of the wafer; Oxidizing the surface of the gate material layer to form a protective layer; Performing ion etching on the first surface of the wafer based on a mask layer defining a gate pattern; The protection layer is removed to form a gate on the first surface of the wafer.

2. A method for manufacturing a semiconductor device, characterized in that: The manufacturing method comprises: Provide wafers; forming a gate material layer, wherein the gate material layer covers a first surface and a second surface opposite to each other, and a side surface of the wafer; Performing ion etching on the first surface of the wafer based on a mask layer defining a gate pattern to form a gate on the first surface of the wafer; At least the surface of the gate material layer at the junction between the side surface of the wafer and the second surface is oxidized to repair the surface damage of the gate material layer at the junction.

3. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein: The gate material includes polysilicon.

4. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein: The method of performing ion etching on the first surface of the wafer based on a mask layer having a gate pattern defined thereon comprises: forming a patterned mask layer on the first surface of the wafer, wherein the mask layer defines a pattern of the gate to be formed; Ion etching is performed based on the mask layer to form a gate on the first surface of the wafer.

5. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein: When ion etching is performed, the interface between the side surface and the second surface of the wafer is in an unstable plasma atmosphere.

6. The method for manufacturing a semiconductor device according to claim 1, wherein: The removing of the protective layer comprises: The protective layer on the surface of the gate material layer and the protective layer on the surface of the gate on the second surface and the side surface of the wafer are removed simultaneously by a wet etching process.

7. The method for manufacturing a semiconductor device according to claim 2, wherein: The method further comprises, after the oxidation step, using a wet etching process to remove the oxide layer formed in the oxidation step.

8. A semiconductor device, characterized in that: The semiconductor device is prepared by the method for manufacturing a semiconductor device according to any one of claims 1 to 7.

9. The semiconductor device according to claim 8, characterized in that The semiconductor device includes an insulated gate bipolar transistor.

10. An electronic device, characterized in that: The electronic apparatus includes the semiconductor device according to claim 8 or 9.

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