Page replacement method and system of self-adaptive NAND flash memory

Abstract

The invention discloses a page replacement method and system of a self-adaptive NAND flash memory. The method comprises the steps of obtaining related information of an access page; judging whether the page is a new page or a page without the access historical record; if yes, the pages are marked, and the marked pages are inserted into two cache queues; when the queue containing all the LIR pages and the HIR pages is full of the stack, a victim page is selected from the other queue, and the victim page is processed; trimming and stacking a queue containing all the LIR pages and the HIR pages; performing self-learning to adjust the cache amount of the HIR page; judging whether the cache amount of the current HIR page is equal to the target cache amount or not; if yes, ending; if not, the victim page is selected from the other queue, and the victim page is processed. By implementing the method provided by the invention, the characteristics of the NAND flash memory are adapted, the asymmetric cost of reading and writing operations is considered, and the service life of the NAND flash memory is prolonged, so that the optimal overall performance is achieved.

Description

Technical Field

[0001] The present invention relates to a solid state hard disk, and more specifically to a page replacement method and system for an adaptive NAND flash memory. Background Art

[0002] NAND flash memory, as an electronic non-volatile storage medium, is organized in blocks, each of which typically contains multiple pages ranging in size from 256KB to 20MB. Its structure allows read and program commands to be executed on a page basis, but erase operations are performed at the block level containing multiple pages. This means that the entire block must be erased before any page is written. In general, the speed of write operations is much lower than that of read operations, and the latency of write operations is about seven times that of read operations. In addition, erase operations take longer than write operations, and the speed difference between the two can reach several orders of magnitude. NAND flash memory has a relatively small number of erase cycles, usually between 10,000 and 100,000 erase cycles, so its service life is limited. Compared with read operations, write and erase operations are much more expensive, especially erase operations, which consume a lot of time and energy and have a serious impact on the life of NAND flash memory.

[0003] When doing page processing, the performance gap between the processor and the disk makes traditional storage systems unable to meet the needs of high-performance computing. Although NAND flash memory performs well in read speed, it has obvious performance bottlenecks in write and erase operations. The read operation cost of NAND flash memory is low, while the write and erase operation cost is high. Existing cache replacement algorithms often only focus on improving cache hit rate or reducing the number of writes, ignoring the asymmetric cost characteristics of read and write operations, resulting in unnecessary increase in I / O costs. NAND flash memory has a limited number of erase times, and frequent erase operations will significantly shorten its service life. Existing cache strategies have failed to effectively extend the life of NAND flash memory, affecting the long-term reliability of the system. Although setting a cache area for data pages between the operating system and NAND flash memory can reduce I / O operations, the memory used for cache is high in price and small in capacity, which is not the optimal solution. Existing cache replacement algorithms fail to make full use of historical information to predict future access patterns, resulting in inefficient cache management.

[0004] Therefore, it is necessary to design a new method to adapt to the characteristics of NAND flash memory, take into account the asymmetric costs of read and write operations, and extend the service life of NAND flash memory to achieve the best overall performance. Summary of the invention

[0005] The purpose of the present invention is to overcome the defects of the prior art and provide a method and system for adaptive NAND flash memory page replacement.

[0006] To achieve the above object, the present invention adopts the following technical solution: a page replacement method of an adaptive NAND flash memory, comprising: Get information about the visited page; Determine whether the page is a new page or a page with no access history according to the access page related information; If the page is a new page or a page with no access history, mark the page and insert the marked page into two cache queues, one of which contains all LIR pages and HIR pages, and the other contains all resident HIR pages; When the queue containing all LIR pages and HIR pages is full, a victim page is selected from another queue and processed; Prune the stack of queues containing all LIR pages and HIR pages; Self-learning to adjust the cache size of HIR pages; Determine whether the current cache size of the HIR page is equal to the target cache size; If the current cache size of the HIR page is equal to the target cache size, then enter the end step; If the current cache size of the HIR page is not equal to the target cache size, the step of selecting a victim page from another queue is performed, and the victim page is processed.

[0007] A further technical solution is: after judging whether a page is a new page or a page without a visit history according to the access page related information, it also includes: If the page is neither a new page nor a page without access history, the page status is updated, and the stack pruning of the queue containing all LIR pages and HIR pages is performed.

[0008] A further technical solution is that marking the page and inserting the marked page into the queue comprises: The page is marked as a HIR page, and the marked page is inserted into two cache queues.

[0009] A further technical solution is: selecting a victim page from another queue and processing the victim page comprises: Select the page at the bottom of the other queue as the victim page; When the victim page is a clean page, the victim page is evicted; when the victim page is a dirty page and the corresponding deep cold flag is 0, the victim page is retained in the current queue and the corresponding deep cold flag is set to 1; when the victim page is a dirty page and the corresponding deep cold flag is 1, the victim page is evicted.

[0010] A further technical solution is: the pruning stack of the queues containing all LIR pages and HIR pages includes: Traverse the queue containing all LIR pages and HIR pages from bottom to top, convert HIR pages to LIR state, evict dirty pages with a deep cold flag of 1, convert clean pages or pages with a deep cold flag of 0 to LIR state, and move them to the top of the queue.

[0011] A further technical solution is: the self-learning adjustment of the cache amount of the HIR page includes: Calculate the cache size of the HIR page after each page access to get the new cache size; The adjust_Lh_process() function is called according to the new cache amount to check whether the cache amount of the current HIR page needs to be adjusted.

[0012] A further technical solution is: the calculation of the cache amount of the HIR page after each page access to obtain a new cache amount includes: use Calculate the cache size of the HIR page after each page access to get the new cache size, where Lbuf is the cache size given in page units, and L' hir is the new cache size; R rw is the read / write ratio.

[0013] The further technical solution is: calling the function adjust_Lh_process() according to the new cache amount to check whether the cache amount of the current HIR page needs to be adjusted, including: When the current cache amount of HIR pages is greater than the new cache amount, pages are selected for deletion from the queue containing all resident HIR pages. When the current cache amount of HIR pages is less than the new cache amount, the LIR page at the bottom of the queue containing all LIR pages and HIR pages is converted to the HIR page at the top of the queue containing all resident HIR pages.

[0014] The present invention also provides an adaptive NAND flash memory page replacement system, comprising: An information acquisition unit, used to acquire information related to the visited page; A page determination unit, used to determine whether a page is a new page or a page without a visit history record according to the access page related information; a marking unit, for marking the page if the page is a new page or a page without an access history, and inserting the marked page into two cache queues, one of which contains all LIR pages and HIR pages, and the other contains all resident HIR pages; a victim page selection unit, configured to select a victim page from another queue and process the victim page when the queue including all LIR pages and HIR pages is full; A pruning unit, for pruning the stack of queues containing all LIR pages and HIR pages; A self-learning unit, used for self-learning to adjust the cache amount of HIR pages; The cache amount judgment unit is used to judge whether the cache amount of the current HIR page is equal to the target cache amount; if the cache amount of the current HIR page is equal to the target cache amount, then enter the end step; if the cache amount of the current HIR page is not equal to the target cache amount, then execute the selection of the victim page from another queue and process the victim page.

[0015] The present invention further provides a computer device, which includes a memory and a processor. The memory stores a computer program, and the processor implements the above method when executing the computer program.

[0016] Compared with the prior art, the beneficial effects of the present invention are as follows: the present invention determines whether a page is a new page or has no access record by obtaining page access information, and if so, marks and inserts the page into a queue containing LIR and HIR pages and a queue containing resident HIR pages; when the LIR and HIR page queues are full, selects a victim page from the resident HIR page queue for processing, giving priority to dirty pages to reduce unnecessary write operations; the LIR and HIR page queues are pruned to ensure a reasonable queue structure and reduce frequent replacements due to queue overflow; the cache size of the HIR page is dynamically adjusted using a self-learning mechanism to adapt to the optimal performance requirements under different workload modes; the cache size of the HIR page is continuously monitored and adjusted to a target value to ensure that the cache strategy can both maximize the hit rate and minimize the write cost; the cache management is optimized through the above process, the read and write operation costs are effectively balanced, and the service life of the NAND flash memory is extended, thereby achieving the optimization of the overall system performance.

[0017] The present invention is further described below in conjunction with the accompanying drawings and specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying any creative work.

[0019] Figure 1 A schematic flow chart of a method for replacing a page of an adaptive NAND flash memory provided by an embodiment of the present invention; Figure 2 An example diagram of page specifications of IRR and R provided in an embodiment of the present invention; Figure 3 A structural diagram of an S sequence and a Q sequence provided in an embodiment of the present invention; Figure 4 Schematic diagram of the insertion strategy, promotion strategy and victim selection strategy provided by the embodiment of the present invention Figure 1 ; Figure 5 Schematic diagram of the insertion strategy, promotion strategy and victim selection strategy provided by the embodiment of the present invention Figure 2 ; Figure 6 A schematic block diagram of an adaptive NAND flash memory page replacement system provided by an embodiment of the present invention; Figure 7 A schematic block diagram of a computer device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0020] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0021] It should be understood that when used in this specification and the appended claims, the terms "include" and "comprises" indicate the presence of described features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof.

[0022] It should also be understood that the terms used in this specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used in the specification of the present invention and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms.

[0023] It should be further understood that the term "and / or" used in the present description and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

[0024] See also Figure 1 , Figure 1 A schematic flow chart of an adaptive NAND flash memory page replacement method provided in an embodiment of the present invention is provided. The method is applied in a solid state drive to adapt to the characteristics of the NAND flash memory, take into account the asymmetric costs of read and write operations, and extend the service life of the NAND flash memory, thereby achieving optimal overall performance.

[0025] Figure 1 FIG. 1 is a flow chart of a method for replacing a page of an adaptive NAND flash memory provided by an embodiment of the present invention. Figure 1 As shown, the method includes the following steps S110 to S180.

[0026] S110, obtaining information related to the accessed page.

[0027] In this embodiment, the access page related information may include a page ID, a version number, and a last modified time, etc., to determine whether it is a new page or a page with an existing access history record.

[0028] S120: Determine whether the page is a new page or a page with no access history according to the access page related information.

[0029] In this embodiment, the creation time of the page is compared with the current time. If the page creation time is very close to the current time, it is a new page. The user's access history is checked to see if there is a record of the same page access. The total number of page visits is checked. If it is the first visit, it is considered to be a new page or a page with no access history.

[0030] S130. If the page is a new page or a page with no access history, mark the page and insert the marked page into two cache queues, one of which contains all LIR pages and HIR pages, and the other contains all resident HIR pages.

[0031] In this embodiment, two cache queues are constructed based on LIRS (Least Recently Used with Inter-Reference Recency), where the LIRS algorithm uses a parameter called IRR (Inter-Reference Recency) to determine the reference pattern of pages. IRR is defined as the number of different pages accessed between two consecutive references to the same page. Figure 2 As shown, for example, if the system accessed page 1 and page 2 before the last access to page 9, then the IRR of page 9 is 2. This measurement method helps to identify pages that are not frequently used, because pages with larger IRRs are often not frequently accessed, so when selecting replacement pages, pages with smaller IRRs should be given priority.

[0032] In addition, the LIRS algorithm introduces a variable called R (Recency) to measure the recent use of the page. The R value represents the number of different pages that have been passed from the last time a page was accessed to the current point in time. For example, if the R value of page 9 is 2, this means that the system has accessed two different other pages since page 9 was last accessed. Since the traditional LRU (Least Recently Used) algorithm only considers the recent use of the page and ignores other historical access information, it performs poorly in some scenarios. In contrast, LIRS can more flexibly adjust the status of all referenced pages by integrating multiple sources of historical access information, thereby significantly improving the I / O performance of the storage system.

[0033] In the specific implementation of the LIRS algorithm, all accessed pages are divided into two main sets: the High IRR (HIR) set and the Low IRR (LIR) set. The HIR set occupies a relatively small space, and the pages in it are usually evicted quickly. Figure 3 and Figure 4 As shown, LIRS maintains two LRU queues, namely the Q queue and the S queue. The Q queue is used to record all resident HIR pages, while the S queue contains all LIR pages and HIR pages (HIR pages are further divided into two types: resident HIR pages, i.e., page data and its metadata are stored in the cache; non-resident HIR pages, i.e., only metadata is stored in the cache). The R value of all HIR pages in the S queue is less than the maximum R value of the LIR page. Among them, Figure 3 It means that when page 7 is not in the S queue, page 5 is evicted and page 3 is set to the deep cold state flag; Figure 4This means that when accessing the high IRR (HIR) page 3 in the S queue, the page state changes to low IRR (LIR) and the stack is pruned. When accessing the LIR page 4 in the S queue, the page is inserted at the top of the S queue and the stack is pruned.

[0034] When the system needs to reference a new page that does not exist in the S queue, the page will be marked as HIR and added to the front of the Q queue. If a page that is already in the Q queue but not in the S queue is accessed again, it will be moved to the front of the Q queue while keeping its HIR status unchanged. However, if a page in the S queue is re-referenced, the page will be promoted to the front of the queue and its status will be changed from any previous status to LIR. During the page eviction process, the HIR page at the end of the Q queue will be removed. If the page also exists in the S queue, its status will be changed to non-resident. In this way, the LIRS algorithm effectively manages the pages in the cache and optimizes the efficiency of resource utilization.

[0035] In this embodiment, if Figure 4 As shown in Figure 1, when a new page or a page with no access history is accessed, it is placed at the top of the Q queue and the S queue and marked as a HIR page. In addition, when a non-resident HIR page is accessed after not being referenced for a long time, it is inserted at the top of the S queue and its status is changed to LIR.

[0036] When a hit occurs, the LIR page will be promoted to the top of the S queue. The HIR page that left a history mark in the S queue will be promoted to the top of the queue and marked as LIR. On the other hand, the HIR page that is not in the S queue will be promoted to the top of the Q queue without changing its status.

[0037] S140: When the queue including all LIR pages and HIR pages is full, a victim page is selected from another queue and processed.

[0038] In this embodiment, the victim page refers to a page that needs to be processed.

[0039] In one embodiment, if Figure 5 As shown, the above-mentioned step S140 may include steps S141-S142.

[0040] S141, selecting a page at the bottom of another queue as a victim page; S142. When the victim page is a clean page, evict the victim page; when the victim page is a dirty page and the corresponding deep cold flag is 0, retain the victim page in the current queue and set the corresponding deep cold flag to 1; when the victim page is a dirty page and the corresponding deep cold flag is 1, evict the victim page.

[0041] In this embodiment, this example adopts the P-LIRS (Probability-based LIRS) algorithm to replace the page, which is an improved LIRS algorithm designed to optimize flash-based database operations, especially in the case of asymmetric read and write operations, to improve the buffer hit rate and reduce the cost of write operations.

[0042] In the LIRS (Least Recently Used) algorithm, when the buffer space is insufficient, the system selects a page for replacement, and the pages at the bottom of the Q queue are considered "victims" and these pages will be replaced. If the page is also in the S queue, its status will be updated to non-resident. The traditional LIRS algorithm adopts the same replacement strategy for dirty pages (modified pages) and clean pages (unmodified pages), but in flash-based storage, the replacement of dirty pages will result in additional write and erase operations, thereby increasing the overall operating cost of the system. Therefore, the LIRS algorithm may exhibit poor I / O performance in this storage environment.

[0043] To improve this, P-LIRS introduces the following improvement strategies: First, it reduces the frequency of write operations by prioritizing the least frequently used and least used clean pages; second, it retains dirty pages in the buffer until they become "victim" candidates for the second time, thereby avoiding a significant drop in the buffer hit rate during the replacement process. In this way, P-LIRS better adapts to the asymmetry of read and write operations under different I / O latencies while maintaining a high hit rate.

[0044] The core idea of ​​P-LIRS is to use two LRU (least recently used) queues similar to the LIRS algorithm: S queue and Q queue. The S queue contains all LIR pages (recently accessed pages) and HIR pages (less frequently accessed pages), and the Q queue contains all resident HIR pages. Unlike the traditional LIRS strategy, all pages in P-LIRS are marked as read-write, and when there is insufficient space, the page needs to be evicted through the "victim" selection strategy.

[0045] Specifically, when processing the victim page, it is mainly based on P-LIRS execution, as follows: Deep cold detection strategy: Assign a "deep cold flag" to the cold pages in the Q queue to identify whether the page is in the "deep cold" state.

[0046] Delaying the eviction of dirty pages: For dirty pages that are considered not deeply cold, their eviction time is delayed to reduce unnecessary write operations.

[0047] During the actual eviction process, the page at the bottom of the Q queue is checked first. If the page is clean, regardless of whether it is marked as deep cold or not, it will be considered a "victim" and removed from the cache, and the data will be written to the NAND flash. If the page is dirty, the deep cold flag will come into play. If the "deep cold flag" bit of a dirty page is 0, it means that the page is likely to stay in the cache, and the page will be moved to the top of the queue with the deep cold flag bit set to 1. If dirty pages that already have a deep cold flag are selected as "victims", these dirty pages will be replaced to avoid a significant drop in cache hit rate.

[0048] When a page hit occurs, P-LIRS moves the LIR page in the S queue to the top. The page in the Q queue is inserted to the top of the queue and the deep cold flag is reset to 0.

[0049] Dirty pages are when a page is used and its data has been modified, causing the data in the cache page to be inconsistent with the data on disk. Dirty pages indicate that changes to the data have not yet been written to disk, but may need to be written back to disk at any time by a background thread or when buffer pool space needs to be freed to ensure data persistence and consistency.

[0050] A clean page means that when a page is used but its content has not been modified, such a page is called a clean page. The data of a clean page is consistent with the data on the disk, which means that the data in the buffer pool is synchronized with the data on the disk and does not need to be written back to the disk immediately.

[0051] For example, in Figure 4 In the P-LIRS "victim" selection process shown in , it is assumed that the LIR set contains three pages, the HIR set contains two pages, and the cache is initially full. When a page reference occurs, P-LIRS manages the contents of the buffer. For example, when page 7 is written, the clean page 5 is first evicted from the cache according to the "victim" selection strategy and marked as a non-resident HIR page and placed in the S queue. At the same time, due to the deep cold detection algorithm, the dirty page 3 will be retained in the cache and its deep cold flag will be set to 1. Next, page 7 is inserted at the top of the Q queue and the S queue as a dirty resident HIR page.

[0052] Through these optimizations, the P-LIRS algorithm can effectively reduce write operations, avoid excessive eviction of dirty pages, thereby improving the cache hit rate, and adapt to the characteristics of flash devices and the asymmetry of I / O latency.

[0053] S150: Prune the stack of the queue containing all LIR pages and HIR pages.

[0054] In this embodiment, the queue containing all LIR pages and HIR pages is traversed from bottom to top, HIR pages are converted to LIR state pages, and pages that are dirty pages and have a deep cold flag of 1 are evicted, and pages that are clean pages or have a deep cold flag of 0 are converted to LIR state and moved to the top of the queue.

[0055] S160, self-learning to adjust the cache amount of the HIR page.

[0056] In one embodiment, the above-mentioned step S160 may include steps S161 - S162 .

[0057] S161. Calculate the cache amount of the HIR page after each page access to obtain a new cache amount.

[0058] In this embodiment, the Calculate the cache size of the HIR page after each page access to get the new cache size, where Lbuf is the cache size given in page units, and L' hir is the new cache size; R rw is the read / write ratio.

[0059] S162. Call the function adjust_Lh_process() according to the new cache amount to check whether the cache amount of the current HIR page needs to be adjusted.

[0060] In this embodiment, when the current cache amount of the HIR page is larger than the new cache amount, a page is selected from the queue containing all resident HIR pages for deletion; when the current cache amount of the HIR page is smaller than the new cache amount, the LIR page at the bottom of the queue containing all LIR pages and HIR pages is converted to the HIR page at the top of the queue containing all resident HIR pages.

[0061] In this embodiment, in the P-LIRS algorithm, L hir An important parameter representing the page cache size, specifically related to the cache size of HIR (highly referenced) pages. hir The setting is not particularly sensitive, and when L hir When L is set to 1% of the cache size, the best hit rate and I / O performance can be achieved. However, this conclusion ignores the impact of asymmetric I / O overhead. hir May not be suitable for all situations, especially when considering asymmetric I / O. hir The settings need to be adjusted dynamically based on the workload.

[0062] To overcome this limitation, the PA-LIRS (Probabilistic LIRS) algorithm proposes an adjustable L hir value, and automatically adjust L through the self-learning mechanism hir , so that it gradually approaches the theoretical target value L' hir This means that the algorithm can be based on the actual read-write ratio (R rw ) and workload history data to flexibly adjust the cache management strategy. Specifically, PA-LIRS A new L'hir value is calculated at each page access, and the size of the HIR buffer is dynamically adjusted to adapt to different workload requirements.

[0063] When Lhir is less than the target value L'hir, PA-LIRS will promote the LIR (low reference rate) pages in the S queue to HIR pages and expand the HIR cache area, thereby improving the cache's capacity to accommodate high-frequency access pages.

[0064] If Lhir is greater than the target value L'hir, PA-LIRS will reduce the HIR cache area and select pages in the Q queue for sacrifice to avoid promoting LIR pages to HIR pages and reduce the cache burden.

[0065] This dynamic adjustment mechanism ensures that the cache can be adaptively adjusted as needed under different workloads, thereby optimizing system performance.

[0066] Under write-intensive loads, the overall access time varies with the hit rate, so PA-LIRS adjusts the size of Lhir according to the characteristics of the workload to optimize the write performance.

[0067] Under read-intensive loads, it is recommended to use a larger Lhir value to provide a wider access range and reduce write operations, especially for less frequent dirty pages, to avoid frequent writes to the flash memory.

[0068] The PA-LIRS algorithm optimizes cache management by adjusting the LLhir value and ensures that unnecessary pages in the queue are marked as LIR through stack pruning (stack_pruning_process), thereby improving the overall replacement efficiency. The purpose of stack pruning is to ensure that the least active pages in the cache are removed as early as possible, ensuring that frequently accessed pages can be kept in the cache first.

[0069] PA-LIRS dynamically adjusts Lhir through a self-learning mechanism, so that cache management can be flexibly optimized according to the characteristics of the workload (read / write ratio), thereby improving the hit rate and I / O performance. By intelligently selecting and pushing infrequently accessed dirty pages to the low-reference queue, write operations are reduced, reducing the pressure on storage devices, especially in read-intensive scenarios. Under write-intensive and read-intensive workloads, PA-LIRS can intelligently adjust the cache size, improve the efficiency of I / O operations, and optimize the overall performance of the system. By introducing the PA-LIRS algorithm, the system can achieve a higher cache hit rate and I / O performance, while reducing invalid writes and adapting to different workload requirements, thereby improving the life cycle and response speed of storage devices.

[0070] S170, determining whether the current cache size of the HIR page is equal to the target cache size; In this embodiment, the target cache size is a preset cache size threshold.

[0071] If the current cache size of the HIR page is equal to the target cache size, then enter the end step; If the current cache size of the HIR page is not equal to the target cache size, step S140 is executed.

[0072] S180. If the page is neither a new page nor a page without access history, update the page status and execute step S150.

[0073] In this embodiment, after the page status is updated, a promotion strategy can also be used to perform a hit promotion. Specifically, when a hit occurs, the LIR page will be promoted to the top of the S queue. The HIR page that leaves a history mark in the S queue will be promoted to the top of the queue and marked as LIR. On the other hand, the HIR page that is not in the S queue will be promoted to the top of the Q queue without changing its status.

[0074] It can be seen that the method of this embodiment is based on the PA-LIRS (Probability Adjusted LeastRecently Used with Inter-reference Recency and Frequency) algorithm for cache replacement. It combines the "recency" and "frequency" information of the page to intelligently determine which pages should be replaced from the cache. PA-LIRS pays special attention to reducing the replacement of dirty pages (data pages that have been modified but not written back to the disk) because such operations often result in higher I / O overhead, including additional write amplification effects and erase cycles, which are key factors affecting the life of NAND flash memory.

[0075] An important feature of the PA-LIRS algorithm is its ability to dynamically adjust parameters based on changes in workload. This means that the algorithm can automatically adjust the cache replacement strategy based on the current working mode (such as read-intensive or write-intensive) to achieve optimal performance and resource utilization. This adaptive capability enables PA-LIRS to perform well in different application scenarios, whether it is online transaction processing or large-scale data analysis.

[0076] PA-LIRS maintains a cache structure consisting of two main queues: one is the Q queue, which is used to store pages that may be replaced; the other is the S queue, which contains all active LIR (Low Inter-reference Recency) and HIR (High Inter-reference Recency) pages. When a page needs to be replaced, PA-LIRS tends to choose clean pages in the Q queue as "victims" and assign a lower replacement probability to dirty pages. In particular, for dirty pages marked as "deep cold", they will get an extra chance to stay in the cache until they are selected as replacement candidates again.

[0077] Experiments have shown that compared with the traditional LIRS algorithm, PA-LIRS can significantly reduce the write amplification effect while maintaining or even improving the cache hit rate, thereby extending the service life of the flash memory device. In addition, the adaptive parameter adjustment function of PA-LIRS also proves its strong adaptability in the face of changing workloads, further improving the overall performance of the system.

[0078] The above-mentioned adaptive NAND flash memory page replacement method obtains page access information to determine whether the page is a new page or has no access record. If so, it is marked and inserted into the queue containing LIR and HIR pages and the queue of resident HIR pages; when the LIR and HIR page queues are full, the victim page is selected from the resident HIR page queue for processing, and dirty pages are given priority to reduce unnecessary write operations; the LIR and HIR page queues are pruned to ensure a reasonable queue structure and reduce frequent replacements caused by queue overflow; the cache amount of the HIR page is dynamically adjusted using a self-learning mechanism to adapt to the optimal performance requirements under different workload modes; the cache amount of the HIR page is continuously monitored and adjusted to the target value to ensure that the cache strategy can maximize the hit rate and minimize the write cost; the cache management is optimized through the above process, the read and write operation costs are effectively balanced, and the service life of the NAND flash memory is extended, thereby achieving the optimization of the overall system performance.

[0079] Figure 6 FIG. 3 is a schematic block diagram of an adaptive NAND flash memory page replacement system 300 provided in an embodiment of the present invention. Figure 6As shown, corresponding to the above adaptive NAND flash memory page replacement method, the present invention also provides an adaptive NAND flash memory page replacement system 300. The adaptive NAND flash memory page replacement system 300 includes a unit for executing the above adaptive NAND flash memory page replacement method, and the system can be configured in a server. Specifically, please refer to Figure 6 The page replacement system 300 of the adaptive NAND flash memory includes an information acquisition unit 301, a page determination unit 302, a marking unit 303, a victim page selection unit 304, a pruning unit 305, a self-learning unit 306 and a cache amount determination unit 307.

[0080] The information acquisition unit 301 is used to acquire the access page related information; the page judgment unit 302 is used to judge whether the page is a new page or a page with no access history according to the access page related information; the marking unit 303 is used to mark the page if the page is a new page or a page with no access history, and insert the marked page into two cache queues, one of which contains all LIR pages and HIR pages, and the other contains all resident HIR pages; the victim page selection unit 304 is used to select a victim page when the queue containing all LIR pages and HIR pages is full. Then a victim page is selected from another queue and the victim page is processed; a pruning unit 305 is used to prune the stack of the queue containing all LIR pages and HIR pages; a self-learning unit 306 is used to self-learn and adjust the cache size of the HIR page; a cache size judgment unit 307 is used to judge whether the current cache size of the HIR page is equal to the target cache size; if the current cache size of the HIR page is equal to the target cache size, enter the end step; if the current cache size of the HIR page is not equal to the target cache size, execute the selection of the victim page from another queue and process the victim page.

[0081] In one embodiment, if Figure 6 As shown, the above-mentioned adaptive NAND flash memory page replacement system 300 also includes: a page update unit 308, which is used to update the page status if the page is not a new page or a page without access history, and execute the pruning stack of the queue containing all LIR pages and HIR pages.

[0082] In one embodiment, the marking unit 303 is used to mark the page as a HIR page, and insert the marked page into two cache queues.

[0083] In one embodiment, the victim page selection unit 304 includes: A selection subunit, used to select a page at the bottom of another queue as a victim page; The victim page processing subunit is used to evict the victim page when the victim page is a clean page; when the victim page is a dirty page and the corresponding deep cold flag is 0, retain the victim page in the current queue and set the corresponding deep cold flag to 1; when the victim page is a dirty page and the corresponding deep cold flag is 1, evict the victim page.

[0084] In one embodiment, the pruning unit 305 is used to traverse the queue containing all LIR pages and HIR pages from bottom to top, convert HIR pages to pages in LIR state, evict pages that are dirty pages and have a deep cold flag of 1, convert pages that are clean pages or have a deep cold flag of 0 to LIR state, and move them to the top of the queue.

[0085] In one embodiment, the self-learning unit 306 includes: The calculation subunit is used to calculate the cache amount of the HIR page after each page access to obtain a new cache amount; specifically, the Calculate the cache size of the HIR page after each page access to get the new cache size, where Lbuf is the cache size given in page units, and L' hir is the new cache size; R rw is the read / write ratio.

[0086] The checking subunit is used to call the function adjust_Lh_process() to check whether the cache amount of the current HIR page needs to be adjusted according to the new cache amount. Specifically, when the cache amount of the current HIR page is greater than the new cache amount, a page is selected from the queue containing all resident HIR pages for deletion, and when the cache amount of the current HIR page is less than the new cache amount, the LIR page at the bottom of the queue containing all LIR pages and HIR pages is converted to the HIR page at the top of the queue containing all resident HIR pages.

[0087] It should be noted that technicians in the relevant field can clearly understand that the specific implementation process of the above-mentioned adaptive NAND flash memory page replacement system 300 and each unit can refer to the corresponding description in the aforementioned method embodiment, and for the convenience and brevity of description, it will not be repeated here.

[0088] The above-mentioned adaptive NAND flash memory page replacement system 300 can be implemented in the form of a computer program. The computer program can be used in Figure 7 Runs on the computer device shown.

[0089] See also Figure 7, Figure 7 5 is a schematic block diagram of a computer device provided in an embodiment of the present application. The computer device 500 may be a server, wherein the server may be an independent server or a server cluster composed of multiple servers.

[0090] See also Figure 7 The computer device 500 includes a processor 502 , a memory and a network interface 505 connected via a system bus 501 , wherein the memory may include a non-volatile storage medium 503 and an internal memory 504 .

[0091] The non-volatile storage medium 503 can store an operating system 5031 and a computer program 5032. The computer program 5032 includes program instructions, and when the program instructions are executed, the processor 502 can execute a page replacement method for an adaptive NAND flash memory.

[0092] The processor 502 is used to provide computing and control capabilities to support the operation of the entire computer device 500 .

[0093] The internal memory 504 provides an environment for the operation of the computer program 5032 in the non-volatile storage medium 503. When the computer program 5032 is executed by the processor 502, the processor 502 can execute an adaptive NAND flash memory page replacement method.

[0094] The network interface 505 is used to communicate with other devices over the network. Figure 7 The structure shown in the figure is merely a block diagram of a portion of the structure related to the solution of the present application, and does not constitute a limitation on the computer device 500 to which the solution of the present application is applied. The specific computer device 500 may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0095] The processor 502 is used to run the computer program 5032 stored in the memory to implement the following steps: Obtain information related to the accessed page; determine whether the page is a new page or a page with no access history based on the information related to the accessed page; if the page is a new page or a page with no access history, mark the page and insert the marked page into two cache queues, one of which contains all LIR pages and HIR pages, and the other contains all resident HIR pages; when the queue containing all LIR pages and HIR pages is full, select a victim page from the other queue and process the victim page; prune the stack of the queue containing all LIR pages and HIR pages; self-learn and adjust the cache size of the HIR page; determine whether the current cache size of the HIR page is equal to the target cache size; if the current cache size of the HIR page is equal to the target cache size, enter the end step; if the current cache size of the HIR page is not equal to the target cache size, select the victim page from the other queue and process the victim page.

[0096] In one embodiment, after implementing the step of determining whether a page is a new page or a page without a visit history record according to the access page related information, the processor 502 further implements the following steps: If the page is neither a new page nor a page without access history, the page status is updated, and the stack pruning of the queue containing all LIR pages and HIR pages is performed.

[0097] In one embodiment, when the processor 502 implements the step of marking the page and inserting the marked page into the queue, the processor 502 specifically implements the following steps: The page is marked as a HIR page, and the marked page is inserted into two cache queues.

[0098] In one embodiment, the processor 502 implements the following steps when implementing the steps of selecting a victim page from another queue and processing the victim page: Select the page at the bottom of another queue as the victim page; when the victim page is a clean page, evict the victim page; when the victim page is a dirty page and the corresponding deep cold flag is 0, retain the victim page in the current queue and set the corresponding deep cold flag to 1; when the victim page is a dirty page and the corresponding deep cold flag is 1, evict the victim page.

[0099] In one embodiment, when the processor 502 implements the step of pruning the stack of the queue including all LIR pages and HIR pages, the processor 502 specifically implements the following steps: Traverse the queue containing all LIR pages and HIR pages from bottom to top, convert HIR pages to LIR state, evict dirty pages with a deep cold flag of 1, convert clean pages or pages with a deep cold flag of 0 to LIR state, and move them to the top of the queue.

[0100] In one embodiment, the processor 502 implements the steps of traversing the queue including all LIR pages and HIR pages from the bottom to the top, converting HIR pages to pages in the LIR state, and evicting dirty pages with a deep cold flag of 1, converting clean pages or pages with a deep cold flag of 0 to the LIR state, and moving them to the top of the queue. Specifically, the following steps are implemented: Calculate the cache amount of the HIR page after each page access to obtain a new cache amount; call the adjust_Lh_process() function based on the new cache amount to check whether the cache amount of the current HIR page needs to be adjusted.

[0101] In one embodiment, when the processor 502 implements the step of calculating the cache amount of the HIR page after each page access to obtain a new cache amount, the processor 502 specifically implements the following steps: use Calculate the cache size of the HIR page after each page access to get the new cache size, where Lbuf is the cache size given in page units, L'hir is the new cache size; Rrw is the read / write ratio.

[0102] In one embodiment, when the processor 502 implements the step of calling the function adjust_Lh_process() according to the new cache amount to check whether the cache amount of the current HIR page needs to be adjusted, the processor 502 specifically implements the following steps: When the current cache amount of HIR pages is greater than the new cache amount, pages are selected for deletion from the queue containing all resident HIR pages. When the current cache amount of HIR pages is less than the new cache amount, the LIR page at the bottom of the queue containing all LIR pages and HIR pages is converted to the HIR page at the top of the queue containing all resident HIR pages.

[0103] It should be understood that in the embodiment of the present application, the processor 502 may be a central processing unit (CPU), and the processor 502 may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Among them, the general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0104] It can be understood by those skilled in the art that all or part of the processes in the method for implementing the above embodiment can be completed by instructing the relevant hardware through a computer program. The computer program includes program instructions, and the computer program can be stored in a storage medium, which is a computer-readable storage medium. The program instructions are executed by at least one processor in the computer system to implement the process steps of the embodiment of the above method.

[0105] Therefore, the present invention also provides a storage medium. The storage medium may be a computer-readable storage medium. The storage medium stores a computer program, wherein when the computer program is executed by a processor, the processor executes the following steps: Obtain information related to the accessed page; determine whether the page is a new page or a page with no access history based on the information related to the accessed page; if the page is a new page or a page with no access history, mark the page and insert the marked page into two cache queues, one of which contains all LIR pages and HIR pages, and the other contains all resident HIR pages; when the queue containing all LIR pages and HIR pages is full, select a victim page from the other queue and process the victim page; prune the stack of the queue containing all LIR pages and HIR pages; self-learn and adjust the cache size of the HIR page; determine whether the current cache size of the HIR page is equal to the target cache size; if the current cache size of the HIR page is equal to the target cache size, enter the end step; if the current cache size of the HIR page is not equal to the target cache size, select the victim page from the other queue and process the victim page.

[0106] In one embodiment, after executing the computer program to implement the step of determining whether a page is a new page or a page without a visit history record according to the access page related information, the processor further implements the following steps: If the page is neither a new page nor a page without access history, the page status is updated, and the stack pruning of the queue containing all LIR pages and HIR pages is performed.

[0107] In one embodiment, when the processor executes the computer program to implement the step of marking the page and inserting the marked page into the queue, the processor specifically implements the following steps: The page is marked as a HIR page, and the marked page is inserted into two cache queues.

[0108] In one embodiment, when the processor executes the computer program to implement the steps of selecting a victim page from another queue and processing the victim page, the processor specifically implements the following steps: Select the page at the bottom of another queue as the victim page; when the victim page is a clean page, evict the victim page; when the victim page is a dirty page and the corresponding deep cold flag is 0, retain the victim page in the current queue and set the corresponding deep cold flag to 1; when the victim page is a dirty page and the corresponding deep cold flag is 1, evict the victim page.

[0109] In one embodiment, when the processor executes the computer program to implement the step of pruning the stack of the queue including all LIR pages and HIR pages, the processor specifically implements the following steps: Traverse the queue containing all LIR pages and HIR pages from bottom to top, convert HIR pages to LIR state, evict dirty pages with a deep cold flag of 1, convert clean pages or pages with a deep cold flag of 0 to LIR state, and move them to the top of the queue.

[0110] In one embodiment, when the processor executes the computer program to implement the step of self-learning to adjust the cache amount of the HIR page, the processor specifically implements the following steps: Calculate the cache amount of the HIR page after each page access to obtain a new cache amount; call the adjust_Lh_process() function based on the new cache amount to check whether the cache amount of the current HIR page needs to be adjusted.

[0111] In one embodiment, when the processor executes the computer program to implement the step of calculating the cache amount of the HIR page after each page access to obtain a new cache amount, the processor specifically implements the following steps: use Calculate the cache size of the HIR page after each page access to get the new cache size, where Lbuf is the cache size given in page units, L'hir is the new cache size; Rrw is the read / write ratio.

[0112] In one embodiment, when the processor executes the computer program to implement the step of calling the function adjust_Lh_process() according to the new cache amount to check whether the cache amount of the current HIR page needs to be adjusted, the processor specifically implements the following steps: When the current cache amount of HIR pages is greater than the new cache amount, pages are selected for deletion from the queue containing all resident HIR pages. When the current cache amount of HIR pages is less than the new cache amount, the LIR page at the bottom of the queue containing all LIR pages and HIR pages is converted to the HIR page at the top of the queue containing all resident HIR pages.

[0113] The storage medium may be a USB flash drive, a mobile hard disk, a read-only memory (ROM), a magnetic disk, or an optical disk, etc., which are computer-readable storage media that can store program codes.

[0114] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in terms of function in the above description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0115] In the several embodiments provided by the present invention, it should be understood that the disclosed systems and methods can be implemented in other ways. For example, the system embodiments described above are only schematic. For example, the division of each unit is only a logical function division, and there may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed.

[0116] The steps in the method of the embodiment of the present invention can be adjusted in order, combined and deleted according to actual needs. The units in the system of the embodiment of the present invention can be combined, divided and deleted according to actual needs. In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0117] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a storage medium. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, terminal, or network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention.

[0118] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed by the present invention, and these modifications or replacements should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. A page replacement method for an adaptive NAND flash memory, characterized in that: include: Get information about the visited page; Determine whether the page is a new page or a page with no access history according to the access page related information; If the page is a new page or a page with no access history, mark the page and insert the marked page into two cache queues, one of which contains all LIR pages and HIR pages, and the other contains all resident HIR pages; When the queue containing all LIR pages and HIR pages is full, a victim page is selected from another queue and processed; Prune the stack of queues containing all LIR pages and HIR pages; Self-learning to adjust the cache size of HIR pages; Determine whether the current cache size of the HIR page is equal to the target cache size; If the current cache size of the HIR page is equal to the target cache size, then enter the end step; If the current cache size of the HIR page is not equal to the target cache size, the step of selecting a victim page from another queue is performed, and the victim page is processed.

2. The method for replacing a page of an adaptive NAND flash memory according to claim 1, characterized in that: After determining whether the page is a new page or a page without a visit history record according to the access page related information, the method further includes: If the page is neither a new page nor a page without access history, the page status is updated, and the stack pruning of the queue containing all LIR pages and HIR pages is performed.

3. The method for replacing a page of an adaptive NAND flash memory according to claim 1, characterized in that: The marking of the page and inserting the marked page into the queue comprises: The page is marked as an HIR page, and the marked page is inserted into two cache queues.

4. The method for replacing a page of an adaptive NAND flash memory according to claim 1, characterized in that: The step of selecting a victim page from another queue and processing the victim page includes: Select the page at the bottom of the other queue as the victim page; When the victim page is a clean page, the victim page is evicted; when the victim page is a dirty page and the corresponding deep cold flag is 0, the victim page is retained in the current queue and the corresponding deep cold flag is set to 1; when the victim page is a dirty page and the corresponding deep cold flag is 1, the victim page is evicted.

5. The method for adaptively replacing a NAND flash memory page according to claim 1, characterized in that: The pruning stack of the queue containing all LIR pages and HIR pages includes: The queue containing all LIR pages and HIR pages is traversed from the bottom to the top. HIR pages are converted to LIR state pages, and pages that are dirty pages and have a deep cold flag of 1 are evicted. Pages that are clean pages or have a deep cold flag of 0 are converted to LIR state and moved to the top of the queue.

6. The method for adaptively replacing a NAND flash memory page according to claim 1, characterized in that: The self-learning adjustment of the cache amount of the HIR page includes: Calculate the cache size of the HIR page after each page access to get the new cache size; The adjust_Lh_process() function is called according to the new cache amount to check whether the cache amount of the current HIR page needs to be adjusted.

7. The method for replacing a page of an adaptive NAND flash memory according to claim 6, characterized in that: The calculation of the cache amount of the HIR page after each page access to obtain a new cache amount includes: use Calculate the cache size of the HIR page after each page access to get the new cache size, where Lbuf is the cache size given in page units, L'hir is the new cache size; Rrw is the read / write ratio.

8. The method for adaptively replacing a page of a NAND flash memory according to claim 7, characterized in that: The calling of the adjust_Lh_process() function according to the new cache amount to check whether the cache amount of the current HIR page needs to be adjusted includes: When the current cache amount of HIR pages is greater than the new cache amount, pages are selected for deletion from the queue containing all resident HIR pages. When the current cache amount of HIR pages is less than the new cache amount, the LIR page at the bottom of the queue containing all LIR pages and HIR pages is converted to the HIR page at the top of the queue containing all resident HIR pages.

9. An adaptive NAND flash memory page replacement system, characterized in that: include: An information acquisition unit, used to acquire information related to the visited page; A page determination unit, used to determine whether a page is a new page or a page without a visit history record according to the access page related information; a marking unit, for marking the page if the page is a new page or a page without an access history, and inserting the marked page into two cache queues, one of which contains all LIR pages and HIR pages, and the other contains all resident HIR pages; a victim page selection unit, configured to select a victim page from another queue and process the victim page when the queue including all LIR pages and HIR pages is full; A pruning unit, for pruning the stack of queues containing all LIR pages and HIR pages; A self-learning unit, used for self-learning to adjust the cache amount of HIR pages; The cache amount judgment unit is used to judge whether the cache amount of the current HIR page is equal to the target cache amount; if the cache amount of the current HIR page is equal to the target cache amount, then enter the end step; if the cache amount of the current HIR page is not equal to the target cache amount, then execute the selection of the victim page from another queue and process the victim page.

10. A computer device, characterized in that: The computer device comprises a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the method according to any one of claims 1 to 8 when executing the computer program.

Images