Display panel, preparation method thereof and display device

Abstract

The invention discloses a display panel, a preparation method thereof and a display device, and relates to the technical field of display. A first wiring layer of a power wiring in the display panel is provided with a first target area exposed by a through groove area of a first organic film layer, and the orthographic projection of a third material layer, located in the first target area, of the first wiring layer on a substrate is located in the orthographic projection of a second material layer on the substrate. The orthographic projection of the second material layer, located in the first target area, of the first wiring layer on the substrate is located in the orthographic projection of the first material layer on the substrate. Therefore, a packaging film layer subsequently formed by the display panel can be prevented from generating cracks in the first target area, and then water and oxygen are prevented from invading the display area along an invasion channel generated by the cracks. According to the scheme, the light emitting effect of the pixel units in the display area can be guaranteed, the display area is prevented from generating black spots, the yield of the display panel is high, and the display effect of the display panel is good.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a method for preparing the same, and a display device. Background Art

[0002] Organic light-emitting diode (OLED) display panels have become the mainstream development direction in the field of display technology due to their advantages such as self-luminescence, high brightness, good image quality and low energy consumption.

[0003] In the related art, the display panel has a display area and a peripheral area surrounding the display area. The display panel includes a blocking structure located in the peripheral area and surrounding the display area, which is used to block the overflow of organic materials in the display area. In order to prevent water and oxygen from penetrating from the peripheral area to the display area along the organic materials, the organic film layer located in the area next to the blocking structure needs to be removed. In addition, the display panel includes a power supply line, which needs to pass through the blocking structure from the peripheral area and connect to the relevant structure of the pixel unit in the display area, thereby providing a power supply signal to the relevant structure of the pixel unit.

[0004] However, since the organic film layer located next to the blocking structure needs to be removed, the power line is exposed at the position where the organic film layer is removed. During the film preparation process after the power line, the exposed part of the power line may be side-etched, thereby affecting the yield of the display panel and causing poor display effect of the display panel. Summary of the invention

[0005] The present application provides a display panel and a manufacturing method thereof, and a display device, which can solve the problem of poor display effect of the display panel in the related art. The technical solution is as follows:

[0006] In one aspect, a display panel is provided, the display panel comprising:

[0007] A base substrate, the base substrate having a display area and a peripheral area surrounding the display area;

[0008] A plurality of pixel units, wherein the plurality of pixel units are located in the display area;

[0009] a blocking structure, the blocking structure surrounding the display area;

[0010] At least one power supply line is located on one side of the substrate, each of the power supply lines is used to receive a power supply signal and is connected to the plurality of pixel units;

[0011] a first organic film layer, the first organic film layer is located on a side of the power line away from the base substrate, and the first organic film layer has at least one through-groove area, an orthographic projection of the through-groove area on the base substrate and an orthographic projection of the blocking structure on the base substrate are arranged adjacent to each other, and the through-groove area is used to expose a first target area of ​​the power line;

[0012] Among them, the power routing includes at least a first routing layer, the first routing layer includes a first material layer, a second material layer and a third material layer stacked in sequence in a direction away from the base substrate, the orthographic projection of the third material layer of the first routing layer located in the first target area on the base substrate is located within the orthographic projection of the second material layer on the base substrate, and the orthographic projection of the second material layer of the first routing layer located in the first target area on the base substrate is located within the orthographic projection of the first material layer on the base substrate.

[0013] Optionally, the first material layer of the first routing layer located in the first target area has a first boundary extending along a first direction, the second material layer of the first routing layer located in the first target area has a second boundary extending along the first direction, and the third material layer of the first routing layer located in the first target area has a third boundary extending along the first direction;

[0014] The distance between the first boundary and the third boundary in the second direction is greater than 3 micrometers, the second boundary is located between the first boundary and the third boundary, and the second direction is perpendicular to the first direction.

[0015] Optionally, the first organic film layer has a groove area, the thickness of the first organic film layer in the groove area is less than the thickness of other areas except the groove area, and the groove area is used to cover the second target area of ​​the first wiring layer;

[0016] The second target area and the first target area are adjacent to each other in the first direction.

[0017] Optionally, the groove area has a first groove boundary close to the first wiring layer and extending along a first direction, and the third material layer of the first wiring layer located in the first target area has a third boundary extending along the first direction;

[0018] The orthographic projection of the first groove boundary on the substrate is collinear with the orthographic projection of the third boundary on the substrate.

[0019] Optionally, the groove region further has a second groove boundary away from the through groove region and extending along a second direction, and a third groove boundary adjacent to the through groove region and extending along the second direction; wherein the second direction is perpendicular to the first direction;

[0020] A distance between the second groove boundary and the third groove boundary in the first direction is greater than 3 micrometers.

[0021] Optionally, the power routing includes a third routing layer, a second routing layer and the first routing layer stacked in sequence in a direction away from the base substrate; the display panel includes: a third organic film layer located between the third routing layer and the second routing layer, and a second organic film layer located between the second routing layer and the first routing layer, and the first organic film layer is located on a side of the first routing layer away from the base substrate;

[0022] The third routing layer and the second routing layer are connected through openings in the third organic film layer, and the second routing layer and the first routing layer are connected through openings in the second organic film layer; the through groove area is used to expose the first target area of ​​the first routing layer.

[0023] Optionally, the power wiring includes a second wiring layer and the first wiring layer stacked in sequence in a direction away from the base substrate; the display panel includes: a second organic film layer located between the second wiring layer and the first wiring layer, and the first organic film layer is located on a side of the first wiring layer away from the base substrate;

[0024] The second wiring layer and the first wiring layer are connected via an opening in the second organic film layer; and the through groove area is used to expose a first target area of ​​the first wiring layer.

[0025] Optionally, the at least one power supply line includes a first signal power supply line and a second signal power supply line spaced apart above the second direction, and the through-slot area includes a first sub-through-slot area for exposing the first signal power supply line and a second sub-through-slot area for exposing the second signal power supply line;

[0026] Wherein, the length of the first sub-through-groove region along the first direction is less than or equal to the length of the second sub-through-groove region along the first direction.

[0027] Optionally, the thickness of a portion of the second material layer located in the first target area is less than or equal to the thickness of a portion of the second material layer located in the other areas.

[0028] Optionally, when the thickness of the portion of the second material layer located in the first target area is less than the thickness of the portion of the second material layer located in the other areas, the portion of the second material layer located in the first target area is uneven away from the surface of the base substrate.

[0029] Optionally, the blocking structure comprises: a first blocking dam, a second blocking dam and a third blocking dam which are sequentially arranged away from the display area;

[0030] The first organic film layer has two through-groove regions, one of which is located on a side of the third blocking dam away from the display region, and the other through-groove region is located between the second blocking dam and the third blocking dam.

[0031] Optionally, each barrier dam in the barrier structure includes at least one layer of the organic film layers in the display panel, and the organic film layers in the display panel include: a third organic film layer, a second organic film layer and the first organic film layer;

[0032] Among them, one of the first organic film layer, the second organic film layer and the third organic film layer is located in an area adjacent to any blocking dam in the blocking structure and where the through groove area is not provided.

[0033] Optionally, in the area of ​​the power supply line covered by the organic film layer in the display panel, the sides of the third material layer, the second material layer and the first material layer are flat sides, and the flat sides are inclined relative to the supporting surface of the base substrate;

[0034] The orthographic projection of the third material layer on the base substrate is located within the orthographic projection of the second material layer on the base substrate, and the orthographic projection of the second material layer on the base substrate is located within the orthographic projection of the first material layer on the base substrate.

[0035] In another aspect, a method for preparing a display panel is provided, the method comprising:

[0036] Providing a base substrate, the base substrate having a display area and a peripheral area surrounding the display area;

[0037] A plurality of pixel units, a blocking structure and at least one initial power supply line are formed on one side of the base substrate, the plurality of pixel units are located in the display area, the blocking structure surrounds the display area, each of the initial power supply lines is used to receive a power supply signal and is connected to the plurality of pixel units; the initial power supply line comprises at least a first initial wiring layer, the first initial wiring layer comprises a first material layer, a second material layer and a third material layer stacked in sequence in a direction away from the base substrate;

[0038] An initial organic film layer is formed on a side of the initial power supply line away from the base substrate, the initial organic film layer has at least one through-groove area, the orthographic projection of the through-groove area on the base substrate and the orthographic projection of the blocking structure on the base substrate are arranged adjacent to each other, and the through-groove area is used to expose a first target area of ​​the initial power supply line;

[0039] An etching process is adopted to etch the third material layer of the first target area of ​​the first initial routing layer of the at least one initial power routing and to etch the initial organic film layer to obtain a first routing layer and a first organic film layer of the at least one power routing, wherein the orthographic projection of the third material layer of the first routing layer located in the first target area on the base substrate is within the orthographic projection of the second material layer on the base substrate, and the orthographic projection of the second material layer of the power routing located in the first target area on the base substrate is within the orthographic projection of the first material layer on the base substrate.

[0040] Optionally, forming the plurality of pixel units comprises: sequentially forming an anode layer, a pixel defining layer, a light emitting layer and a cathode layer on a side of the initial organic film layer away from the base substrate;

[0041] The etching process is used to etch the third material layer of the first initial wiring layer of the at least one initial power wiring located in the first target area and the initial organic film layer, including:

[0042] After forming the anode layer and before forming the pixel defining layer, the etching process is used to etch the third material layer of the first initial wiring layer of the at least one initial power wiring located in the first target area and to etch the initial organic film layer.

[0043] Optionally, before forming the anode layer, the first initial wiring layer is located in the first target region so that a first boundary of the first material layer, a second boundary of the second material layer and a third boundary of the third material layer are collinear;

[0044] After forming the anode layer, the orthographic projection of the second material layer of the first initial routing layer located in the first target area on the base substrate is located within the orthographic projection of the third material layer on the base substrate, and the first boundary of the first material layer of the first initial routing layer located in the first target area and the third boundary of the third material layer are collinear;

[0045] The first boundary, the second boundary and the third boundary all extend along a first direction.

[0046] Optionally, forming the plurality of pixel units includes: sequentially forming an anode layer, a pixel defining layer, a light emitting layer and a cathode layer on a side of the first organic film layer away from the base substrate;

[0047] The etching process is used to etch the third material layer of the first initial wiring layer of the at least one initial power wiring located in the first target area and the initial organic film layer, including:

[0048] After forming the pixel defining layer and before forming the light emitting layer, the etching process is used to etch the third material layer of the first initial wiring layer of the at least one initial power wiring located in the first target area and to etch the initial organic film layer.

[0049] Optionally, before forming the pixel defining layer, an orthographic projection of a second material layer of a first initial routing layer located in the first target area on the base substrate is located within an orthographic projection of a third material layer on the base substrate, and a first boundary of a first material layer of the first initial routing layer located in the first target area and a third boundary of the third material layer are collinear;

[0050] After forming the pixel definition layer, part of the material of the pixel definition layer is located in a retracted area, and the retracted area is an area where the first initial wiring layer has the first material layer and the third material layer, and does not have the second material layer;

[0051] After etching the third material layer of the first initial wiring layer of the at least one initial power wiring located in the first target area and etching the initial organic film layer using the etching process, a portion of the material of the pixel defining layer located in the retracted area is removed.

[0052] Optionally, the etching of the third material layer of the first initial wiring layer of the at least one initial power wiring located in the first target area and the etching of the initial organic film layer by using an etching process includes:

[0053] Coating photoresist on a side of the first initial wiring layer away from the substrate;

[0054] Exposing the photoresist using a mask;

[0055] Developing the photoresist with a developer to remove the exposed portion of the photoresist;

[0056] Using an etching process to remove the third material layer of the first initial wiring layer located in the first target area and the portion of the initial organic film layer not protected by the photoresist;

[0057] Remove the remaining photoresist.

[0058] Optionally, the mask has a plurality of mask openings, and an orthographic projection of each mask opening on the substrate partially overlaps with the through-slot region and partially overlaps with the first target region of the initial power routing;

[0059] The mask opening has a first mask boundary extending along a first direction, the first mask boundary is used to form a third boundary of the third material layer after etching, and the orthographic projection of the first mask boundary on the substrate is located within the orthographic projection of the first material layer on the substrate, the distance between the first mask boundary and the third boundary in the second direction is greater than 3 microns, and the second direction is perpendicular to the first direction.

[0060] Optionally, the first mask boundary is also used to form a first groove boundary of a groove region of the first organic film layer after etching, and the first groove boundary is close to the power line and extends along the first direction;

[0061] The thickness of the first organic film layer in the groove area is less than the thickness of other areas except the groove area. The groove area is used to cover the second target area of ​​the power line. The second target area and the first target area are adjacent to each other in the first direction.

[0062] Optionally, the mask opening further has a second mask boundary extending along the second direction, the through-groove region is located on one side of the second mask boundary, and the second mask boundary is used to form a second groove boundary of a groove region of the first organic film layer away from the through-groove region and extending along the second direction; the groove region further has a third groove boundary adjacent to the through-groove region and extending along the second direction;

[0063] Wherein, the distance between the second groove boundary and the third groove boundary in the first direction is greater than 3 micrometers.

[0064] Optionally, forming the power wiring includes: forming a first wiring layer on one side of the substrate;

[0065] Alternatively, forming the power wiring includes: sequentially forming a second wiring layer, a second organic film layer and a first wiring layer on one side of the base substrate, wherein the first wiring layer and the second wiring layer are connected through an opening in the second organic film layer;

[0066] Alternatively, forming the power wiring includes: sequentially forming a third wiring layer, a third organic film layer, a second wiring layer, a second organic film layer and a first wiring layer on one side of the base substrate, the first wiring layer and the second wiring layer are connected through an opening in the second organic film layer, and the second wiring layer and the third wiring layer are connected through an opening in the third organic film layer;

[0067] The through-groove area is used to expose a first target area of ​​the first wiring layer.

[0068] In yet another aspect, a display device is provided, the display device comprising a power supply component and the display panel as described in the above aspect;

[0069] Wherein, the power supply component is used to supply power to the display panel.

[0070] The beneficial effects of the technical solution provided by this application include at least:

[0071] The present application provides a display panel and a method for preparing the same, and a display device, wherein the first routing layer of the power routing in the display panel has a first target area exposed by the through-groove area of ​​the first organic film layer, and the orthographic projection of the third material layer of the first routing layer located in the first target area on the substrate is located within the orthographic projection of the second material layer on the substrate. The orthographic projection of the second material layer of the first routing layer located in the first target area on the substrate is located within the orthographic projection of the first material layer on the substrate. Thus, it is possible to prevent the encapsulation film layer subsequently formed on the display panel from generating cracks in the first target area, thereby preventing water and oxygen from invading the display area along the intrusion channels generated by the cracks. The solution of the embodiment of the present application can ensure the luminous effect of the pixel unit in the display area, avoid the occurrence of black spots in the display area, and provide a high yield of the display panel and a good display effect of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0072] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0073] Figure 1 is a schematic diagram of the structure of a display panel provided in an embodiment of the present application;

[0074] Figure 2 yes Figure 1 A partial schematic diagram of a display panel shown;

[0075] Figure 3 is a schematic diagram of a substrate provided in an embodiment of the present application;

[0076] Figure 4 It is a schematic diagram of a stacking of power supply lines provided in an embodiment of the present application;

[0077] Figure 5 It is a schematic diagram of a power supply line being engraved on the side provided by an embodiment of the present application;

[0078] Figure 6 is a schematic diagram of a power supply routing provided in an embodiment of the present application;

[0079] Figure 7 yes Figure 2 A partial schematic diagram of

[0080] Figure 8 yes Figure 7 Cross-sectional view along AA direction;

[0081] Fig. 9 yes Figure 7 Cross-section along direction BB;

[0082] Fig.10 yes Figure 7 Cross-sectional view along CC direction;

[0083] Fig.11 yes Figure 7 Cross-section along DD direction;

[0084] Fig.12 yes Figure 7 Cross-sectional view along EE direction;

[0085] Fig.13 is a flow chart of a method for preparing a display panel provided in an embodiment of the present application;

[0086] Fig.14 is a flow chart of another method for preparing a display panel provided in an embodiment of the present application;

[0087] Fig.15 is a schematic diagram of a process for etching a third material layer provided in an embodiment of the present application;

[0088] Fig.16 is a flow chart of another method for preparing a display panel provided in an embodiment of the present application;

[0089] Fig.17 is a schematic diagram of forming an active thin film provided by an embodiment of the present application;

[0090] Fig.18 is a schematic diagram of patterning an active thin film provided in an embodiment of the present application;

[0091] Fig.19 is a schematic diagram of forming a first insulating layer provided by an embodiment of the present application;

[0092] Fig. 20 is a schematic diagram of forming a first gate film provided by an embodiment of the present application;

[0093] Fig.21 is a schematic diagram of patterning a first gate film provided in an embodiment of the present application;

[0094] Fig. 22 is a schematic diagram of forming a second insulating layer provided by an embodiment of the present application;

[0095] Fig.23 is a schematic diagram of forming a second gate film provided by an embodiment of the present application;

[0096] Fig.24 is a schematic diagram of patterning a second gate film provided in an embodiment of the present application;

[0097] Fig.25 is a schematic diagram of forming an interlayer dielectric layer provided by an embodiment of the present application;

[0098] Fig.26 is a schematic diagram of forming a first source-drain thin film provided in an embodiment of the present application;

[0099] Fig. 27 It is a schematic diagram of coating a photoresist on a side of a first source / drain film away from a substrate provided by an embodiment of the present application;

[0100] Fig.28 is a schematic diagram of exposing and developing a photoresist provided in an embodiment of the present application;

[0101] Fig.29 is a schematic diagram of etching a first source-drain film provided in an embodiment of the present application;

[0102] Fig.30 is a schematic diagram of removing photoresist provided in an embodiment of the present application;

[0103] Fig.31 is a schematic diagram of forming a first flat film provided in an embodiment of the present application;

[0104] Fig.32 is a schematic diagram of patterning a first flat film provided in an embodiment of the present application;

[0105] Fig.33 is a schematic diagram of forming an anode film provided in an embodiment of the present application;

[0106] Fig.34 is a schematic diagram of patterning an anode film provided in an embodiment of the present application;

[0107] Fig.35 is a schematic diagram of forming a pixel defining film provided in an embodiment of the present application;

[0108] Fig.36 is a schematic diagram of patterning a pixel defining film provided in an embodiment of the present application;

[0109] Fig.37 It is a schematic diagram of coating a photoresist after the anode layer is prepared, provided in an embodiment of the present application;

[0110] Fig.38 is a schematic diagram of exposure and development of a photoresist provided in an embodiment of the present application;

[0111] Fig.39 is a schematic diagram of etching the third material layer provided in an embodiment of the present application;

[0112] Fig.40 is a schematic diagram of removing photoresist provided in an embodiment of the present application;

[0113] Fig.41 It is a schematic diagram of coating a photoresist after a pixel defining layer is prepared, provided in an embodiment of the present application;

[0114] Fig.42 is a schematic diagram of exposure and development of a photoresist provided in an embodiment of the present application;

[0115] Fig.43 is a schematic diagram of etching the third material layer provided in an embodiment of the present application;

[0116] Fig.44 is a schematic diagram of removing photoresist provided in an embodiment of the present application;

[0117] Fig.45 is a flow chart of another method for preparing a display panel provided in an embodiment of the present application;

[0118] Fig.46 is a flow chart of another method for preparing a display panel provided in an embodiment of the present application;

[0119] Fig.47 is a flow chart of another method for preparing a display panel provided in an embodiment of the present application;

[0120] Fig.48 is a flow chart of another method for preparing a display panel provided in an embodiment of the present application;

[0121] Fig.49 This is an electron microscope schematic diagram of an I-shaped structure in an area of ​​the first wiring layer not covered by the organic film layer provided in an embodiment of the present application;

[0122] Fig.50 is an electron microscope schematic diagram of a region of a first wiring layer covered by an organic film layer provided in an embodiment of the present application;

[0123] Fig.51 It is a schematic diagram of an electron microscope showing residual pixel defining material in an I-shaped structure provided in an embodiment of the present application;

[0124] Fig.52 is a schematic diagram of an electron microscope for etching a third material layer provided in an embodiment of the present application;

[0125] Fig.53 is another electron microscope schematic diagram of etching the third material layer provided in an embodiment of the present application;

[0126] Fig.54 yes Fig.53 A partial enlarged schematic diagram of the electron microscope schematic diagram shown;

[0127] Fig.55 It is a structural schematic diagram of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0128] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0129] Figure 1 1 is a schematic diagram of the structure of a display panel 10 provided in an embodiment of the present application. Figure 2 yes Figure 1 FIG. 1 is a partial schematic diagram of the display panel 10 shown in FIG. Figure 1 and Figure 2 The display panel 10 includes: a base substrate 101 , a plurality of pixel units 102 , a blocking structure 103 , at least one power supply line 104 , and a first organic film layer 105 .

[0130] Figure 3 Schematic diagram of a substrate provided in an embodiment of the present application. Figure 3 The base substrate 101 has a display area 101a and a peripheral area 101b surrounding the display area 101a. Figures 1 to 3, a plurality of pixel units 102 are located in the display region 101 a , and a blocking structure 103 is located in the peripheral region 101 b and surrounds the display region 101 a , so as to prevent the organic material in the display region 101 a from overflowing.

[0131] At least one power line 104 is located on one side of the substrate 101, and each power line 104 is used to receive a power signal and is connected to the pixel unit 102. Thus, each power line 104 can be used to transmit a power signal to the pixel unit 102, thereby driving the pixel unit 102 to emit light.

[0132] The first organic film layer 105 is located on a side of the power supply line 104 away from the base substrate 101, and the first organic film layer 105 has at least one through-groove area 105a. The orthographic projection of the through-groove area 105a on the base substrate 101 and the orthographic projection of the blocking structure 103 on the base substrate 101 are arranged adjacent to each other, and the through-groove area 105a is used to expose the first target area m of the power supply line 104.

[0133] Since the material of the first organic film layer 105 is an organic material, water and oxygen from the outside may invade the display area 101a along the first organic film layer 105, causing the pixel unit 102 in the display area 101a to fail. Therefore, in order to avoid the failure of the pixel unit 102, the first organic film layer 105 located at the adjacent position of the blocking structure 103 can be removed, that is, the through groove area 105a designed in the first organic film layer 105 is arranged adjacent to the blocking structure 103. Further, since the first organic film layer 105 located at the adjacent position of the blocking structure 103 is removed, the first target area m in the power wiring 104 where the first organic film layer 105 is removed will be exposed to the outside, that is, the through groove area 105a of the first organic film layer 105 exposes the first target area m of the power wiring 104.

[0134] The power supply wiring 104 at least includes a first wiring layer. Figure 4, the first wiring layer includes a first material layer a1, a second material layer a2 and a third material layer a3 which are sequentially stacked in a direction away from the base substrate 101. Typically, the material of the first material layer a1 is the same as the material of the third material layer a3, for example, the material of the first material layer a1 and the third material layer a3 is titanium (Ti), while the material of the second material layer a2 is different from the material of the first material layer a1 and the third material layer a3, for example, the material of the second material layer a2 is aluminum (Al). In addition, the display panel 10 also includes other film layers located on the side of the power wiring 104 away from the base substrate 101. In the subsequent preparation process of these other film layers, since the portion of the first wiring layer of the power wiring 104 located in the first target area m is exposed to the outside, the portion of the first wiring layer of the power wiring 104 located in the first target area m is easily affected by the process. Among them, since the material of the second material layer a2 is easier to be etched than the material of the first material layer a1 (third material layer a3), reference is made to FIG. Figure 5 The first wiring layer is easily side-engraved, and the first wiring layer has an I-shaped (undercut) structure.

[0135] Furthermore, the display panel 10 further includes a packaging film layer (not shown in the figure) for packaging the display area 101a, and the inorganic material layer included in the packaging film layer is prone to cracks at the I-shaped position of the power supply line 104. The existence of the crack provides an invasion channel for the invasion of water and oxygen, and the water and oxygen will diffuse toward the display area 101a along the invasion channel, thereby causing the pixel unit 102 of the display area 101a to fail, resulting in the problem of black spots in the display area 101a.

[0136] From the above analysis, it can be seen that the main reason for the failure of the pixel unit 102 in the display area 101a is that the second material layer a2 of the first routing layer of the power routing 104 located in the first target area m (the first target area m is not protected by the first organic film layer 105) is etched, resulting in an I-shaped structure of the first routing layer.

[0137] In the related art, in order to solve the problem of water and oxygen intrusion caused by the I-shaped structure of the first wiring layer, which in turn causes the pixel unit to fail, an inorganic film layer (for example, a passivation layer (PVX)) is usually formed on the side of the first wiring layer of the power wiring away from the base substrate 101, so that the inorganic film layer covers the area of ​​the first wiring layer exposed by the first organic film layer, thereby preventing the first wiring layer from having an I-shaped structure when subsequent film layers are formed.

[0138] However, the solution of forming an inorganic film layer will lead to an increase in the process, such as adding inorganic film layer deposition, exposure and development processes, thereby affecting the production capacity of the display panel. In addition, if the display panel includes multiple source and drain layers (for example, including a first source and drain layer SD1, a second source and drain layer SD2 and a third source and drain layer SD3), the inorganic film layer can only be designed between SD1 and SD2, that is, only SD1 can be used to route the power line (the power line is a single-layer line), which is not conducive to reducing the power consumption of the display panel, and the flexibility of the wiring of the power line is poor.

[0139] Therefore, in the embodiments of the present application, reference Figure 6 In order to solve the problem that the first routing layer of the power routing line 104 is in an I-shaped structure, the orthographic projection of the third material layer a3 of the first routing layer of the power routing line 104 located in the first target area m on the base substrate 101 is located within the orthographic projection of the second material layer a2 on the base substrate 101. The orthographic projection of the second material layer a2 of the first routing layer of the power routing line 104 located in the first target area m on the base substrate 101 is located within the orthographic projection of the first material layer a1 on the base substrate 101.

[0140] It should be noted that after the preparation of the other film layers included in the display panel 10 and located on the side of the power wiring 104 away from the base substrate 101 is completed, since the second material layer a2 of the first wiring layer of the power wiring 104 located in the first target area m is etched, the orthographic projection of the second material layer a2 of the first wiring layer of the power wiring 104 located in the first target area m on the base substrate 101 can be located within the orthographic projection of the first material layer a1 on the base substrate 101. Further, refer to Figure 6 After the subsequent film layer preparation is completed, the etching process can be used to etch the third material layer a3 of the first routing layer of the power routing 104 located in the first target area m, so that the orthographic projection of the third material layer a3 of the power routing 104 located in the first target area m on the base substrate 101 is located within the orthographic projection of the second material layer a2 on the base substrate 101, thereby avoiding the I-shaped structure of the part of the first routing layer of the power routing 104 located in the first target area m.

[0141] Furthermore, the inorganic material layer in the encapsulation film layer included in the display panel 10 can be gradually increased in the first target area m, thereby preventing cracks in the inorganic material layer and further preventing water and oxygen from invading. Thus, the luminous effect of the pixel unit 102 in the display area 101a can be guaranteed, and black spots in the display area 101a can be avoided.

[0142] In summary, an embodiment of the present application provides a display panel, in which a first routing layer of a power routing line has a first target area exposed by a through groove area of ​​a first organic film layer, and an orthographic projection of a third material layer of the first routing layer located in the first target area on the substrate is located within an orthographic projection of the second material layer on the substrate. An orthographic projection of a second material layer of the first routing layer located in the first target area on the substrate is located within an orthographic projection of the first material layer on the substrate. Thus, cracks in the encapsulation film layer subsequently formed on the display panel can be prevented from forming in the first target area, thereby preventing water and oxygen from invading the display area along the invasion channels generated by the cracks. The solution of the embodiment of the present application can ensure the luminous effect of the pixel unit in the display area, avoid the occurrence of black spots in the display area, and the yield of the display panel is high, and the display effect of the display panel is good.

[0143] Figure 7 yes Figure 2 A partial schematic diagram of . Figure 8 yes Figure 7 Cross-sectional view along the AA direction. Figure 9 to Figure 7 Cross-sectional view along direction BB. Fig.10 yes Figure 7 Cross-sectional view along CC direction. Fig.11 yes Figure 7 Cross-sectional view along DD direction, Fig.12 yes Figure 7 Cross-sectional view along the EE direction. Figures 7 to 11 , the first material layer a1 of the first routing layer of the power routing 104 located in the first target area m has a first boundary a11 extending along the first direction X, and the first boundary a11 can be the midline of the side of the first material layer a1 in its thickness. The second material layer a2 of the first routing layer of the power routing 104 located in the first target area m has a second boundary a21 along the first direction X, and the second boundary a21 can be the midline of the side of the second material layer a2 in its thickness. The third material layer a3 of the first routing layer of the power routing 104 located in the first target area m has a third boundary a31 extending along the first direction X, and the third boundary a31 can be the midline of the side of the third material layer a3 in its thickness. Wherein, Figures 8 to 12 The inorganic film layer in the description refers to a film layer where all materials located on the side of the power trace 104 close to the base substrate are inorganic materials. Figures 8 to 12 The organic film layer refers to a film layer made of organic material. For example, the organic film layer includes a first organic film layer 105 located on a side of the first wiring layer of the power wiring 104 away from the base substrate 101 .

[0144] Generally, the size of the second material layer a2 that is engraved in the subsequent film preparation process is usually less than 3 micrometers (μm). Therefore, in order to ensure that the orthographic projection of the third material layer a3 on the base substrate 101 is located within the orthographic projection of the second material layer a2 on the base substrate 101, the distance between the first boundary a11 and the third boundary a31 in the second direction Y can be greater than 3μm. The second boundary a21 is located between the first boundary a11 and the third boundary a31, thereby making the first material layer a1, the second material layer a2 and the third material layer a3 present a step structure that increases layer by layer. Among them, the second direction Y is perpendicular to the first direction X. For example, the first direction X is the pixel column direction of the display panel 10, and the second direction Y is the pixel row direction of the display panel 10.

[0145] The second boundary a21 being located between the first boundary a11 and the third boundary a31 may mean that the orthographic projection of the second boundary a21 on the base substrate 101 is located between the orthographic projection of the first boundary a11 on the base substrate 101 and the orthographic projection of the third boundary a31 on the base substrate 101 .

[0146] Assumptions Fig.12 The organic film layer shown is the first organic film layer 105, referring to Fig.12 The first organic film layer 105 has a groove region 105b, and the thickness h1 of the first organic film layer 105 in the groove region 105b is less than the thickness h2 of other regions except the groove region 105b. The groove region 105b is used to cover the second target region n of the power supply line 104. The second target region n and the first target region m are adjacent to each other in the first direction X.

[0147] Optionally, the same etching process may be used to etch the third material layer a3 of the first wiring layer of the power wiring 104 located in the first target area m, and to etch the groove area 105b of the first organic film layer 105. For example, when performing the etching process, the same mask opening in the mask plate may be used to form the etched third material layer a3 and the groove area 105b. For example, when performing the etching process, the length w1 of the etched area along the first direction X may be slightly greater than the length of the first target area m along the first direction X, and the length w2 along the second direction Y may be determined based on the product, and it is only necessary to ensure that the third boundary a31 of the first wiring layer is far away from the first boundary a11 relative to the second boundary a21.

[0148] refer to Figure 7The groove region 105b has a first groove boundary 105b1 which is close to the first wiring layer of the power wiring 104 and extends along the first direction X. Since the groove region 105b and the third material layer a3 are formed by the same etching process, assuming that the mask opening in the mask is a rectangular opening, the orthographic projection of the first groove boundary 105b1 on the base substrate 101 is collinear with the orthographic projection of the third boundary a31 on the base substrate 101.

[0149] Since the second target region n and the first target region m of the first wiring layer of the power wiring 104 are adjacent in the first direction X, the groove region 105b covering the second target region n and the through-groove region 105a exposing the first target region m in the first organic film layer 105 are adjacent in the first direction X. Figure 7 The groove area 105b also has a second groove boundary 105b2 away from the through groove area 105a and extending along the second direction Y, and a third groove boundary 105b3 adjacent to the through groove area 105a and extending along the second direction Y. The distance b between the second groove boundary 105b2 and the third groove boundary 105b3 in the first direction X is greater than 3 μm. In this way, the third material layer a3 located in the first target area m of the power wiring 104 can be ensured to be etched, and the power wiring 104 can be prevented from having an I-shaped structure due to a small etching range.

[0150] In an embodiment of the present application, when an etching process is used to etch the third material layer a3 of the first routing layer of the power routing 104 located in the first target area m, a portion of the second material layer a2 of the first routing layer located in the first target area m may also be etched away, and of course the second material layer a2 of the first routing layer located in the first target area m may not be etched away.

[0151] If a portion of the second material layer a2 of the first wiring layer located in the first target area m is etched away, the thickness of the portion of the second material layer a2 located in the first target area m is less than the thickness of the portion of the second material layer a2 located in other areas. In this case, affected by the current process, the surface of the portion of the second material layer a2 located in the first target area (m) away from the base substrate 101 is uneven. Of course, with subsequent improvements in the process, the surface of the portion of the second material layer a2 located in the first target area (m) away from the base substrate 101 can also be made flat.

[0152] If the second material layer a2 of the first wiring layer located in the first target area m is not etched, the thickness of the second material layer a2 located in the first target area m may be equal to the thickness of the second material layer a2 located in other areas.

[0153] As a first optional implementation, the display panel 10 includes: an active layer (poly), a first insulating layer, a first gate layer (gate1), a second insulating layer, a second gate layer (gate2), a third insulating layer, an oxide layer (IGZO), a fourth insulating layer, a third gate layer (gate3), an inter-level dielectric layer (inter level dielectric, ILD), a first source and drain layer (SD1), a first planarization layer (planarization layer, PLN), a second source and drain layer (SD2), a second planarization layer (PLN2), a third source and drain layer (SD3) and a third planarization layer (PLN3). That is, the display panel 10 has three source and drain layers. In this implementation, Figures 8 to 12 The organic film layer includes a first flat layer, a second flat layer, and a third flat layer, Figures 8 to 12 The inorganic film layers include a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer and an interlayer dielectric layer.

[0154] In this case, the power supply line 104 can be wired using one, two or three layers of the first source-drain layer (SD1), the second source-drain layer (SD2) and the third source-drain layer (SD3). That is, the power supply line 104 can include one layer of wiring, two layers of wiring or three layers of wiring. If the power supply line 104 is a multi-layer wiring scheme, it is necessary to ensure that the wiring on the upper layer covers the wiring on the lower layer to avoid the wiring on the lower layer being exposed to the outside and affecting the wiring on the lower layer during the subsequent film preparation.

[0155] Optionally, the power supply wiring 104 includes a third wiring layer, a second wiring layer and a first wiring layer stacked in sequence in a direction away from the base substrate 101. The third wiring layer is located at the first source and drain layer (SD1) of the display panel 10, the second wiring layer is located at the second source and drain layer (SD2), and the first wiring layer is located at the third source and drain layer (SD3). The first flat layer (third organic film layer) between the first source and drain layer and the second source and drain layer has an opening, and the third layer wiring and the second layer wiring are connected through the opening in the first flat layer. The second flat layer (second organic film layer) between the second source and drain layer and the third source and drain layer has an opening, and the second layer wiring and the first layer wiring are connected through the opening in the first flat layer.

[0156] Optionally, the first organic film layer 105 has a through groove area 105a, and the second organic film layer and the third organic film layer also have through groove areas 105a. That is, the area where the first organic film layer 105 is removed next to the blocking structure 103, and the second organic film layer and the third organic film layer are also removed. That is, the through groove area 105a refers to the area where all the film layers composed of organic materials included in the display panel 10 are removed. Since the first layer of wiring covers the second layer of wiring and the third layer of wiring, the design of the through groove area 105a can expose the first target area m of the first wiring layer without exposing the second wiring layer and the third wiring layer.

[0157] Therefore, in the subsequent film layer preparation process, only the first wiring layer located at the top layer may have an I-shaped structure, so the etching process can be used to etch the third layer wiring located in the first target area m in the first layer wiring to avoid the first layer wiring being in an I-shaped structure. Figures 7 to 12 The power supply line 105 shown in the figure may be a first layer line included in the power supply line 105, and Figures 7 to 12 The second layer traces and the third layer traces are not shown.

[0158] In the embodiment of the present application, when the display panel 10 has three source and drain electrode layers, the display panel 10 may be an oxide (low temperature polycrystalline oxide, LTPO) display panel, and the oxide display panel includes oxide thin film transistors.

[0159] As a second optional implementation, the display panel 10 includes: an active layer (poly), a first insulating layer, a first gate layer (gate1), a second insulating layer, a second gate layer (gate2), an interlayer dielectric layer (ILD), a first source and drain layer (SD1), a first planar layer (PLN1), a second source and drain layer (SD2) and a second planar layer (PLN2). That is, the display panel 10 has two source and drain layers.

[0160] In this case, the power supply line 104 may be arranged in one or two layers of the first source-drain layer and the second source-drain layer. That is, the power supply line 104 may include one layer of lines or two layers of lines. If the power supply line 104 is arranged in two layers, it is necessary to ensure that the lines in the upper layer cover the lines in the lower layer to avoid the lines in the lower layer being exposed to the outside and affecting the lines in the lower layer during the subsequent film preparation.

[0161] Optionally, the power supply wiring 104 includes a second wiring layer and a first wiring layer stacked in sequence in a direction away from the base substrate 101. The second wiring layer is located at the first source and drain layer (SD1) of the display panel 10, and the first wiring layer is located at the second source and drain layer (SD2). The first flat layer (second organic film layer) between the first source and drain layer and the second source and drain layer has an opening, and the second layer wiring and the first layer wiring are connected through the opening in the first flat layer.

[0162] Optionally, the first organic film layer 105 has a through-groove region 105a, and the second organic film layer also has a through-groove region 105a. That is, the region where the first organic film layer 105 is removed next to the blocking structure 103 also removes the second organic film layer. That is, the through-groove region 105a refers to the region where all the film layers composed of organic materials included in the display panel 10 are removed. Since the first layer of wiring covers the second layer of wiring, the design of the through-groove region 105a can expose the first target region m of the first wiring layer without exposing the second wiring layer.

[0163] Therefore, in the subsequent film layer preparation process, only the first wiring layer located on the upper layer may have an I-shaped structure, so the etching process can be used to etch the third layer wiring located in the first target area m in the first layer wiring to avoid the first layer wiring being in an I-shaped structure. Figures 7 to 12 The power supply line 105 shown in the figure may be a first layer line included in the power supply line 105, and Figures 7 to 12 The second layer traces are not shown.

[0164] In the embodiment of the present application, when the display panel 10 has two source and drain layers, the display panel 10 may be a low temperature poly-silicon (LTPS) display panel, and the LTPS display panel includes LTPS thin film transistors.

[0165] As a third optional implementation, the display panel 10 includes: an active layer (poly), a first insulating layer, a first gate layer (gate1), a second insulating layer, a second gate layer (gate2), an interlayer dielectric layer (ILD), a first source and drain layer (SD1) and a first planar layer (PLN1). That is, the display panel 10 has a source and drain layer.

[0166] In this case, the power supply line 104 can be wired using the first source and drain layer. That is, the power supply line 104 can include a layer of lines. Optionally, the power supply line 104 includes a first line layer, and the first flat layer on the first line layer can be the first organic film layer 105 described in the above embodiment. In this implementation, Figures 7 to 12The power supply line 105 shown in the figure may be a first layer line included in the power supply line 105 .

[0167] In the embodiment of the present application, when the display panel 10 has a source-drain electrode layer, the display panel 10 may be a low-temperature polycrystalline silicon (LTPS) display panel, and the LTPS display panel includes LTPS thin film transistors.

[0168] refer to Figure 2 , at least one power supply line 104 includes a first signal power supply line 104a and a second signal power supply line 104b spaced apart in the second direction Y. The first signal power supply line 104a can provide a first signal for the pixel unit 102, and the first signal power supply line 104a can be a negative power supply line (referred to as a VSS line). The second signal power supply line 104b can provide a second signal for the pixel unit 102, and the second signal power supply line 104b can be a positive power supply line (referred to as a VDD line).

[0169] Usually, other signal lines may be designed in the area where the VSS line is set, and other signal lines may also be wired in two layers, and an insulating layer is required between the two layers for insulation. Figure 2 The through-groove region 105a has a first sub-through-groove region 105a1 for exposing the first signal power supply wiring 104a and a second sub-through-groove region 105a2 for exposing the second signal power supply wiring 104b. The length k1 of the first sub-through-groove region 105a1 along the first direction X is less than or equal to the length k2 of the second sub-through-groove region 105a2 along the first direction X. Thus, the first sub-through-groove region 105a1 of the VSS wiring arrangement area can be designed to be smaller, so that the organic film layer in this area insulates the double-layer wiring of other signal wirings.

[0170] In the embodiment of the present application, the orthographic projection of the power supply line 104 on the base substrate 101 partially overlaps with the orthographic projection of the blocking structure 103 on the base substrate 101. Thus, a portion of the power supply line 104 is located on a side of the blocking structure 103 close to the display area 101a to connect with the pixel unit 102, and another portion of the power supply line 104 is located on a side of the blocking structure 103 away from the display area 101a to receive a power signal.

[0171] Optionally, the orthographic projection of the blocking structure 103 on the substrate 101 may be a ring structure. A portion of the power line 104 located on the side of the blocking structure 103 close to the display area 101a is located within the area surrounded by the blocking structure 103. Another portion of the power line 104 located on the side of the blocking structure 103 away from the display area 101a is located outside the area surrounded by the blocking structure 103. Thus, the power line 104 can pass through the blocking structure 103 and enter the area surrounded by the blocking structure 103. Among them, the portion of the blocking structure 103 through which the power line 104 passes can also be called a port.

[0172] Combination Figure 1 and Figure 2 The barrier structure 103 may include a first barrier dam 1031, a second barrier dam 1032, and a third barrier dam 1033. The first barrier dam 1031, the second barrier dam 1032, and the third barrier dam 1033 are sequentially arranged in a direction away from the display area 101a. In addition, there is a gap between adjacent barrier dams among the first barrier dam 1031, the second barrier dam 1032, and the third barrier dam 1033.

[0173] Optionally, the through groove region 105a may be located at the third barrier dam 1033 away from the display region 101a, and may also be located between adjacent barrier dams. Figure 2 Two through-slot regions 105a are designed, one of which is located on the side of the third barrier dam 1033 away from the display region 101a, and the other through-slot region 105a is located between the second barrier dam 1032 and the third barrier dam 1033. In addition, no through-slot region 105a is designed between the first barrier dam 1031 and the second barrier dam 1032, and the through-slot region 105a between the second barrier dam 1032 and the third barrier dam 1033 is only located in the area where the first power signal wiring is located, but not in the area where the second power signal wiring is located. This design method can make the cathode layer and the barrier dam overlap, which is convenient for realizing a narrow frame of the display panel.

[0174] It should be noted that a through groove region 105 a may be designed between the first barrier dam 1031 and the second barrier dam 1032 , and between the second barrier dam 1032 and the third barrier dam 1033 .

[0175] In the embodiment of the present application, each barrier dam in the barrier structure 103 includes at least one layer of the organic film layer in the display panel. The organic film layer in the display panel 10 includes: a third organic film layer, a second organic film layer and a first organic film layer. Of course, the organic film layer in the display panel 10 also includes: a pixel defining layer and a supporting layer.

[0176] Among them, one of the first organic film layer, the second organic film layer and the third organic film layer is located in an area adjacent to any barrier dam in the barrier structure 103 and where no through groove area 105a is provided. That is, if the through groove area 105a is provided between adjacent barrier dams or beside the barrier dams, or an organic film layer is provided.

[0177] Optionally, the heights of the first barrier dam 1031, the second barrier dam 1032, and the third barrier dam 1033 may increase in sequence in a direction away from the display area 101a. That is, the height of the first barrier dam 1031 is less than the height of the second barrier dam 1032, and the height of the second barrier dam 1032 is less than the height of the third barrier dam 1033. Alternatively, the heights of the first barrier dam 1031, the second barrier dam 1032, and the third barrier dam 1033 may be equal. This embodiment of the present application is not limited thereto.

[0178] In the embodiment of the present application, the display panel 10 further includes an encapsulation film layer (not shown) for encapsulating the display area 101a. The encapsulation film layer may include: a first film layer, a second film layer and a third film layer stacked in a direction away from the base substrate 101.

[0179] Optionally, the first film layer and the third film layer may be made of an inorganic material, and the second film layer may be made of an organic material. For example, the first film layer and the third film layer may be made of one or more inorganic oxides such as SiNx (silicon nitride), SiOx (silicon oxide) and SiOxNy (silicon oxynitride). The second film layer may be made of a resin material. The resin may be a thermoplastic resin or a thermoplastic resin, the thermoplastic resin may include an acrylic (PMMA) resin, and the thermosetting resin may include an epoxy resin.

[0180] It should be noted that the second film layer can be located in the area surrounded by the blocking structure 103, and the first film layer and the third film layer can cover the area surrounded by the blocking structure 103 and cover the blocking structure 103. That is, the orthographic projections of the first film layer and the third film layer on the base substrate 101 can be located on the side of the blocking structure 103 away from the display area 101a, that is, can be located in the first target area m of the power line 104.

[0181] Therefore, by etching the third layer of the power line 104 located in the first target area m, the power line 104 is prevented from being in an I-shape, thereby preventing the first film layer and the third film layer of the packaging film layer from cracking in the first target area m.

[0182] Optionally, the second film layer may be manufactured by ink jet printing (IJP) method. The first film layer and the third film layer may be manufactured by chemical vapor deposition (CVD) method.

[0183] In the embodiment of the present application, in the area of ​​the power supply line 104 covered by the organic film layer in the display panel 10, the side edges of the third material layer a3, the second material layer a2 and the first material layer a1 are flat side edges, and the flat side edges are inclined relative to the supporting surface of the base substrate 101. Among them, the orthographic projection of the third material layer a3 on the base substrate 101 is located within the orthographic projection of the second material layer a2 on the base substrate 101, and the orthographic projection of the second material layer a2 on the base substrate 101 is located within the orthographic projection of the first material layer a1 on the base substrate 101.

[0184] In summary, an embodiment of the present application provides a display panel, in which a first routing layer of a power routing line has a first target area exposed by a through groove area of ​​a first organic film layer, and an orthographic projection of a third material layer of the first routing layer located in the first target area on the substrate is located within an orthographic projection of the second material layer on the substrate. An orthographic projection of a second material layer of the first routing layer located in the first target area on the substrate is located within an orthographic projection of the first material layer on the substrate. Thus, cracks in the encapsulation film layer subsequently formed on the display panel can be prevented from forming in the first target area, thereby preventing water and oxygen from invading the display area along the invasion channels generated by the cracks. The solution of the embodiment of the present application can ensure the luminous effect of the pixel unit in the display area, avoid the occurrence of black spots in the display area, and the yield of the display panel is high, and the display effect of the display panel is good.

[0185] Fig.13 is a flow chart of a method for preparing a display panel provided in an embodiment of the present application. Fig.13 , the method comprising:

[0186] Step S101: provide a base substrate.

[0187] refer to Figure 3 The base substrate 101 has a display area 101 a and a peripheral area 101 b surrounding the display area 101 a .

[0188] Step S102: forming a plurality of pixel units, a blocking structure and at least one initial power supply line on one side of the substrate.

[0189] Among them, a plurality of pixel units 102 are located in the display area 101a, the blocking structure 103 surrounds the display area 101a, and each initial power supply line is used to receive a power supply signal and is connected to the plurality of pixel units 102 to provide a power supply signal to the plurality of pixel units 102. The initial power supply line at least includes a first initial wiring layer, and the first initial wiring layer includes a first material layer a1, a second material layer a2, and a third material layer a3 stacked in sequence in a direction away from the base substrate 101.

[0190] Optionally, the material of the first material layer a1 is the same as the material of the third material layer a3, and the material of the second material layer a2 is different from the materials of the first material layer a1 and the third material layer a3.

[0191] Step S103 , forming an initial organic film layer on a side of the initial power supply line away from the base substrate.

[0192] In the embodiment of the present application, the initial organic film layer has at least one through-groove region 105a, the orthographic projection of the through-groove region 105a on the base substrate 101 and the orthographic projection of the blocking structure 103 on the base substrate 101 are arranged adjacent to each other. The through-groove region 105a is used to expose the first target region m of the initial power supply wiring.

[0193] Step S104 , etching the third material layer of the first initial routing layer of at least one initial power routing line located in the first target area and etching the initial organic film layer by an etching process to obtain a first routing layer and a first organic film layer of at least one initial power routing line.

[0194] refer to Fig.11 , the orthographic projection of the third material layer a3 of the first routing layer of the power routing 104 located in the first target area m on the base substrate 101 is located within the orthographic projection of the second material layer a2 on the base substrate 101, and the orthographic projection of the second material layer a2 of the first routing layer of the power routing 104 located in the first target area m on the base substrate 101 is located within the orthographic projection of the first material layer a1 on the base substrate 101.

[0195] In summary, an embodiment of the present application provides a method for preparing a display panel, wherein the first routing layer of the power routing in the display panel prepared by the method has a first target area exposed by the through groove area of ​​the first organic film layer, and the orthographic projection of the third material layer of the first routing layer located in the first target area on the base substrate is located within the orthographic projection of the second material layer on the base substrate. The orthographic projection of the second material layer of the first routing layer located in the first target area on the base substrate is located within the orthographic projection of the first material layer on the base substrate. Thus, it is possible to prevent the encapsulation film layer subsequently formed on the display panel from generating cracks in the first target area, thereby preventing water and oxygen from invading the display area along the intrusion channels generated by the cracks. The solution of the embodiment of the present application can ensure the luminous effect of the pixel unit in the display area, avoid the occurrence of black spots in the display area, and the yield of the display panel is high, and the display effect of the display panel is good.

[0196] The first implementation method is Fig.14 FIG. 1 is a flow chart of another method for manufacturing a display panel provided in an embodiment of the present application. Taking the power supply wiring 104 including the first wiring layer as an example, refer to Fig.14 , the method comprising:

[0197] Step S201: forming an active layer, a first insulating layer, a first gate layer, a second insulating layer, a second gate layer and an interlayer dielectric layer in sequence on one side of a substrate.

[0198] In an embodiment of the present application, the active layer includes a plurality of active patterns, each of which can be used to constitute a thin film transistor in a pixel circuit included in the pixel unit 102. The first insulating layer is used to insulate the active layer from the first gate layer. The first gate layer includes a plurality of first gate patterns, and the orthographic projection of each first gate pattern on the substrate 101 partially overlaps with the orthographic projection of an active pattern on the substrate 101, and the overlapping area can be a channel of the thin film transistor. The second insulating layer is used to insulate the first gate layer from the second gate layer. The second gate layer includes a plurality of second gate patterns, each of which can be used to constitute a plate of a storage capacitor in a pixel circuit. The interlayer dielectric layer is used to insulate the second gate layer from the first source and drain layer formed subsequently.

[0199] Step S202 : forming a first source-drain electrode layer and an initial planarization layer on a side of the interlayer dielectric layer away from the substrate.

[0200] In the embodiment of the present application, the first source and drain electrode layer at least includes a first wiring layer of the power wiring 104. The first wiring layer includes a first material layer a1, a second material layer a2 and a third material layer a3 stacked in sequence in a direction away from the base substrate 101.

[0201] Optionally, the materials of the first material layer a1 and the third material layer a3 may both be titanium (Ti), and the material of the second material layer a2 may be aluminum (Al). That is, the first wiring layer may be a triple-layer structure of Ti / Al / Ti.

[0202] In the embodiment of the present application, the initial flat layer (initial organic film layer) has at least one through groove area 105a, and the through groove area 105a is used to expose the first target area m of the first layer wiring. In addition, the initial flat layer also includes a pattern for forming a blocking structure 103 in the display panel 10, for example, the initial flat layer includes at least one annular pattern surrounding the display area 101a, and the annular pattern is used to form a blocking dam in the blocking structure 103.

[0203] The through-groove region 105 a and the annular pattern used to form a blocking dam in the blocking structure 103 are disposed adjacent to each other, that is, the through-groove region 105 a and the blocking structure 103 are disposed adjacent to each other.

[0204] Step S203 , forming an anode layer of a plurality of pixel units on a side of the initial planar layer away from the base substrate.

[0205] In the embodiment of the present application, the process of forming the anode layer includes: forming an anode film on the side of the initial flat layer away from the base substrate 101, and processing the anode film using a patterning process to form the anode layer of multiple pixel units 102. The patterning process includes: photoresist coating, exposure, development, etching, and removal of the photoresist.

[0206] The developer used in the development process of preparing the anode layer will affect the first target area m of the first wiring layer, and will have a greater impact on the second material layer a2 of the first wiring layer.

[0207] For example, before forming the anode layer, the first boundary a11 of the first material layer a1 of the first routing layer located in the first target area m, the second boundary a21 of the second material layer a2, and the third boundary a31 of the third material layer a3 are collinear. After forming the anode layer, the developer used to prepare the anode layer will perform side engraving on the second material layer a2. The orthographic projection of the second material layer a2 of the first routing layer located in the first target area m on the base substrate 101 is located within the orthographic projection of the third material layer a3 on the base substrate 101, and the first boundary a11 of the first material layer a1 of the first routing layer located in the first target area m and the third boundary a31 of the third material layer a3 are collinear. That is, after forming the anode layer, the first routing layer has an I-shaped structure. Among them, the first boundary a11, the second boundary a21, and the third boundary a31 all extend along the first direction X.

[0208] Since the first routing layer needs to be etched later, in order to distinguish the first routing layer before and after etching, the layer before etching is referred to as the first initial routing layer, and the layer after etching is referred to as the first routing layer.

[0209] Step S204 , etching the third material layer of the first initial wiring layer located in the first target area and etching the initial planar layer using an etching process to obtain a first wiring layer and a first planar layer.

[0210] In the embodiment of the present application, since the portion of the first initial wiring layer located in the first target area m is exposed to the outside and is affected by the developer of the anode layer in the above step S203 to present an I-shaped structure, an etching process can be used to etch the third material layer a3 of the first initial wiring layer located in the first target area m, thereby obtaining the first wiring layer. This process can be called a TTE (Top Ti Etch) process.

[0211] refer to Fig.11 In the first wiring layer obtained by the etching process, the orthographic projection of the third material layer a3 of the first target area m on the base substrate 101 is located within the orthographic projection of the second material layer a2 of the first target area m on the base substrate 101. That is, the I-shaped structure of the first initial wiring layer can be eliminated, so that the final first layer wiring has a step structure.

[0212] It should be noted that, in the process of etching the third material layer a3 of the first target area m, in order to ensure that the third material layer a3 is fully etched, a portion of the initial flat layer may also be etched to obtain the first flat layer (the first flat layer is the first organic film layer 105) that is finally formed. In addition, the formed first flat layer has a groove area 105b, and the thickness of the portion of the first flat layer located in the groove area 105b is less than the thickness of the portion located in other areas.

[0213] refer to Fig.15 The etching process includes: coating a photoresist on the side of the initial organic film layer and the first target area m of the first initial wiring layer away from the substrate; exposing the photoresist using a mask; developing the photoresist using a developer to remove the exposed portion of the photoresist; using an etching process to remove the third material layer of the first initial wiring layer located in the first target area and the portion of the initial organic film layer not protected by the photoresist; and removing the remaining photoresist.

[0214] In the examples of this application, refer to Figure 2 and Figure 7The mask has a plurality of mask openings, each of which has a first mask boundary extending along the first direction X. The first mask boundary is used to form a third boundary a31 of the third material layer a3 after etching, and the orthographic projection of the first mask boundary on the base substrate 101 is located within the orthographic projection of the first material layer a1 on the base substrate 101. Moreover, the distance between the first mask boundary and the first boundary a11 in the second direction Y is greater than 3 μm. Thus, the distance between the third boundary a13 and the first boundary a11 in the second direction Y can be greater than 3 μm.

[0215] Furthermore, the first mask boundary is also used to form a first groove boundary 105b1 of the groove region 105b of the first organic film layer 105 after etching. The first groove boundary 105b1 is close to the first wiring layer of the power wiring 104 and extends along the first direction X. Fig.11 The thickness of the first organic film layer 105 in the groove area 105b is less than the thickness of other areas outside the groove area 105b. The groove area is used to cover the second target area n of the first wiring layer of the power wiring 104. The second target area n and the first target area m are adjacent in the first direction X.

[0216] The mask opening also has a second mask boundary extending along the second direction Y. The through-groove region 105a is located on one side of the second mask boundary, and the second mask boundary is used to form a second groove boundary 105b2 of the groove region 105b of the first organic film layer 105 away from the through-groove region 105a and extending along the second direction Y. The groove region 105b also has a third groove boundary 105b3 adjacent to the through-groove region 105a and extending along the second direction Y. The distance between the second groove boundary 105b2 and the third groove boundary 105b3 in the first direction X is greater than 3 μm.

[0217] Step S205 , forming a pixel defining layer, a light emitting layer and a cathode layer in sequence on a side of the anode layer away from the base substrate.

[0218] In the embodiment of the present application, the pixel defining layer may have a plurality of hollow regions, each of which may be used to expose an anode pattern in the anode layer. The preparation process of the pixel defining layer includes: forming a pixel defining film on a side of the anode layer away from the base substrate 101, and processing the pixel defining film using a patterning process to obtain the pixel defining layer.

[0219] If the etching process is not used to etch the third material layer a3 (the first wiring layer is in an I-shaped structure) of the first target area m, after the pixel definition layer is prepared, the pixel definition material will remain in the I-shaped structure. Usually, the pixel definition material is an organic material (such as polyimide PI), so the pixel definition material will absorb water and oxygen, which may cause some impact on the display of the display panel 10.

[0220] However, the solution of the embodiment of the present application has eliminated the I-shaped structure of the first wiring layer through the above-mentioned step S204. Therefore, after the pixel definition layer is prepared, there will usually be no pixel definition material remaining at the position of the first wiring layer, and thus the display of the display panel 10 will not be affected.

[0221] After the preparation of the pixel definition layer is completed, the light-emitting layer and the cathode layer can be prepared in sequence, and then the preparation of multiple pixel units 102 is completed to realize the display of the display panel 10. Generally, the cathode layer of multiple pixel units 102 can be a common film layer, and the cathode layer can be located in the peripheral area 101b in addition to the display area 101a. In addition, the boundary of the cathode layer in the peripheral area 101b is located on the side of the through groove area 105a close to the display area 101a, so as to avoid the cathode layer being directly connected to the power supply wiring 104 of different signals through the through groove area 105a, thereby preventing a short circuit.

[0222] Step S206: forming a packaging film layer on a side of the cathode layer away from the base substrate.

[0223] In the embodiment of the present application, the packaging film layer may include: a first film layer, a second film layer and a third film layer stacked in a direction away from the base substrate 101 .

[0224] Optionally, the first film layer and the third film layer may be made of an inorganic material, and the second film layer may be made of an organic material. For example, the first film layer and the third film layer may be made of one or more inorganic oxides such as SiNx (silicon nitride), SiOx (silicon oxide) and SiOxNy (silicon oxynitride). The second film layer may be made of a resin material. The resin may be a thermoplastic resin or a thermoplastic resin, the thermoplastic resin may include an acrylic (PMMA) resin, and the thermosetting resin may include an epoxy resin.

[0225] It should be noted that the second film layer can be located in the area surrounded by the blocking structure 103, and the first film layer and the third film layer can cover the area surrounded by the blocking structure 103 and cover the blocking structure 103. That is, the orthographic projections of the first film layer and the third film layer on the base substrate 101 can be located on the side of the blocking structure 103 away from the display area 101a, that is, can be located in the first target area m of the first wiring layer.

[0226] Therefore, by etching the third layer of wiring in the first initial wiring layer located in the first target area m, the first wiring layer finally formed is prevented from being in an I-shape, thereby preventing the first film layer and the third film layer of the packaging film layer from cracking in the first target area m.

[0227] Optionally, the second film layer may be manufactured by IJP method. The first film layer and the third film layer may be manufactured by CVD method.

[0228] Since the above step S204 has removed the I-shaped structure of the first wiring layer, even if the first film layer and the third film layer of the packaging film layer cover the first target area m, they will not break due to the existence of the I-shaped structure, but can climb layer by layer on the step structure of the first target area m, thereby avoiding the formation of an invasion channel for water and oxygen, and avoiding the occurrence of black spots in the display area 101a.

[0229] The second implementation method is Fig.16 FIG. 1 is a flow chart of another method for manufacturing a display panel provided in an embodiment of the present application. Taking the power supply wiring 104 including the first wiring layer as an example, refer to Fig.16 , the method comprising:

[0230] Step S301: forming an active layer, a first insulating layer, a first gate layer, a second insulating layer, a second gate layer and an interlayer dielectric layer in sequence on one side of a substrate.

[0231] In the embodiment of the present application, the specific process of step S301 can refer to the relevant description in the above-mentioned step S201, and the embodiment of the present application will not be repeated here.

[0232] Step S302 : forming a first source and drain electrode layer and an initial planarization layer on a side of the interlayer dielectric layer away from the substrate.

[0233] In the embodiment of the present application, the specific process of step S302 can refer to the relevant description in the above-mentioned step S202, and the embodiment of the present application will not be repeated here.

[0234] Step S303 , forming an anode layer of a plurality of pixel units on a side of the initial planar layer away from the base substrate.

[0235] In the embodiment of the present application, the specific process of step S303 can refer to the relevant description in the above-mentioned step S203, and the embodiment of the present application will not be repeated here.

[0236] Step S304 , forming a pixel defining layer on a side of the anode layer away from the base substrate.

[0237] In the embodiment of the present application, the pixel defining layer may have a plurality of hollow regions, each of which may be used to expose an anode pattern in the anode layer. The preparation process of the pixel defining layer includes: forming a pixel defining film on a side of the anode layer away from the base substrate 101, and processing the pixel defining film using a patterning process to obtain the pixel defining layer.

[0238] Since the etching process is not used to etch the third material layer a3 of the first target area m after the anode layer is prepared, the first wiring layer has an I-shaped structure. Therefore, after the pixel definition layer is prepared, the first wiring layer has a retracted area, and part of the material of the pixel definition layer will be located in the retracted area (that is, the pixel definition material will remain in the I-shaped structure). The retracted area is the area where the first wiring layer has the first material layer a1 and the third material layer a3, and does not have the second material layer a2.

[0239] Step S305 , etching the third material layer of the first initial wiring layer located in the first target area and etching the initial planar layer using an etching process to obtain a first wiring layer and a first planar layer.

[0240] In the embodiment of the present application, since the portion of the first initial wiring layer located in the first target area m is exposed, and is affected by the developer of the anode layer in the above step S303 to form an I-shaped structure, and pixel defining material remains in the I-shaped structure in the above step S304, in order to eliminate the I-shaped structure and remove the remaining pixel defining material, an etching process can be used to etch the third material layer a3 of the first initial wiring layer located in the first target area m, thereby obtaining the first wiring layer. This process can be called a TTE process.

[0241] refer to Fig.11 In the first wiring layer obtained by the etching process, the orthographic projection of the third material layer a3 of the first target area m on the base substrate 101 is located within the orthographic projection of the second material layer a2 of the first target area m on the base substrate 101. That is, the I-shaped structure of the first initial wiring layer can be eliminated, so that the final first layer wiring has a step structure. In addition, the pixel defining material remaining in the I-shaped structure can be removed.

[0242] It should be noted that, in the process of etching the third material layer a3 of the first target area m, in order to ensure sufficient etching of the third material layer a3, a portion of the initial flat layer may also be etched to finally form a first flat layer. In addition, the formed first flat layer has a groove area 105b, and the thickness of the portion of the first flat layer located in the groove area 105b is less than the thickness of the portion located in other areas.

[0243] In addition, the specific process of the etching process can refer to the above-mentioned step S204, and the embodiment of the present application will not be repeated here.

[0244] Step S306 , forming a light emitting layer and a cathode layer in sequence on a side of the pixel defining layer away from the base substrate.

[0245] After the preparation of the pixel definition layer is completed, the light-emitting layer and the cathode layer can be prepared in sequence, and then the preparation of multiple pixel units 102 is completed to realize the display of the display panel 10. Generally, the cathode layer of multiple pixel units 102 can be a common film layer, and the cathode layer can be located in the peripheral area 101b in addition to the display area 101a. In addition, the boundary of the cathode layer in the peripheral area 101b is located on the side of the through groove area 105a close to the display area 101a, so as to avoid the cathode layer being directly connected to the power supply wiring 104 of different signals through the through groove area 105a, thereby preventing a short circuit.

[0246] Step S307 , forming a packaging film layer on a side of the cathode layer away from the base substrate.

[0247] In the embodiment of the present application, the specific process of step S307 can refer to the relevant description in the above-mentioned step S206, and the embodiment of the present application will not be repeated here.

[0248] In the first and second implementations above, Figure 7 The cross-sectional view in the DD direction is used as an example for detailed introduction. Figures 17 to 32 The steps include: forming an active film; patterning the active film (coating photoresist, exposing, developing, etching and removing the photoresist); forming a first insulating layer; forming a first gate film; patterning the first gate film (coating photoresist, exposing, developing, etching and removing the photoresist); forming a second insulating layer; forming a second gate film; patterning the second gate film (coating photoresist, exposing, developing, etching and removing the photoresist); forming an interlayer dielectric layer; forming a first source-drain film (the first source-drain film is used to form the source and drain of the thin film transistor, and The first layer of power routing), the first source and drain film includes a first material layer, a second material layer and a third material layer; photoresist is coated on the side of the first source and drain film away from the substrate; the photoresist is exposed using a mask, and the photoresist is developed using a developer; the first source and drain film is etched to form a first routing layer; the remaining photoresist is removed; a first flat film is formed; the first flat film is patterned (coated with photoresist, exposed, developed, etched and removed from the photoresist), and after the patterning, a through groove area of ​​the first flat layer is formed, exposing the first target area of ​​the first routing layer. Fig.32 It can be seen that after the first flat film is patterned, affected by the process, the second material layer a2 is inwardly engraved relative to the first material layer a1 and the third material layer a3; an anode film is formed; and the anode film is patterned (coating photoresist, exposing, developing, etching and removing the photoresist). Fig.34It can be seen that after the anode film is patterned, affected by the process, the second material layer a2 is further inscribed relative to the first material layer a1 and the third material layer a3.

[0249] refer to Fig.35 and Fig.36 After the anode film is patterned, a pixel defining film is directly formed, and the pixel defining film is patterned, which will cause residual pixel defining material to exist in the recessed area of ​​the second material layer a2 relative to the first material layer a1 and the third material layer a3. If the third material layer a3 is not subsequently etched, the first wiring layer will have an I-shaped structure, and there will be residual pixel defining material in the I-shaped structure. This will cause the subsequent encapsulation film to crack at the location of the I-shaped structure, and due to the presence of residual pixel defining material (organic material), a water and oxygen invasion channel will be formed, affecting the yield of the pixel unit in the display area.

[0250] In the embodiment of the present application, as an optional implementation method, refer to Figures 37 to 40 After patterning the anode film, the third material layer a3 is etched to eliminate the I-shaped structure of the first wiring layer. The steps include: coating photoresist; exposing the photoresist with a mask and developing the photoresist with a developer; etching the third material layer; and removing the remaining photoresist. In this way, the I-shaped structure of the first wiring layer is eliminated, thereby avoiding the residue of the subsequent pixel defining material and the generation of cracks in the subsequent encapsulation film, thereby ensuring the yield of the pixel unit in the display area.

[0251] As another optional implementation, refer to Figure 41 to Figure 44 After patterning the pixel definition film, the third material layer a3 is etched to eliminate the I-shaped structure of the first wiring layer and remove the residual pixel definition material. The steps include: coating photoresist; exposing the photoresist with a mask and developing the photoresist with a developer; etching the third material layer; removing the remaining photoresist. In this way, the I-shaped structure of the first wiring layer is eliminated, and the residual pixel definition material can be removed, so as to avoid cracks in the subsequent packaging film and ensure the yield of the pixel unit in the display area.

[0252] The third implementation method is Fig.45 FIG. 1 is a flow chart of another method for manufacturing a display panel provided in an embodiment of the present application. Taking the power supply wiring 104 including the first layer wiring and the second layer wiring as an example, refer to FIG. Fig.45 , the method comprising:

[0253] Step S401: forming an active layer, a first insulating layer, a first gate layer, a second insulating layer, a second gate layer and an interlayer dielectric layer in sequence on one side of a substrate.

[0254] In the embodiment of the present application, the specific process of step S401 can refer to the relevant description in the above-mentioned step S201, and the embodiment of the present application will not be repeated here.

[0255] Step S402 : forming a first source-drain electrode layer, a first initial planarization layer, a second source-drain electrode layer and a second initial planarization layer on a side of the interlayer dielectric layer away from the substrate.

[0256] In the embodiment of the present application, the first source-drain layer at least includes the second routing layer of the power routing 104. The second source-drain layer at least includes the first routing layer of the power routing 104. The orthographic projection of the first routing layer on the base substrate 101 covers the orthographic projection of the second routing layer on the base substrate 101. The first routing layer and the second routing layer both include a first material layer a1, a second material layer a2, and a third material layer a3 stacked in sequence in a direction away from the base substrate 101.

[0257] Optionally, the first material layer a1 and the third material layer a3 may both be made of titanium (Ti), and the second material layer a2 may be made of aluminum (Al). That is, the first wiring layer and the second wiring layer may both be a triple-layer structure of Ti / Al / Ti.

[0258] In the embodiment of the present application, the first initial flat layer and the second initial flat layer have at least one through-groove area 105a. Moreover, since the orthographic projection of the first wiring layer on the base substrate 101 covers the orthographic projection of the second wiring layer on the base substrate 101, the through-groove area 105a can only expose the first target area m of the first wiring layer, and will not expose the second wiring layer. Moreover, the first initial flat layer and the second initial flat layer also include a pattern for forming a blocking structure 103 in the display panel 10, for example, the first initial flat layer and the second initial flat layer both include at least one annular pattern surrounding the display area 101a, and the annular pattern is used to form a blocking dam in the blocking structure 103.

[0259] The through-groove region 105 a and the annular pattern used to form a blocking dam in the blocking structure 103 are disposed adjacent to each other, that is, the through-groove region 105 a and the blocking structure 103 are disposed adjacent to each other.

[0260] Step S403 , forming an anode layer of a plurality of pixel units on a side of the second initial planar layer away from the base substrate.

[0261] In the embodiment of the present application, the process of forming the anode layer includes: forming an anode film on the side of the second initial flat layer away from the base substrate 101, and processing the anode film using a patterning process to form the anode layer of multiple pixel units 102. The patterning process includes: photoresist coating, exposure, development, etching, and removing the photoresist.

[0262] The developer used in the development process of preparing the anode layer will affect the first target area m of the first wiring layer, and will have a greater impact on the second material layer a2 of the first wiring layer.

[0263] For example, before forming the anode layer, the first boundary a11 of the first material layer a1 of the first routing layer located in the first target area m, the second boundary a21 of the second material layer a2, and the third boundary a31 of the third material layer a3 are collinear. After forming the anode layer, the developer used to prepare the anode layer will perform side engraving on the second material layer a2. The orthographic projection of the second material layer a2 of the first routing layer located in the first target area m on the base substrate 101 is located within the orthographic projection of the third material layer a3 on the base substrate 101, and the first boundary a11 of the first material layer a1 of the first routing layer located in the first target area m and the third boundary a31 of the third material layer a3 are collinear. That is, after forming the anode layer, the first routing layer has an I-shaped structure. Among them, the first boundary a11, the second boundary a21, and the third boundary a31 all extend along the first direction X.

[0264] Since the first routing layer needs to be etched later, in order to distinguish the first routing layer before and after etching, the first routing layer before etching is referred to as the first initial routing layer, and the first routing layer after etching is referred to as the first routing layer. In addition, the first flat layer and the second flat layer may also be etched. For the convenience of description, the first flat layer and the second flat layer before etching are collectively referred to as the initial flat layer, and the first flat layer and the second flat layer after etching are collectively referred to as the flat layer.

[0265] Step S404: Etch the third material layer of the first initial wiring layer located in the first target area and etch the initial planar layer using an etching process to obtain a first wiring layer and a planar layer.

[0266] In the embodiment of the present application, since the portion of the first initial wiring layer located in the first target area m is exposed to the outside and is affected by the developer of the anode layer in the above step S403 to present an I-shaped structure, an etching process can be used to etch the third material layer a3 of the first initial wiring layer located in the first target area m, thereby obtaining the first wiring layer. This process can be called a TTE process.

[0267] refer to Fig.11In the first wiring layer obtained by the etching process, the orthographic projection of the third material layer a3 of the first target area m on the base substrate 101 is located within the orthographic projection of the second material layer a2 of the first target area m on the base substrate 101. That is, the I-shaped structure of the first initial wiring layer can be eliminated, so that the final first layer wiring has a step structure.

[0268] It should be noted that, in the process of etching the third material layer a3 of the first target area m, in order to ensure sufficient etching of the third material layer a3, a portion of the initial flat layer may also be etched to obtain a final flat layer. In addition, the formed flat layer has a groove area 105b, and the thickness of the portion of the flat layer located in the groove area 105b is less than the thickness of the portion located in other areas.

[0269] Step S405 , forming a pixel defining layer, a light emitting layer and a cathode layer in sequence on a side of the anode layer away from the base substrate.

[0270] In the embodiment of the present application, the specific process of step S405 can refer to the relevant description in the above-mentioned step S205, and the embodiment of the present application will not be repeated here.

[0271] Step S406: forming a packaging film layer on a side of the cathode layer away from the base substrate.

[0272] In the embodiment of the present application, the specific process of step S406 can refer to the relevant description in the above-mentioned step S206, and the embodiment of the present application will not be repeated here.

[0273] The fourth implementation method is Fig.46 FIG. 1 is a flow chart of another method for manufacturing a display panel provided in an embodiment of the present application. Taking the power supply wiring 104 including the first layer wiring and the second layer wiring as an example, refer to FIG. Fig.46 , the method comprising:

[0274] Step S501: forming an active layer, a first insulating layer, a first gate layer, a second insulating layer, a second gate layer and an interlayer dielectric layer in sequence on one side of a substrate.

[0275] In the embodiment of the present application, the specific process of step S501 can refer to the relevant description in the above-mentioned step S201, and the embodiment of the present application will not be repeated here.

[0276] Step S502 : forming a first source-drain electrode layer, a first initial planarization layer, a second source-drain electrode layer and a second initial planarization layer on a side of the interlayer dielectric layer away from the substrate.

[0277] In the embodiment of the present application, the specific process of step S502 can refer to the relevant description in the above-mentioned step S402, and the embodiment of the present application will not be repeated here.

[0278] Step S503 , forming an anode layer of a plurality of pixel units on a side of the second initial planar layer away from the base substrate.

[0279] In the embodiment of the present application, the specific process of step S503 can refer to the relevant description in the above-mentioned step S403, and the embodiment of the present application will not be repeated here.

[0280] Step S504 , forming a pixel defining layer on a side of the anode layer away from the base substrate.

[0281] In the embodiment of the present application, the specific process of step S504 can refer to the relevant description in the above-mentioned step S304, and the embodiment of the present application will not be repeated here.

[0282] Step S505 , etching the third material layer of the first initial wiring layer located in the first target area and etching the initial planar layer using an etching process to obtain a first wiring layer and a planar layer.

[0283] In the embodiment of the present application, since the portion of the first initial wiring layer located in the first target area m is exposed, and is affected by the developer of the anode layer in the above step S503 to form an I-shaped structure, and pixel defining material remains in the I-shaped structure in the above step S504, in order to eliminate the I-shaped structure and remove the remaining pixel defining material, an etching process can be used to etch the third material layer a3 of the first initial wiring layer located in the first target area m, thereby obtaining the first wiring layer. This process can be called a TTE process.

[0284] refer to Fig.11 In the first wiring layer obtained by the etching process, the orthographic projection of the third material layer a3 of the first target area m on the base substrate 101 is located within the orthographic projection of the second material layer a2 of the first target area m on the base substrate 101. That is, the I-shaped structure of the first initial wiring layer can be eliminated, so that the final first layer wiring has a step structure. In addition, the pixel defining material remaining in the I-shaped structure can be removed.

[0285] It should be noted that, in the process of etching the third material layer a3 of the first target area m, in order to ensure sufficient etching of the third material layer a3, a portion of the initial flat layer may also be etched to obtain a final flat layer. In addition, the formed flat layer has a groove area 105b, and the thickness of the portion of the flat layer located in the groove area 105b is less than the thickness of the portion located in other areas.

[0286] Step S506 : forming a light emitting layer and a cathode layer in sequence on a side of the pixel defining layer away from the base substrate.

[0287] In the embodiment of the present application, the specific process of step S506 can refer to the relevant description in the above-mentioned step S306, and the embodiment of the present application will not be repeated here.

[0288] Step S507 , forming a packaging film layer on a side of the cathode layer away from the base substrate.

[0289] In the embodiment of the present application, the specific process of step S507 can refer to the relevant description in the above-mentioned step S206, and the embodiment of the present application will not be repeated here.

[0290] The fifth implementation method is Fig.47 FIG. 1 is a flow chart of another method for preparing a display panel 10 provided in an embodiment of the present application. Taking the power supply wiring 104 including the first wiring layer, the second wiring layer and the third wiring layer as an example, refer to FIG. Fig.47 , the method comprising:

[0291] Step S601: forming an active layer, a first insulating layer, a first gate layer, a second insulating layer, a second gate layer, a third insulating layer, an oxide layer, a fourth insulating layer, a third gate layer and an interlayer dielectric layer in sequence on one side of the substrate.

[0292] In an embodiment of the present application, the active layer includes a plurality of active patterns, each of which can be used to form a thin film transistor in a pixel circuit included in the pixel unit 102. The first insulating layer is used to insulate the active layer from the first gate layer. The first gate layer includes a plurality of first gate patterns, and the orthographic projection of each first gate pattern on the substrate 101 partially overlaps with the orthographic projection of an active pattern on the substrate 101, and the overlapping area can be a channel of a thin film transistor. The second insulating layer is used to insulate the first gate layer from the second gate layer. The second gate layer includes a plurality of second gate patterns and a plurality of third gate patterns, each of which can be used to form a plate of a storage capacitor in a pixel circuit, and each third gate pattern can be used to form a bottom gate of an oxide thin film transistor in a pixel circuit. The third insulating layer is used to insulate the second gate layer from the oxide layer. The oxide layer includes a plurality of oxide patterns, each of which is used to form an oxide thin film transistor. The fourth insulating layer is used to insulate the oxide layer from the third gate layer. The third gate layer includes at least a plurality of fourth gate patterns, each of which can be used to form a top gate of an oxide thin film transistor. The interlayer dielectric layer is used to insulate the third gate layer from the first source and drain layer formed subsequently.

[0293] Step S602 : forming a first source-drain electrode layer, a first initial planarization layer, a second source-drain electrode layer, a second initial planarization layer, a third source-drain electrode layer and a third initial planarization layer on a side of the interlayer dielectric layer away from the substrate.

[0294] In the embodiment of the present application, the first source-drain layer at least includes the third routing layer of the power routing 104. The second source-drain layer at least includes the second routing layer of the power routing 104. The third source-drain layer at least includes the first routing layer of the power routing 104, and the orthographic projection of the first routing layer on the base substrate 101 covers the orthographic projection of the second routing layer on the base substrate 101, and covers the orthographic projection of the third routing layer on the base substrate 101. The first routing layer, the second routing layer, and the third routing layer all include a first material layer a1, a second material layer a2, and a third material layer a3 stacked in sequence in a direction away from the base substrate 101.

[0295] Optionally, the first material layer a1 and the third material layer a3 may both be made of titanium (Ti), and the second material layer a2 may be made of aluminum (Al). That is, the first wiring layer, the second wiring layer and the third wiring layer may all be a triple-layer structure of Ti / Al / Ti.

[0296] In the embodiment of the present application, the first initial flat layer, the second initial flat layer and the third initial flat layer have at least one through-groove area 105a. Moreover, since the orthographic projection of the first wiring layer on the base substrate 101 covers the orthographic projection of the second wiring layer and the third wiring layer on the base substrate 101, the through-groove area 105a can only expose the first target area m of the first wiring layer, and will not expose the second wiring layer and the third wiring layer. Moreover, the first initial flat layer, the second initial flat layer and the third initial flat layer also include a pattern for forming a blocking structure 103 in the display panel 10, for example, the first initial flat layer, the second initial flat layer and the third initial flat layer all include at least one annular pattern surrounding the display area 101a, and the annular pattern is used to form a blocking dam in the blocking structure 103.

[0297] The through-groove region 105 a and the annular pattern used to form a blocking dam in the blocking structure 103 are disposed adjacent to each other, that is, the through-groove region 105 a and the blocking structure 103 are disposed adjacent to each other.

[0298] Step S603 , forming an anode layer of a plurality of pixel units on a side of the third initial planar layer away from the base substrate.

[0299] In the embodiment of the present application, the process of forming the anode layer includes: forming an anode film on the side of the third initial flat layer away from the base substrate 101, and processing the anode film using a patterning process to form the anode layer of multiple pixel units 102. The patterning process includes: photoresist coating, exposure, development, etching, and removing the photoresist.

[0300] The developer used in the development process of preparing the anode layer will affect the first target area m of the first wiring layer, and will have a greater impact on the second material layer a2 of the first wiring layer.

[0301] For example, before forming the anode layer, the first boundary a11 of the first material layer a1 of the first routing layer located in the first target area m, the second boundary a21 of the second material layer a2, and the third boundary a31 of the third material layer a3 are collinear. After forming the anode layer, the developer used to prepare the anode layer will perform side engraving on the second material layer a2. The orthographic projection of the second material layer a2 of the first routing layer located in the first target area m on the base substrate 101 is located within the orthographic projection of the third material layer a3 on the base substrate 101, and the first boundary a11 of the first material layer a1 of the first routing layer located in the first target area m and the third boundary a31 of the third material layer a3 are collinear. That is, after forming the anode layer, the first routing layer has an I-shaped structure. Among them, the first boundary a11, the second boundary a21, and the third boundary a31 all extend along the first direction X.

[0302] Since the first wiring layer needs to be etched later, in order to distinguish the first wiring layer before and after etching, the first wiring layer before etching is referred to as the first initial wiring layer, and the first wiring layer after etching is referred to as the first wiring layer. In addition, the first flat layer, the second flat layer, and the third flat layer may also be etched. For the convenience of description, the first flat layer, the second flat layer, and the third flat layer before etching are collectively referred to as the initial flat layer, and the first flat layer, the second flat layer, and the third flat layer after etching are collectively referred to as the flat layer.

[0303] Step S604 , etching the third material layer of the first initial wiring layer located in the first target area and etching the initial planar layer using an etching process to obtain a first wiring layer and a planar layer.

[0304] In the embodiment of the present application, the specific process of step S604 can refer to the relevant description in the above-mentioned step S404, and the embodiment of the present application will not be repeated here.

[0305] Step S605 , forming a pixel defining layer, a light emitting layer and a cathode layer in sequence on a side of the anode layer away from the base substrate.

[0306] In the embodiment of the present application, the specific process of step S605 can refer to the relevant description in the above-mentioned step S205, and the embodiment of the present application will not be repeated here.

[0307] Step S606: forming a packaging film layer on a side of the cathode layer away from the base substrate.

[0308] In the embodiment of the present application, the specific process of step S606 can refer to the relevant description in the above-mentioned step S206, and the embodiment of the present application will not be repeated here.

[0309] The sixth implementation method is: Fig.48 FIG. 1 is a flow chart of another method for manufacturing a display panel provided in an embodiment of the present application. Taking the power supply wiring 104 including the first wiring layer, the second wiring layer and the third wiring layer as an example, refer to FIG. Fig.48 , the method comprising:

[0310] Step S701: forming an active layer, a first insulating layer, a first gate layer, a second insulating layer, a second gate layer, a third insulating layer, an oxide layer, a fourth insulating layer, a third gate layer and an interlayer dielectric layer in sequence on one side of the substrate.

[0311] In the embodiment of the present application, the specific process of step S701 can refer to the relevant description in the above step S601, and the embodiment of the present application will not be repeated here.

[0312] Step S702 : forming a first source-drain electrode layer, a first initial planarization layer, a second source-drain electrode layer, a second initial planarization layer, a third source-drain electrode layer and a third initial planarization layer on a side of the interlayer dielectric layer away from the substrate.

[0313] In the embodiment of the present application, the specific process of step S702 can refer to the relevant description in the above step S602, and the embodiment of the present application will not be repeated here.

[0314] Step S703 , forming an anode layer of a plurality of pixel units on a side of the third initial planar layer away from the base substrate.

[0315] In the embodiment of the present application, the specific process of step S703 can refer to the relevant description in the above step S603, and the embodiment of the present application will not be repeated here.

[0316] Step S704 , forming a pixel defining layer on a side of the anode layer away from the base substrate.

[0317] In the embodiment of the present application, the specific process of step S704 can refer to the relevant description in the above-mentioned step S304, and the embodiment of the present application will not be repeated here.

[0318] Step S705 , etching the third material layer of the first initial wiring layer located in the first target area and etching the initial planar layer using an etching process to obtain a first wiring layer and a planar layer.

[0319] In the embodiment of the present application, the specific process of step S705 can refer to the relevant description in the above step S505, and the embodiment of the present application will not be repeated here.

[0320] Step S706 : forming a light emitting layer and a cathode layer in sequence on a side of the pixel defining layer away from the base substrate.

[0321] In the embodiment of the present application, the specific process of step S706 can refer to the relevant description in the above-mentioned step S306, and the embodiment of the present application will not be repeated here.

[0322] Step S507 , forming a packaging film layer on a side of the cathode layer away from the base substrate.

[0323] In the embodiment of the present application, the specific process of step S707 can refer to the relevant description in the above-mentioned step S206, and the embodiment of the present application will not be repeated here.

[0324] In the examples of this application, refer to Fig.49 and Fig.50 It can be seen that the area of ​​the first wiring layer that is not protected by the organic film layer (the first target area) will present an I-shaped structure, and the area protected by the organic film layer will not present an I-shaped structure. Fig.51 After the pixel defining layer is prepared, there will be residual pixel defining material in the I-shaped structure.

[0325] In order to prevent the area of ​​the first wiring layer that is not protected by the organic film layer from forming an I-shaped structure, an etching process may be used to etch the third material layer a3 of the first wiring layer. Fig.52 After the etching is completed, there may still be an indentation of the second material layer a2. Fig.53 and Fig.54 In order to ensure the removal of the I-shaped structure, it is necessary to ensure that the distance between the third boundary of the third wiring layer a3 and the first boundary of the first wiring layer a1 is greater than 3 μm.

[0326] In summary, an embodiment of the present application provides a method for preparing a display panel, wherein the first routing layer of the power routing in the display panel prepared by the method has a first target area exposed by the through groove area of ​​the first organic film layer, and the orthographic projection of the third material layer of the first routing layer located in the first target area on the base substrate is located within the orthographic projection of the second material layer on the base substrate. The orthographic projection of the second material layer of the first routing layer located in the first target area on the base substrate is located within the orthographic projection of the first material layer on the base substrate. Thus, it is possible to prevent the encapsulation film layer subsequently formed on the display panel from generating cracks in the first target area, thereby preventing water and oxygen from invading the display area along the intrusion channels generated by the cracks. The solution of the embodiment of the present application can ensure the luminous effect of the pixel unit in the display area, avoid the occurrence of black spots in the display area, and the yield of the display panel is high, and the display effect of the display panel is good.

[0327] Fig.55 is a schematic diagram of the structure of a display device provided in an embodiment of the present application. Fig.55The display device includes: a power supply component 20 and a display panel 10 provided in the above embodiment. The power supply component 20 is used to supply power to the display panel 10.

[0328] Optionally, the display device may be an LTPO display device, an LTPS display device, or an OLED display device. The display device may be any appropriate display device, including but not limited to any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and an e-book.

[0329] Since the display device can have substantially the same technical effects as the display panel described in the previous embodiment, the technical effects of the display device will not be repeatedly described here for the purpose of brevity.

[0330] The terms used in the embodiments of this application are only used to explain the embodiments of this application, and are not intended to limit this application. Unless otherwise defined, the technical terms or scientific terms used in the embodiments of this application should be the common meanings understood by people with general skills in the field to which this application belongs.

[0331] The terms used in the implementation mode of the present application are only used to explain the embodiments of the present application, and are not intended to limit the present application. Unless otherwise defined, the technical terms or scientific terms used in the implementation mode of the present application should be the common meanings understood by people with ordinary skills in the field to which the present application belongs. The words "first", "second", "third" and similar words used in the patent application specification and claims of the present application do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "one" do not indicate a quantity limit, but indicate that there is at least one. Words such as "include" or "include" and similar words mean that the elements or objects appearing in front of "include" or "include" include the elements or objects listed after "include" or "include" and their equivalents, and do not exclude other elements or objects. Words such as "connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0332] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A display panel (10), characterized in that: The display panel (10) comprises: A base substrate (101), wherein the base substrate (101) has a display area (101a) and a peripheral area (101b) surrounding the display area (101a); A plurality of pixel units (102), wherein the plurality of pixel units (102) are located in the display area (101a); A blocking structure (103), the blocking structure (103) surrounding the display area (101a); At least one power supply line (104) is located on one side of the substrate (101), each of the power supply lines (104) is used to receive a power supply signal and is connected to the plurality of pixel units (102); A first organic film layer (105), the first organic film layer (105) being located on a side of the power supply line (104) away from the base substrate (101), and the first organic film layer (105) having at least one through-groove area (105a), an orthographic projection of the through-groove area (105a) on the base substrate (101) and an orthographic projection of the blocking structure (103) on the base substrate (101) being arranged adjacent to each other, and the through-groove area (105a) being used to expose a first target area (m) of the power supply line (104); The power supply wiring (104) comprises at least a first wiring layer, the first wiring layer comprising a first material layer (a1), a second material layer (a2) and a third material layer (a3) ​​stacked in sequence in a direction away from the base substrate (101), the orthographic projection of the third material layer (a3) ​​of the first wiring layer located in the first target area (m) on the base substrate (101) is located within the orthographic projection of the second material layer (a2) on the base substrate (101), and the orthographic projection of the second material layer (a2) of the first wiring layer located in the first target area (m) on the base substrate (101) is located within the orthographic projection of the first material layer (a1) on the base substrate (101).

2. The display panel according to claim 1, characterized in that: The first material layer (a1) of the first routing layer located in the first target area (m) has a first boundary (a11) extending along a first direction (X), the second material layer (a2) of the first routing layer located in the first target area (m) has a second boundary (a21) extending along the first direction (X), and the third material layer (a3) ​​of the first routing layer located in the first target area (m) has a third boundary (a31) extending along the first direction (X); The distance between the first boundary (a11) and the third boundary (a31) in the second direction (Y) is greater than 3 micrometers, the second boundary (a21) is located between the first boundary (a11) and the third boundary (a31), and the second direction (Y) is perpendicular to the first direction (X).

3. The display panel according to claim 1, characterized in that: The first organic film layer (105) has a groove region (105b), the thickness of the first organic film layer (105) in the groove region (105b) is less than the thickness of other regions except the groove region (105b), and the groove region (105b) is used to cover the second target region (n) of the first wiring layer; The second target area (n) and the first target area (m) are adjacent to each other in the first direction (X).

4. The display panel according to claim 3, characterized in that: The groove area (105b) has a first groove boundary (105b1) close to the first wiring layer and extending along the first direction (X), and the third material layer (a3) ​​of the first wiring layer located in the first target area (m) has a third boundary (a31) extending along the first direction (X); The orthographic projection of the first groove boundary (105b1) on the base substrate (101) is collinear with the orthographic projection of the third boundary (a31) on the base substrate (101).

5. The display panel according to claim 4, characterized in that: The groove region (105b) further comprises a second groove boundary (105b2) which is away from the through groove region (105a) and extends along a second direction (Y), and a third groove boundary (105b3) which is adjacent to the through groove region (105a) and extends along the second direction (Y); wherein the second direction (Y) is perpendicular to the first direction (X); The distance between the second groove boundary (105b2) and the third groove boundary (105b3) in the first direction (X) is greater than 3 micrometers.

6. The display panel according to any one of claims 1 to 5, characterized in that: The power wiring (104) comprises a third wiring layer, a second wiring layer and the first wiring layer which are sequentially stacked in a direction away from the base substrate (101); the display panel (10) comprises: a third organic film layer located between the third wiring layer and the second wiring layer, and a second organic film layer located between the second wiring layer and the first wiring layer, and the first organic film layer (105) is located on a side of the first wiring layer away from the base substrate (101); The third routing layer and the second routing layer are connected via an opening in the third organic film layer, and the second routing layer and the first routing layer are connected via an opening in the second organic film layer; the through groove area (105a) is used to expose a first target area (m) of the first routing layer.

7. The display panel according to any one of claims 1 to 5, characterized in that: The power wiring (104) comprises a second wiring layer and the first wiring layer which are sequentially stacked in a direction away from the base substrate (101); the display panel (10) comprises: a second organic film layer located between the second wiring layer and the first wiring layer, and the first organic film layer (105) is located on a side of the first wiring layer away from the base substrate (101); The second wiring layer and the first wiring layer are connected via an opening in the second organic film layer; and the through groove area (105a) is used to expose the first target area (m) of the first wiring layer.

8. The display panel according to any one of claims 1 to 5, characterized in that: The at least one power supply line (104) comprises a first signal power supply line (104a) and a second signal power supply line (104b) spaced apart above the second direction (Y), and the through-slot area (105a) comprises a first sub-through-slot area (105a1) for exposing the first signal power supply line (104a) and a second sub-through-slot area (105a2) for exposing the second signal power supply line (104b); Wherein, the length of the first sub-through groove area (105a1) along the first direction (X) is less than or equal to the length of the second sub-through groove area (105a2) along the first direction (X).

9. The display panel according to any one of claims 1 to 5, characterized in that: The thickness of the second material layer (a2) located in the first target area (m) is less than or equal to the thickness of the second material layer (a2) located in the other areas.

10. The display panel according to claim 9, characterized in that: When the thickness of the second material layer (a2) located in the first target area (m) is less than the thickness of the second material layer (a2) located in the other areas, the surface of the second material layer (a2) located in the first target area (m) is uneven away from the base substrate (101).

11. The display panel according to any one of claims 1 to 5, characterized in that: The blocking structure (103) comprises: a first blocking dam (1031), a second blocking dam (1032) and a third blocking dam (1033) which are sequentially arranged away from the display area (101a); The first organic film layer (105) has two through-groove regions (105a), one of which is located on a side of the third blocking dam (1033) away from the display region (101a), and the other through-groove region (105a) is located between the second blocking dam (1032) and the third blocking dam (1033).

12. The display panel according to claim 11, characterized in that: Each barrier dam in the barrier structure (103) comprises at least one layer of the organic film layers in the display panel (10), and the organic film layers in the display panel (10) comprise: a third organic film layer, a second organic film layer and the first organic film layer; Among them, one of the first organic film layer, the second organic film layer and the third organic film layer is located in an area adjacent to any blocking dam in the blocking structure (103) and where the through groove area (105a) is not provided.

13. The display panel according to any one of claims 1 to 5, characterized in that: In the area of ​​the power supply wiring (104) covered by the organic film layer in the display panel (10), the side edges of the third material layer (a3), the second material layer (a2) and the first material layer (a1) are flat side edges, and the flat side edges are inclined relative to the supporting surface of the base substrate (101); The orthographic projection of the third material layer (a3) ​​on the base substrate (101) is located within the orthographic projection of the second material layer (a2) on the base substrate (101), and the orthographic projection of the second material layer (a2) on the base substrate (101) is located within the orthographic projection of the first material layer (a1) on the base substrate (101).

14. A method for preparing a display panel, characterized in that: The method comprises: Providing a base substrate (101), wherein the base substrate (101) has a display area (101a) and a peripheral area (101b) surrounding the display area (101a); A plurality of pixel units (102), a blocking structure (103) and at least one initial power supply wiring are formed on one side of the base substrate (101); the plurality of pixel units (102) are located in the display area (101a); the blocking structure (103) surrounds the display area (101a); each of the initial power supply wiring is used to receive a power supply signal and is connected to the plurality of pixel units (102); the initial power supply wiring comprises at least a first initial wiring layer, the first initial wiring layer comprising a first material layer (a1), a second material layer (a2) and a third material layer (a3) ​​stacked in sequence in a direction away from the base substrate (101); An initial organic film layer is formed on a side of the initial power supply line away from the base substrate (101), the initial organic film layer having at least one through-groove area (105a), an orthographic projection of the through-groove area (105a) on the base substrate (101) and an orthographic projection of the blocking structure (103) on the base substrate (101) being arranged adjacent to each other, and the through-groove area (105a) is used to expose a first target area (m) of the initial power supply line; The first initial routing layer of the at least one initial power routing line, the third material layer (a3) ​​located in the first target area (m), and the initial organic film layer are etched by an etching process to obtain a first routing layer and a first organic film layer (105) of the at least one power routing line (104), wherein the orthographic projection of the third material layer (a3) ​​of the first routing layer located in the first target area (m) on the base substrate (101) is located within the orthographic projection of the second material layer (a2) on the base substrate (101), and the orthographic projection of the second material layer (a2) of the first routing layer located in the first target area (m) on the base substrate (101) is located within the orthographic projection of the first material layer (a1) on the base substrate (101).

15. The method according to claim 14, characterized in that Forming a plurality of pixel units (102) comprises: sequentially forming an anode layer, a pixel defining layer, a light emitting layer and a cathode layer on a side of the initial organic film layer away from the base substrate (101); The method of etching the third material layer (a3) ​​of the first initial wiring layer of the at least one initial power wiring located in the first target area (m) and etching the initial organic film layer by using an etching process comprises: After forming the anode layer and before forming the pixel defining layer, the etching process is used to etch the third material layer (a3) ​​of the first initial wiring layer of the at least one initial power wiring located in the first target area (m) and to etch the initial organic film layer.

16. The method according to claim 15, characterized in that Before forming the anode layer, the first initial wiring layer is located in the first target area (m) at a first boundary (a11) of the first material layer (a1), a second boundary (a21) of the second material layer (a2), and a third boundary (a31) of the third material layer (a3) ​​on a collinear basis; After the anode layer is formed, the orthographic projection of the second material layer (a2) of the first initial wiring layer located in the first target area (m) on the base substrate (101) is located within the orthographic projection of the third material layer (a3) ​​on the base substrate (101), and the first boundary (a11) of the first material layer (a1) of the first initial wiring layer located in the first target area (m) and the third boundary (a31) of the third material layer (a3) ​​are collinear; The first boundary (a11), the second boundary (a21) and the third boundary (a31) all extend along the first direction (X).

17. The method according to claim 16, characterized in that Forming a plurality of pixel units (102) comprises: sequentially forming an anode layer, a pixel defining layer, a light emitting layer and a cathode layer on a side of the first organic film layer (105) away from the base substrate (101); The method of etching the third material layer (a3) ​​of the first initial wiring layer of the at least one initial power wiring located in the first target area (m) and etching the initial organic film layer by using an etching process comprises: After forming the pixel defining layer and before forming the light emitting layer, the etching process is used to etch the third material layer (a3) ​​of the first initial wiring layer of the at least one initial power wiring located in the first target area (m) and to etch the initial organic film layer.

18. The method according to claim 17, characterized in that Before forming the pixel definition layer, the orthographic projection of the second material layer (a2) of the first initial wiring layer located in the first target area (m) on the base substrate (101) is located within the orthographic projection of the third material layer (a3) ​​on the base substrate (101), and the first boundary (a11) of the first material layer (a1) of the first initial wiring layer located in the first target area (m) and the third boundary (a31) of the third material layer (a3) ​​are collinear; After forming the pixel definition layer, part of the material of the pixel definition layer is located in a retracted area, and the retracted area is an area where the first initial wiring layer has the first material layer (a1) and the third material layer (a3) ​​but does not have the second material layer (a2); After etching the third material layer (a3) ​​of the first initial wiring layer of the at least one initial power wiring located in the first target area (m) and etching the initial organic film layer using the etching process, part of the material of the pixel defining layer located in the retracted area is removed.

19. The method according to any one of claims 14 to 18, characterized in that: The method of etching the third material layer (a3) ​​of the first initial wiring layer of the at least one initial power wiring located in the first target area (m) and etching the initial organic film layer by using an etching process comprises: Coating photoresist on a side of the first initial wiring layer away from the substrate (101); Exposing the photoresist using a mask; Developing the photoresist with a developer to remove the exposed portion of the photoresist; Using an etching process to remove the third material layer (a3) ​​of the first initial wiring layer located in the first target area (m) and the portion of the initial organic film layer not protected by the photoresist; Remove the remaining photoresist.

20. The method according to claim 19, characterized in that The mask plate has a plurality of mask openings, and the orthographic projection of each mask opening on the base substrate (101) partially overlaps with the through-slot area (105a) and partially overlaps with the first target area (m) of the initial power supply wiring; The mask opening has a first mask boundary extending along a first direction (X), the first mask boundary is used to form a third boundary (a31) of the third material layer (a3) ​​after etching, and the orthographic projection of the first mask boundary on the substrate (101) is located within the orthographic projection of the first material layer (a1) on the substrate (101), the distance between the first mask boundary and the first boundary (a11) in the second direction (Y) is greater than 3 microns, and the second direction (Y) is perpendicular to the first direction (X).

21. The method according to claim 20, characterized in that The first mask boundary is also used to form a first groove boundary (105b1) of the groove region (105b) of the first organic film layer (105) after etching, and the first groove boundary (105b1) is close to the first wiring layer and extends along the first direction (X); The thickness of the first organic film layer (105) in the groove area (105b) is less than the thickness of other areas except the groove area (105b), and the groove area (105b) is used to cover the second target area (n) of the power line (104), and the second target area (n) and the first target area (m) are adjacent in the first direction (X).

22. The method according to claim 20 or 21, characterized in that The mask opening also has a second mask boundary extending along a second direction (Y); the through-groove region (105a) is located on one side of the second mask boundary; the second mask boundary is used to form a groove region (105b) of the first organic film layer (105); the groove region (105b) is away from the through-groove region (105a) and extends along the second direction (Y); the groove region (105b) also has a third groove boundary (105b3) adjacent to the through-groove region (105a) and extending along the second direction (Y); Wherein, the distance between the second groove boundary (105b2) and the third groove boundary (105b3) in the first direction (X) is greater than 3 micrometers.

23. The method according to any one of claims 14 to 22, characterized in that: Forming the power supply wiring (104) comprises: forming a first wiring layer on one side of the base substrate (101); Alternatively, forming the power wiring (104) comprises: sequentially forming a second wiring layer, a second organic film layer and the first wiring layer on one side of the base substrate (101), wherein the first wiring layer and the second wiring layer are connected via an opening in the second organic film layer; Alternatively, forming the power wiring (104) comprises: sequentially forming a third wiring layer, a third organic film layer, a second wiring layer, a second organic film layer and the first wiring layer on one side of the base substrate (101), the first wiring layer and the second wiring layer being connected via an opening in the second organic film layer, and the second wiring layer and the third wiring layer being connected via an opening in the third organic film layer; Wherein, the through-groove area (105a) is used to expose the first target area (m) of the first wiring layer.

24. A display device, characterized in that: The display device comprises a power supply component and a display panel (10) according to any one of claims 1 to 13; Wherein, the power supply component is used to supply power to the display panel (10).

Images