MEMS capacitive sensor structure based on SOI wafer and preparation method thereof
By adopting the structural design and process flow of SOI wafer-based in MEMS capacitive sensors, the surface roughness and cleanliness problems in the wafer bonding process are solved, and high sensitivity and low cost sensor production is achieved, which is suitable for batch applications.
Patent Information
- Application Number
- CN202410909040.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-08
- Publication Date
- 2025-01-03
AI Technical Summary
Existing MEMS capacitive sensors are sensitive to surface roughness and cleanliness in wafer bonding process, resulting in low yields and difficult to achieve efficient mass production.
Using a MEMS capacitive sensor structure based on SOI wafer, the capacitive cavity and the ring-shaped support are arranged in a rectangular array through the upper electrode layer, the diaphragm layer, the capacitive cavity layer and the lower electrode layer arranged from top to bottom. The wall, combined with MEMS diffusion and coating processes, forms a high-sensitivity sensor structure and simplifies the process flow to reduce costs.
It realizes scientific design, simple manufacturing, low cost, high integration and high sensitivity of sensor structures, and is suitable for mass production.
Smart Images
Figure CN119240594A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of MEMS sensors, and in particular relates to a capacitive transducer, specifically a SOI wafer-based MEMS capacitive sensor structure and a preparation method thereof. Background Art
[0002] Capacitive sensors based on MEMS technology have the characteristics of small size, high consistency, high-density integration, low cost, and easy mass production. Therefore, their application potential in various fields is highly recognized.
[0003] The manufacturing methods based on wafer bonding expansion include silicon local oxidation process, anodic bonding process, etc. Compared with the sacrificial release process, the diaphragm thickness and cavity height can be better controlled. However, the wafer bonding process is very sensitive to the surface roughness and cleanliness of the wafer, so it may have a lower yield.
[0004] Therefore, it is necessary to propose a new capacitive sensor structure and its manufacturing method to avoid the difficulties of traditional technology. Summary of the invention
[0005] The purpose of the present invention is to solve the problems existing in the prior art and the application potential of capacitive transducers based on MEMS technology in various fields, and to provide a MEMS capacitive sensor structure based on SOI wafer and a preparation method thereof.
[0006] The present invention is achieved through the following technical solutions: One object of the present invention is to provide a MEMS capacitive sensor structure based on SOI wafer, which includes an upper electrode layer, a diaphragm layer, a capacitor cavity layer, a substrate layer and a lower electrode layer arranged from top to bottom; wherein, a plurality of capacitor cavities arranged in a rectangular array are formed on the capacitor cavity layer, and an annular support wall is formed between adjacent capacitor cavities; a portion of the diaphragm layer located directly above each capacitor cavity forms a diaphragm body, and an annular release channel penetrating the diaphragm layer is opened around each diaphragm body; the upper electrode layer includes a plurality of upper electrode bodies, and the plurality of upper electrode bodies are disposed at the top center position of the respective corresponding diaphragm bodies, and the plurality of upper electrode bodies are interconnected by metal wires; the lower electrode layer includes a lower electrode body, and the lower electrode body is entirely covered on the bottom surface of the substrate layer.
[0007] As a preferred technical solution, welding points are arranged at the edges of the diaphragm layer, and a plurality of upper electrode bodies are interconnected and then connected to the welding points as a whole.
[0008] As a preferred technical solution, the capacitor cavity, the diaphragm body, and the upper electrode body are arranged in a 6×6 rectangular array.
[0009] As a preferred technical solution, the materials of the diaphragm layer and the substrate layer are silicon, the material of the annular support wall in the capacitor cavity layer is silicon dioxide, and the materials of the upper electrode body, metal wiring, solder joints and lower electrode body are chromium and gold.
[0010] As a preferred technical solution, the thickness of the upper electrode body, metal wiring, solder joints and lower electrode body is 330nm, the thickness of the diaphragm layer is 1.5um, the thickness of the capacitor cavity and the annular support wall in the capacitor cavity layer is 0.5um, and the thickness of the substrate layer is 300um.
[0011] Another object of the present invention is to provide a method for preparing the above-mentioned MEMS capacitive sensor structure based on SOI wafer, which comprises the following steps: 1) Select SOI wafer as the spare wafer. The SOI wafer is composed of device layer, oxide layer and handle layer from top to bottom. The upper electrode layer and solder joints are on the upper surface of the device layer. The device layer is the layer where the diaphragm layer is located. The oxide layer is the layer where the capacitor cavity layer is located. The handle layer is the substrate layer. The lower electrode layer is on the lower surface of the handle layer.
[0012] 2) Boron ion doping is performed on the device layer and handle layer respectively through MEMS diffusion process.
[0013] 3) Magnetron sputtering of metal chromium and gold is performed on the upper surface of the device layer and the lower surface of the handle layer respectively through a MEMS coating process; wherein the metal layer on the lower surface of the handle layer forms a lower electrode body.
[0014] 4) Coat a layer of photoresist on the device layer, use photolithography technology to transfer the mask pattern to the photoresist, use the photoresist pattern as a mask, and use wet etching technology to etch the unmasked area of the device layer, finally forming an upper electrode body and solder joints arranged in a rectangular array on the device layer.
[0015] 5) Coat a layer of photoresist on the device layer, use photolithography technology to transfer the mask pattern to the photoresist, use the photoresist pattern as a mask, and use RIE etching technology to etch the unmasked area of the device layer, and finally form a ring-shaped release channel around each upper electrode body on the device layer.
[0016] 6) The oxide layer is etched by HF dry etching technology through the annular release channel on the device layer, and finally a capacitor cavity is released at a position directly below each upper electrode body on the oxide layer, and the remaining part of the oxide layer forms an annular support wall; wherein, the portion of the device layer located on the top of each capacitor cavity forms a diaphragm body.
[0017] 8) The SOI wafer processed as above can be diced.
[0018] As a preferred technical solution, in step 1), a four-inch SOI wafer is used, the thickness of the device layer is 1.5um, the thickness of the oxide layer is 0.5um, and the thickness of the handle layer is 300um.
[0019] As a preferred technical solution, in step 6), after the capacitor cavity is formed, high-temperature annealing treatment of metal chromium and gold is performed.
[0020] Compared with the prior art, the present invention has the following beneficial effects: 1) The sensor structure of the present invention is scientifically designed, reasonably structured, simple to manufacture, and easy to use. The sensor structure is small in size, can be highly integrated, and has high sensitivity.
[0021] 2) The sensor structure manufacturing method of the present invention is simple, has few process steps, low cost, and can be mass-produced. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.
[0023] Figure 1 This is a top view of the MEMS capacitive sensor structure based on SOI wafer of the present invention (not packaged).
[0024] Figure 2 for Figure 1 AA section view in (unencapsulated).
[0025] Figure 3 The present invention is a flow chart of the manufacturing process of the capacitive transducer.
[0026] In the figure: a-upper electrode layer, b-diaphragm layer, c-capacitor cavity layer, d-substrate layer, e-lower electrode layer; 1-capacitor cavity, 2-annular support wall, 3-diaphragm, 4-annular release channel, 5-upper electrode, 6-soldering point, 7-lower electrode, 8-metal connection, 9-device layer, 10-oxide layer, 11-handle layer, 12-substrate. DETAILED DESCRIPTION
[0027] The following is a clear and complete description of the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the protection scope of the present invention.
[0028] In the description of the present invention, it should be understood that the terms "upper", "lower", etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance, quantity or position.
[0029] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the term "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances. Example 1
[0030] This embodiment provides a MEMS capacitive sensor structure based on SOI wafer, such as Figure 1 and Figure 2 As shown, it includes an upper electrode layer a, a diaphragm layer b, a capacitor cavity layer c, a substrate layer d and a lower electrode layer e arranged from top to bottom.
[0031] Among them, a plurality of capacitor cavities 1 arranged in a rectangular array are formed on the capacitor cavity layer c. The capacitor cavity 1 is a thin cylindrical structure, and an annular support wall 2 is formed between adjacent capacitor cavities 1.
[0032] The part of the diaphragm layer b located directly above each capacitor cavity 1 forms a diaphragm body 3, and an annular release channel 4 is opened around each diaphragm body 3 and penetrates the diaphragm layer b, and the annular release channel is connected to the capacitor cavity 1; the annular release channel 4 is composed of four evenly distributed arc grooves, and the four arc grooves form a circular ring, and the four arc grooves are respectively located at the 12 o'clock-3 o'clock position, the 3 o'clock-6 o'clock position, the 6 o'clock-9 o'clock position, and the 9 o'clock-12 o'clock position of the circular ring.
[0033] The upper electrode layer a includes several upper electrode bodies 5 and a welding point 6. The several upper electrode bodies 5 are arranged at the top center position of their respective corresponding diaphragm bodies 3, and the upper electrode bodies 5 are thin cylindrical structures; the welding point 6 is arranged at the edge of the diaphragm layer b, and the several upper electrode bodies 5 are interconnected by metal wires 8 and then connected to the welding point 6 as a whole.
[0034] The substrate layer d forms the substrate 12 of the sensor structure.
[0035] The lower electrode layer e includes a lower electrode body 7 , and the lower electrode body 7 is entirely covered and disposed on the bottom surface of the substrate layer d.
[0036] In the above-mentioned MEMS capacitive sensor structure based on SOI wafer, the capacitor cavity 1, the diaphragm body 3, and the upper electrode body 5 correspond to each other and are arranged in a 6×6 rectangular array; the material of the diaphragm layer b and the substrate layer d is silicon, the material of the annular support wall 2 in the capacitor cavity layer c is silicon dioxide, and the materials of the upper electrode body 5, the metal connection 8, the solder joint 6 and the lower electrode body 7 are chromium and gold; the thickness of the upper electrode body 5, the metal connection 8, the solder joint 6 and the lower electrode body 7 are all 330nm, the thickness of the diaphragm layer b is 1.5um, the thickness of the diaphragm body 3 is also 1.5um, the thickness of the capacitor cavity 1 and the annular support wall 2 in the capacitor cavity layer c are both 0.5um, and the thickness of the substrate layer d is 300um.
[0037] The SOI wafer-based MEMS capacitive sensor structure described in this embodiment has a small structure size, can be highly integrated, and has high sensitivity. Example 2
[0038] This embodiment provides a method for preparing the MEMS capacitive sensor structure based on the SOI wafer described in Embodiment 1, comprising the following steps: 1) Select SOI wafer as the backup wafer. The SOI wafer uses a four-inch wafer. The SOI wafer is composed of a device layer 9, an oxide layer 10, and a handle layer 11 from top to bottom. The thickness of the device layer 9 is 1.5um, the thickness of the oxide layer 10 is 0.5um, and the thickness of the handle layer 11 is 300um. Figure 3 As shown in A in the figure, the upper electrode layer a and the solder joint 6 are on the upper surface of the device layer 9, the device layer 9 is the layer where the diaphragm layer b is located, the oxide layer 10 is the layer where the capacitor cavity layer c is located, the handle layer 11 is the substrate layer d, and the lower electrode layer e is on the lower surface of the handle layer 11.
[0039] 2) Boron ion doping is performed on the device layer 9 and the handle layer 11 respectively through a MEMS diffusion process at a high temperature of 1000° C. for 10 minutes.
[0040] 3) The upper surface of the device layer 9 and the lower surface of the handle layer 11 are magnetron sputtered with metal chromium and gold respectively through the MEMS coating process. The thickness of the metal chromium and gold is 30nm and 300nm respectively. Figure 3 As shown in B in FIG. 1 , wherein the metal layer on the lower surface of the handle layer 11 forms the lower electrode body 7 .
[0041] 4) Coat a layer of photoresist on the device layer 9, transfer the mask pattern to the photoresist using photolithography technology, use the photoresist pattern as a mask, and use wet etching technology to etch the mask-free area of the device layer 9, and finally form an upper electrode body 5 and solder joints 6 arranged in a rectangular array on the device layer 9, as shown in FIG. Figure 3 As shown in C.
[0042] 5) Coat a layer of photoresist on the device layer 9, transfer the mask pattern to the photoresist using photolithography technology, use the photoresist pattern as a mask, and use RIE etching technology to etch the mask-free area of the device layer 9, and finally form a ring-shaped release channel around each upper electrode body 5 on the device layer 9, such as Figure 3 As shown in D.
[0043] 6) The oxide layer 10 is etched by HF dry etching technology through the annular release channel on the device layer 9, and finally the position directly below each upper electrode body 5 on the oxide layer 10 is released to form a capacitor cavity 1, and the remaining part of the oxide layer 10 forms an annular support wall 2, and the part of the device layer 9 located on the top of each capacitor cavity 1 forms a diaphragm body 3, as shown in FIG. Figure 3 As shown in E; high temperature annealing treatment is then performed. High temperature annealing can weaken the Schottky barrier between the silicon semiconductor and the metal chromium and gold in the upper electrode body 5 and the device layer 9 and the lower electrode body 7 and the handle layer 11, thereby improving the sensitivity of the sensor.
[0044] 8) The SOI wafer processed as above can be diced.
[0045] The preparation method described in this embodiment is simple to operate, has fewer process steps, is low in cost, and can be mass-produced.
[0046] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.
Claims
1. A MEMS capacitive sensor structure based on SOI wafer, characterized in that: It includes an upper electrode layer, a diaphragm layer, a capacitor cavity layer, a substrate layer and a lower electrode layer arranged from top to bottom; wherein, a plurality of capacitor cavities arranged in a rectangular array are formed on the capacitor cavity layer, and an annular support wall is formed between adjacent capacitor cavities; the portion of the diaphragm layer directly above each capacitor cavity forms a diaphragm body, and an annular release channel penetrating the diaphragm layer is opened around each diaphragm body; the upper electrode layer includes a plurality of upper electrode bodies, which are arranged at the top center position of their respective corresponding diaphragm bodies, and the plurality of upper electrode bodies are interconnected by metal wires; the lower electrode layer includes a lower electrode body, and the lower electrode body is entirely covered on the bottom surface of the substrate layer.
2. The MEMS capacitive sensor structure based on SOI wafer according to claim 1, characterized in that: A welding point is arranged at the edge of the diaphragm layer, and a plurality of upper electrode bodies are interconnected and then connected to the welding point as a whole.
3. The MEMS capacitive sensor structure based on SOI wafer according to claim 2, characterized in that: The capacitor cavity, diaphragm body and upper electrode body are arranged in a 6×6 rectangular array.
4. The MEMS capacitive sensor structure based on SOI wafer according to claim 3, characterized in that: The materials of the diaphragm layer and the substrate layer are silicon, the material of the annular supporting wall in the capacitor cavity layer is silicon dioxide, and the materials of the upper electrode body, metal wiring, welding point and lower electrode body are chromium and gold.
5. The MEMS capacitive sensor structure based on SOI wafer according to claim 4, characterized in that: The thickness of the upper electrode body, metal wiring, solder joints and lower electrode body is 330nm, the thickness of the diaphragm layer is 1.5um, the thickness of the capacitor cavity body and the annular support wall in the capacitor cavity layer is 0.5um, and the thickness of the substrate layer is 300um.
6. The method for preparing a MEMS capacitive sensor structure based on SOI wafer according to claim 5, characterized in that: The steps include: 1) Select SOI wafer as the spare wafer. The SOI wafer is composed of device layer, oxide layer and handle layer from top to bottom. The upper electrode layer and solder joints are on the upper surface of the device layer. The device layer is the layer where the diaphragm layer is located. The oxide layer is the layer where the capacitor cavity layer is located. The handle layer is the substrate layer. The lower electrode layer is on the lower surface of the handle layer. 2) Boron ion doping is performed on the device layer and the handle layer respectively through the MEMS diffusion process; 3) magnetron sputtering metal chromium and gold on the upper surface of the device layer and the lower surface of the handle layer respectively through a MEMS coating process; wherein the metal layer on the lower surface of the handle layer forms a lower electrode body; 4) Coat a layer of photoresist on the device layer, transfer the mask pattern to the photoresist using photolithography technology, use the photoresist pattern as a mask, and use wet etching technology to etch the unmasked area of the device layer, and finally form an upper electrode body and solder joints arranged in a rectangular array on the device layer; 5) Coat a layer of photoresist on the device layer, transfer the mask pattern to the photoresist using photolithography technology, use the photoresist pattern as a mask, and use RIE etching technology to etch the mask-free area of the device layer, and finally form a ring-shaped release channel around each upper electrode body on the device layer; 6) Etching the oxide layer by HF dry etching technology through the annular release channel on the device layer, and finally releasing the position directly below each upper electrode body on the oxide layer to form a capacitor cavity, and the remaining part of the oxide layer forms an annular support wall; wherein, the part of the device layer located on the top of each capacitor cavity forms a diaphragm body; 8) The SOI wafer processed as above can be diced.
7. The method for preparing a MEMS capacitive sensor structure based on SOI wafer according to claim 6, characterized in that: In step 1), a four-inch SOI wafer is used, the thickness of the device layer is 1.5um, the thickness of the oxide layer is 0.5um, and the thickness of the handle layer is 300um.
8. The method for preparing a MEMS capacitive sensor structure based on SOI wafer according to claim 6, characterized in that: In step 6), after the capacitor cavity is formed, high temperature annealing treatment of metal chromium and gold is performed.