Instruction-driven coprocessor architecture design method for computing platform in high-performance magnetic memory

Abstract

The invention discloses an instruction-driven coprocessor architecture design method for an in-memory computing platform of a high-performance magnetic memory. The instruction-driven coprocessor architecture design method comprises the following steps of: switching a magnetic memory into a normal mode or an in-memory computing mode by writing a corresponding operation code into a state register OP; the normal mode is used for the read-write function of a normal memory, and the in-memory calculation mode provides the function that the magnetic memory serves as a calculation unit; when the magnetic memory is used as a computing unit, the operation of in-memory computing consists of two memory access instructions, namely, an in-memory computing activation instruction and an in-memory computing address transmission instruction; the in-memory calculation activation instruction is used for activating an in-memory mode of the memory, and the in-memory calculation address transmission instruction is used for providing necessary control signals for in-memory calculation. On the premise that a memory protocol and an instruction set architecture are not changed, memory access and calculation instructions can be distinguished through the memory circuit with the changeable state, and the high-reliability, low-power-consumption and high-parallelism in-memory calculation architecture based on the magnetic memory is achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of coprocessor computing architecture design, and in particular to an instruction-driven coprocessor architecture design method for a high-performance magnetic memory in-memory computing platform. Background Art

[0002] In big data applications such as artificial intelligence, large language models, and the Internet of Things, the traditional von Neumann architecture exhibits weaknesses in computing throughput under frequent data transfers due to the physical separation of data processing and storage. Furthermore, increases in processor frequency have highlighted the speed mismatch between memory and processors. While the presence of caches in modern computing architectures can address this issue to some extent, for some applications with low cache hit rates, it remains a bottleneck limiting further throughput improvements in modern computing architectures.

[0003] Furthermore, the multi-core, multi-threaded nature of modern processors often leads to cache congestion. Once these issues occur, memory bottlenecks become increasingly prominent. To address this issue, in-memory computing has recently emerged as a viable solution. Despite its significant performance advantages as an emerging computing paradigm, in-memory computing currently lacks commercially available memory chips that incorporate it due to two factors. First, most designers prioritize "accelerators" over "memory," focusing solely on the parallelism and throughput of in-memory computing while ignoring the inherent role of memory, rendering in-memory computing meaningless.

[0004] Currently, there are two promising in-memory computing architectures: near-memory computing and in-memory array computing. First, near-memory computing places arithmetic units near memory. Thanks to mature three-dimensional stacking technology, near-memory computing further expands computing throughput in the vertical dimension. Furthermore, due to the independence of the arithmetic units, near-memory computing requires little modification to the array structure and is compatible with DDR protocols.

[0005] Since near-memory computing typically relies on compute cores within memory, these cores themselves contain decoding modules that receive instructions and perform tasks such as instruction fetch, decoding, and execution. A common approach is to implement in-memory computing operations by adding a compute engine next to the DRAM chip. This approach then automatically determines and distinguishes which instructions are executed by the processor and which are issued to the in-memory compute engine by monitoring cache hits at the last level. This approach seamlessly integrates with existing programming models and system mechanisms. However, it requires modifying the compute core's instruction set to accommodate its in-memory computing instruction set (ISA). Furthermore, while this in-memory computing approach primarily increases computing bandwidth by increasing the number of compute cores in memory, its maximum bandwidth is still constrained by the number of cores and the memory area.

[0006] The concept of in-memory array computing involves placing computations in memory, performing arithmetic and logical operations through bitwise operations across the memory array. This memory-centric computing approach completely eliminates the overhead of data movement. Furthermore, by activating all columns of a memory row in parallel, it achieves cell-level parallelism, maximizing computational throughput.

[0007] The implementation of in-memory array computing does not require a dedicated logic layer or logic processing elements and has very low overhead. This approach can also fully utilize the high internal bandwidth available in the cell array. In addition, in-memory array computing often uses non-volatile devices such as magnetic random access memory (MRAM), resistive random access memory, and ferroelectric random access memory in non-volatile storage technologies to meet low energy requirements. Among them, MRAM is particularly popular due to its superior non-volatility, near-zero standby power, and fast switching speed.

[0008] Taking the AND operation as an example, the steps for implementing an in-memory array computational logic operation in MRAM are as follows. The overall array structure consists of a 2-transistor-1-SOT (2T1SOT) cell array (memory array), a read / write driver (RD / WD) circuit (read / write circuit), a sense amplifier (SA), a decoder circuit (decoding circuit), and an ICOM (peripheral circuit). The steps for implementing an AND logic operation in MRAM are as follows: When performing an AND operation, B3 is initialized, while WWL1 and BLS3 are simultaneously turned on. Second, A3 is read using the sense amplifier (SA), while RWL0 and BLS3 are simultaneously turned on. Third, RWL1, WWL0, and SLS3 are turned on, and the delay A3 read in step 2 is passed to the function selection module (FSM). If A3 is logic '1', a TRS operation (exclusive OR) is performed, changing the state of MTJ A3 based on the state of MTJ B3. Otherwise, no operation is performed. In addition, based on the above logical operations, Radix-4booth and Wallcace tree algorithms can also be used to implement multi-bit multiplication and addition.

[0009] Currently, architectures for near-memory computing and implementations of processor interfaces have been proposed. For example, Onur Mutlu et al. proposed a new in-memory computing architecture that automatically determines whether to execute in-memory computing operations in memory or on the processor based on the location of the data, without changing the existing sequential programming model. Samsung has also proposed a practical and innovative in-memory computing architecture that can work seamlessly with unmodified commercial processors as a direct replacement for standard DRAM.

[0010] However, as mentioned above, in-memory array computing is implemented by the memory array, requiring numerous control signals and lacking a direct instruction set. This makes it incompatible with modern memory architectures. Unlike near-memory computing, which only requires sending instructions to the compute core, in-memory array computing requires the memory array itself to receive instructions. Therefore, how to send commands to memory to control computing operations becomes a critical issue. Summary of the Invention

[0011] The purpose of the present invention is to provide an instruction-driven coprocessor architecture design method for a high-performance magnetic memory in-memory computing platform. In order to utilize the computing characteristics and data arrangement rules of the magnetic memory circuit, normal memory access instructions are used to drive the in-memory computing circuit. Without changing the memory protocol and instruction set architecture, a memory circuit with changeable state is used to distinguish between memory access and computing instructions, thereby realizing a high-reliability, low-power, and highly parallel in-memory computing architecture based on magnetic memory.

[0012] In order to achieve the above technical objectives, the technical solution adopted by the present invention is:

[0013] A method for designing an instruction-driven coprocessor architecture for a high-performance magnetic memory in-memory computing platform, the method comprising the following steps:

[0014] A status register OP is set in the memory, and the status register OP is mapped to a reserved memory space;

[0015] By writing the corresponding operation code to the status register OP, the magnetic memory is switched to normal mode or in-memory calculation mode; wherein the normal mode is used for normal memory reading and writing functions, and the in-memory calculation mode provides the magnetic memory with the function of a calculation unit;

[0016] When the magnetic memory is used as a computing unit, the in-memory computing operation consists of two memory access instructions, the in-memory computing activation instruction and the in-memory computing address transfer instruction; among them, the in-memory computing activation instruction is used to activate the in-memory mode of the memory, and the in-memory computing address transfer instruction is used to provide the necessary control signals for the in-memory computing.

[0017] Furthermore, the memory calculation activation instruction and the memory calculation address transfer instruction both comply with the format of the storage instruction, the address line of the memory calculation activation instruction represents the position of the status register, and the data line represents the state of the required conversion, so that the magnetic memory performs the corresponding type of memory calculation operation.

[0018] Furthermore, the in-memory computing operations include addition, multiplication, AND operation, and OR operation, and the granularity of each operation is the size of a memory page.

[0019] Furthermore, in the ELF file mapping strategy, when any calculation operation is implemented using in-memory calculation, the corresponding program operation is marked, and then an assembly file for the target platform is generated using a compiler. The generated assembly file is then modified at the marked position to replace the corresponding assembly instruction with the in-memory calculation instruction; the data used for the in-memory calculation is provided as an additional data segment;

[0020] The modified assembly file is assembled into an executable file through an assembler, and the data segment, code segment and static data segment are mapped to different block areas respectively, and calculation operations are started. During the execution of the calculation operation, the in-memory calculation in the magnetic storage is only performed in the mapped block area, while the reading and writing operations in other block areas are not affected.

[0021] Furthermore, when there are multiple data-independent storage and calculation operations and multiple free block areas, the storage and calculation operations are mapped to multiple free block areas through relative addresses in the mapping stage and executed in parallel; when there are multiple data-independent storage and calculation operations and there is only one free block area, all storage and calculation operations are mapped to the free block area and executed serially.

[0022] Furthermore, in normal mode, the address signal is transmitted to the address register, which is used to store the memory address to be accessed; the address signal stored in the address register is decoded by the column decoder and the bank decoder to activate the corresponding column and block area; when the column and block area are activated, the data is transmitted to the sensitive amplifier in the corresponding block area and column through the data line, and the data signal is amplified and stabilized by the sensitive amplifier; the address signal is then decoded by the row decoder to determine the memory row to be accessed, and the data amplified by the sensitive amplifier is written into the memory array, completing the data write operation and storing the data in the memory.

[0023] Furthermore, the design method further comprises the following steps:

[0024] When the coprocessor includes a cache, a buffer is set up next to the cache to store the address of the memory status register and the address of the in-memory calculation operation;

[0025] In the in-memory computing mode, before accessing the cache, it is first determined whether the address to be accessed is the address stored in the buffer. If so, it is sent directly to the memory bypassing the cache. Otherwise, a search operation is performed in the cache.

[0026] Furthermore, the design method further comprises the following steps:

[0027] Two address registers, a state register OP and an in-memory computing state machine are introduced into the MRAM memory;

[0028] When switching to in-memory calculation mode through the status register OP, the data line and address line signals of the next instruction are stored in the two address registers, and the transmission of the two operation addresses is completed through the next storage instruction; by controlling the two address registers and the peripheral SA circuit, the operation in the MRAM memory is controlled.

[0029] Furthermore, the process of controlling the operation in the MRAM memory includes the following steps:

[0030] Send the assembly instruction store 0(x0),0, write 0 to the address 0x0, the address 0x0 represents the location of the status register OP, and 0 represents the operation code of the corresponding operation. When the status register OP receives the operation code, the entire memory jumps to the state of calculating the corresponding operation;

[0031] Send the assembly instruction store addr1, addr2. The addr1 and addr2 in the instruction represent the rows that need to be calculated. After addr1 and addr2 are received by the memory and saved to the address register, different calculation states are jumped according to the two addresses, and corresponding logical operations are performed on the data of the two addresses.

[0032] Compared with the prior art, the present invention has the following beneficial effects:

[0033] First, the present invention's instruction-driven coprocessor architecture design method for a high-performance magnetic memory in-memory computing platform, based on the computational characteristics and data arrangement patterns of MRAM in-memory array computing, implements a non-highly parallel, low-power, and highly reliable in-memory computing architecture design scheme, and proposes an architecture-level delay optimization strategy. The present invention can use normal memory access instructions to drive the MRAM in-memory computing circuit. Without changing the memory protocol and instruction set architecture, the present invention distinguishes between memory access and computing instructions through a state-modifiable memory architecture, thereby implementing a highly reliable, low-power, and highly parallel in-memory computing architecture based on MRAM.

[0034] Second, the present invention's instruction-driven coprocessor architecture design method for a high-performance magnetic memory in-memory computing platform utilizes common memory access instructions to dispatch in-memory computing operations without requiring additional in-memory computing control instructions. This method can simultaneously support standard MRAM memory access and MRAM in-memory computing. For common convolution applications, the proposed design can significantly reduce the number of application instructions. Furthermore, the present invention proposes a status register to replace the mode register in conventional main memory to switch memory states. This avoids the significant overhead caused by context switching. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1A schematic diagram of an instruction-driven coprocessor architecture for a high-performance magnetic memory in-memory computing platform according to the present invention;

[0036] Figure 2 This is a schematic diagram of the memory mapping method;

[0037] Figure 3 Schematic diagram of different memory modes; (a) represents normal memory access mode, (b) represents in-memory computing mode;

[0038] Figure 4 A diagram showing how to set up the instruction cache for storage. DETAILED DESCRIPTION

[0039] The embodiments of the present invention are described in further detail below with reference to the accompanying drawings.

[0040] The present invention discloses an instruction-driven coprocessor architecture design method for a high-performance magnetic memory in-memory computing platform, the design method comprising the following steps:

[0041] A status register OP is set in the memory, and the status register OP is mapped to a reserved memory space;

[0042] By writing the corresponding operation code to the status register OP, the magnetic memory is switched to normal mode or in-memory calculation mode; wherein the normal mode is used for normal memory reading and writing functions, and the in-memory calculation mode provides the magnetic memory with the function of a calculation unit;

[0043] When the magnetic memory is used as a computing unit, the in-memory computing operation consists of two memory access instructions, the in-memory computing activation instruction and the in-memory computing address transfer instruction; among them, the in-memory computing activation instruction is used to activate the in-memory mode of the memory, and the in-memory computing address transfer instruction is used to provide the necessary control signals for the in-memory computing.

[0044] Based on the aforementioned design method, the present invention proposes a novel in-memory computing architecture. In this architecture, an in-memory computing operation instruction consists of two common memory access instructions. The first is a status register activation instruction, which activates the memory's in-memory mode. The second is an in-memory computing address transfer instruction, which provides the necessary control signals for the in-memory computing. Both the in-memory computing activation instruction and the in-memory computing address transfer instruction follow the format of conventional storage instructions. The data in the address line of the in-memory computing activation instruction represents the position of the status register, and the data transmitted on the data line represents the desired state to be converted, that is, the type of in-memory computing operation to be performed. The address line and data line of the in-memory computing address transfer instruction respectively transmit the two addresses required for the in-memory computing operation. At the architectural level, to support the implementation of this instruction scheme, the present invention establishes two modes for the MRAM memory: normal mode and in-memory computing mode. Normal mode ensures normal memory read and write functions, while in-memory computing mode enables the MRAM to function as a computing unit. To ensure that the MRAM can switch between these two modes, the present invention provides a status register OP in the memory, which is mapped to a reserved memory space. When changing the memory mode, you can switch between different operation types by writing data to the memory address. The operations that can be performed include addition, multiplication, AND, and OR, where the granularity of each operation is the size of a memory page.

[0045] The overall architecture is as follows Figure 1 As shown, the present invention consists of three key parts: 1. Machine-level instruction design and bank-based ELF file mapping strategy. 2. In-memory architecture design that supports in-memory instruction scheme. 3. Cache setting that supports in-memory instruction scheme.

[0046] Regarding instruction design, the present invention adopts a solution that does not add new instructions for in-memory computations, but instead uses existing memory access instructions to control the memory chip. The main processor can control the execution of each in-memory computation instruction one by one through storage instructions. These instructions are converted into MRAM-in-memory array computation commands and stored in the MRAM memory.

[0047] In terms of instruction format, an in-memory computation operation consists of two memory access instructions. The first is the status register activation instruction, which activates the in-memory mode of the memory. The second is the in-memory computation address transfer instruction, which provides the necessary control signals for the in-memory computation. Both the in-memory computation activation instruction and the in-memory computation address transfer instruction follow the format of the storage instruction. The address lines of the in-memory computation activation instruction represent the position of the status register, and the data lines represent the state to be converted, that is, the type of in-memory computation operation to be performed.

[0048] In the ELF file mapping strategy, taking the in-memory AND operation as an example, when implementing an AND operation using in-memory computation, the corresponding program AND operation must first be marked. The compiler then generates an assembly file suitable for the target platform. The generated assembly file is then modified at the marked position, replacing the corresponding assembly instructions with in-memory computation instructions. Furthermore, the data used for the in-memory computation is provided as an additional data segment. Furthermore, since MRAM's in-memory computation operations do not interfere with each other between banks, when multiple data-independent computation operations exist, data and relative addresses can be mapped to multiple banks during the mapping phase. This is primarily accomplished by the operating system when allocating addresses to the ELF file. If only one bank is free, all operations are mapped to that bank and executed serially. If there are multiple banks and the computation operations can be split across multiple banks, the computations can be mapped to multiple free banks using relative addresses.

[0049] Next, the modified assembly file is assembled into an executable file through the modified assembler. In this process, the data segment, code segment and static data segment will be mapped to different banks (a block area in memory). Figure 2 As shown in the figure, once the executable file is ready and the data, code, and static data segments are mapped to different banks along with the in-memory computation data, execution can begin. During execution, the in-memory computation instructions are executed to perform vector addition calculations. The in-memory computation is performed in the designated bank, while read and write operations in other banks are not affected. This approach leverages the power of in-memory computation to perform computations such as vector addition directly in memory, improving computational efficiency and system performance.

[0050] Regarding the overall memory architecture design, in order to support the use of standard commands to switch between normal mode and in-memory computing mode, the present invention considers using the mode register commands reserved in the instruction set. However, the mode register is usually associated with privileged instructions, and when performing in-memory computing operations, switching between normal mode and in-memory computing mode will be frequent. Calling privileged instructions requires switching from user mode to kernel mode to execute privileged operations. The overhead of frequent context switching can lead to a significant performance degradation.

[0051] Therefore, the present invention establishes two modes within the overall MRAM memory architecture: normal mode and in-memory computing mode. Normal mode ensures normal memory read and write functions, while in-memory computing mode enables the MRAM memory array to function as a computing unit. To ensure the MRAM memory array can switch between these two modes, a status register (OP) is provided, which is mapped to a reserved memory space. When the memory mode needs to be changed, data can be written to this memory address to switch between different memory modes.

[0052] Normal mode:

[0053] The MRAM storage array in this invention uses the NVDIMM standard, which allows new NVMs, including MRAM and ReRAM, to be integrated into the DDR protocol. Under this standard, the front-end processor interface is compatible with DRAM, making it easy to support any new processor.

[0054] like Figure 3 As shown in Figure .a, the process of a write operation in normal memory mode is as follows: First, the address signal is transmitted to the address register, which is used to store the memory address to be accessed. Next, the address signal is decoded by the column decoder and the bank decoder to activate the corresponding column and bank. Once the column and bank are activated, the data is transmitted to the sensitive amplifiers in the corresponding bank and column through the data line. The function of these sensitive amplifiers is to amplify and stabilize the data signal to ensure accurate reading and writing of data. Finally, the row decoder decodes the address signal to determine the memory row to be accessed. Through the decoding process of the row decoder, the memory system can accurately select the target memory row.

[0055] Once the target memory row is determined, the data in the sense amplifier is written to the memory array, completing the data write operation. Thus, the data is successfully stored in the memory. Throughout this process, various components (such as the address register, column decoder, bank decoder, sense amplifier, and row decoder) work together to ensure that the required memory address is correctly accessed and that the data is efficiently written to the memory. This coordinated collaboration ensures the efficient access and storage capabilities of the memory system.

[0056] In-memory computing mode:

[0057] The present invention introduces two address registers, an operation register (OP register) and an in-memory computing state machine into the MRAM memory. The OP register is mapped to a reserved memory address and is used to switch between normal mode and in-memory computing mode. By writing the corresponding operation code to the OP register, different computing states of the in-memory computing state machine can be triggered. At the same time, the data line and address line signals of the next instruction are also stored in the two address registers (such as Figure 3 By controlling these two address registers and the peripheral SA circuit, the operation within the memory can be controlled.

[0058] When calculating an in-memory AND operation, the first step is to send the assembly instruction "store 0(x0),0." This means writing 0 to address 0x0, where 0x0 represents the location of the OP register. 0 represents the opcode for the addition operation. When the OP register receives this 0 signal, the entire memory jumps to a calculation and operation state. The second step is to send the assembly instruction "store addr1,addr2." Here, addr1 and addr2 in the instruction represent the rows to be calculated. As mentioned earlier, the granularity of in-memory calculations in this MRAM is one memory row. All data on two memory rows is calculated in parallel, which facilitates increased parallelism. After addr1 and addr2 are received by the memory and saved to the address register, the in-memory calculation state machine jumps to different calculation states based on these two addresses.

[0059] Since the in-memory computing operations of this MRAM are composed of basic read, write and XOR operations, it is only necessary to jump these three operations according to the two addresses. Taking the calculation and operation as an example, an in-memory calculation and operation consists of three steps. The first step is to read addr1, the second step is to write addr2 (essentially to invert the data at address 2), and the third step is to perform an XOR operation on addr1 and addr2, that is, the two data are logically XORed. In this way, a logical AND operation can be completed. Therefore, the in-memory computing state machine in the MRAM memory only needs to jump these three states according to the specified time to realize an in-memory AND operation.

[0060] In-memory addition and multiplication are implemented using the aforementioned logical operations and shift operations, pieced together according to the BK algorithm. Aside from the increased number of steps, there are no other differences. For example, in-memory addition is still implemented by sending two assembly instructions: "store 0(x0),3" and "store addr1,addr2." The in-memory state machine will jump to the addition state based on the Opcode being 3. The first step in the addition operation is the "encoder shift," which involves reading operand 2, shifting, and writing operand 2. The second step is the "booth encoder," which involves three exclusive-or operations and a read operation. The third step is the "decoder shift," which requires only a single read and write of operand 2.

[0061] Regarding the parallelism of in-memory computation, since the in-memory computation is performed only in one bank, read and write operations to other banks are not affected. However, within the same bank, read and write operations must wait for the completion of the in-memory computation.

[0062] In addition, when the system includes a cache, the read and write instructions sent by the processor to the memory will always pass through the cache. When the accessed address exists in the cache, it will be returned directly to the processor. When the accessed address does not exist in the cache, it will search the lower level cache until the corresponding address does not exist in the last level cache, and then the instruction will be sent to the memory array. For in-memory computing instructions, we do not want this to happen, that is, the in-memory computing instructions are processed as storage instructions through the cache. So regardless of whether it hits or not, we hope that the in-memory computing instructions will reach the memory array directly to control the implementation of in-memory computing. Therefore, if Figure 4 As shown in the figure, we set up a buffer next to the cache to store the address of the memory status register and the addresses that need to be calculated in memory. Before accessing the cache, we first check whether the address to be accessed is in these buffers. If so, the address is sent directly to the memory without performing a cache lookup.

[0063] The design of this invention enables in-memory computing capabilities for MRAM memory. Flexible control of in-memory operations is achieved by introducing address registers, operation registers, and an in-memory computing state machine. Furthermore, this design enables in-memory computing for a specific bank while ensuring normal read and write access to other banks.

[0064] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code. The scheme in the embodiment of the present application can be implemented in various computer languages, for example, object-oriented programming language Java and literal translation scripting language JavaScript, etc.

[0065] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the steps in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0066] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0067] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions for executing the steps in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0068] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present application.

[0069] Obviously, those skilled in the art may make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalents, this application is intended to include these modifications and variations.

Claims

1. A method for designing an instruction-driven coprocessor architecture for a high-performance magnetic storage in-memory computing platform, characterized in that: The design method comprises the following steps: A status register OP is set in the memory, and the status register OP is mapped to a reserved memory space; By writing the corresponding operation code to the status register OP, the magnetic memory is switched to the normal mode or the in-memory calculation mode; wherein the normal mode is used for the normal reading and writing functions of the memory, and the in-memory calculation mode provides the function of the magnetic memory as a calculation unit; When the magnetic memory is used as a computing unit, the in-memory computing operation is composed of two memory access instructions, namely the in-memory computing activation instruction and the in-memory computing address transfer instruction; among which, the in-memory computing activation instruction is used to activate the in-memory mode of the memory, and the in-memory computing address transfer instruction is used to provide necessary control signals for the in-memory computing.

2. The instruction-driven coprocessor architecture design method for a high-performance magnetic storage in-memory computing platform according to claim 1, characterized in that: The memory calculation activation instruction and the memory calculation address transfer instruction both comply with the format of the storage instruction. The address line of the memory calculation activation instruction represents the position of the status register, and the data line represents the state of the required conversion, so that the magnetic storage device performs the corresponding type of memory calculation operation.

3. The method for designing an instruction-driven coprocessor architecture for a high-performance magnetic storage in-memory computing platform according to claim 2, characterized in that: The in-memory computing operations include addition, multiplication, AND operation and OR operation, and the granularity of each operation is the size of a memory page.

4. The method for designing an instruction-driven coprocessor architecture for a high-performance magnetic storage in-memory computing platform according to claim 1, characterized in that: In the ELF file mapping strategy, when using in-memory computing to implement any computing operation, after marking the corresponding program operation, use the compiler to generate an assembly file for the target platform, and then modify the generated assembly file mark to replace the corresponding assembly instruction with the in-memory computing instruction; Data used for in-memory calculations is provided as an additional data segment; The modified assembly file is assembled into an executable file through the assembler, and the data segment, code segment and static data segment are mapped to different block areas respectively, and the calculation operation begins; During the execution of computing operations, in-memory computing in the magnetic storage is performed only in the mapped block area, while the read and write operations of other block areas are not affected.

5. The method for designing an instruction-driven coprocessor architecture for a high-performance magnetic storage in-memory computing platform according to claim 4, characterized in that: When there are multiple data-independent storage and computing operations and multiple free block areas, the storage and computing operations are mapped to multiple free block areas through relative addresses in the mapping stage and executed in parallel; when there are multiple data-independent storage and computing operations and there is only one free block area, all storage and computing operations are mapped to the free block area and executed serially.

6. The method for designing an instruction-driven coprocessor architecture for a high-performance magnetic storage in-memory computing platform according to claim 1, characterized in that: In normal mode, the address signal is transmitted to the address register, which is used to store the memory address to be accessed; the address signal stored in the address register is decoded by the column decoder and the bank decoder to activate the corresponding column and block area; when the column and block area are activated, the data is transmitted to the sensitive amplifier in the corresponding block area and column through the data line, and the data signal is amplified and stabilized by the sensitive amplifier; the address signal is then decoded by the row decoder to determine the memory row to be accessed, and the data amplified by the sensitive amplifier is written into the memory array to complete the data write operation and store the data in the memory.

7. The method for designing an instruction-driven coprocessor architecture for a high-performance magnetic storage in-memory computing platform according to claim 1, characterized in that: The design method further comprises the following steps: When the coprocessor contains a cache, a buffer is set next to the cache to store the address of the memory status register and the address of the in-memory calculation operation; In the in-memory computing mode, before accessing the cache, it is first determined whether the address to be accessed is the address stored in the buffer. If so, it bypasses the cache and is sent directly to the memory. Otherwise, a search operation is performed in the cache.

8. The method for designing an instruction-driven coprocessor architecture for a high-performance magnetic storage in-memory computing platform according to claim 1, characterized in that: The design method further comprises the following steps: Two address registers, a state register OP and an in-memory computing state machine are introduced into the MRAM memory; When the in-memory computing mode is switched through the status register OP, the data line and address line signals of the next instruction are stored in the two address registers, and the transmission of the two operation addresses is completed through the next storage instruction; the operation in the MRAM memory is controlled by controlling the two address registers and the peripheral SA circuit.

9. The method for designing an instruction-driven coprocessor architecture for a high-performance magnetic storage in-memory computing platform according to claim 8, characterized in that: The process of controlling operations within the MRAM memory includes the following steps: Send the assembly instruction store 0(x0),0, write 0 to the address 0x0, the address 0x0 represents the location of the status register OP, and 0 represents the operation code of the corresponding operation. When the status register OP receives the operation code, the entire memory jumps to the state of calculating the corresponding operation; Send the assembly instruction store addr1, addr2. The addr1 and addr2 in the instruction represent the rows that need to be calculated. When addr1 and addr2 are received by the memory and saved in the address register, different calculation states are jumped according to the two addresses, and corresponding logical operations are performed on the data of the two addresses.

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