Semiconductor structure and forming method thereof

Abstract

The invention provides a semiconductor structure and a forming method thereof. The forming method of the semiconductor structure comprises the following steps of forming a substrate and a plurality of active columns located on the substrate, wherein an isolation groove for exposing the substrate is formed between every two adjacent active columns; forming an isolation layer filling the isolation groove, wherein the isolation layer has a solid structure and the top surface of the isolation layer is flat; forming a signal line groove exposing part of the active column; a conductive line is formed in the signal line trench. According to the invention, the problem of electric leakage between adjacent memory cells is reduced, and the electrical performance of the semiconductor structure is improved.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuit manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor device commonly used in electronic devices such as computers. It consists of multiple storage cells, and multiple word lines and bit lines electrically connected to the multiple storage cells. Each storage cell usually includes a switch element and a storage element electrically connected to the switch element. By controlling the word line voltage, the switch element can be turned on and off, so that the data information stored in the storage element can be read through the bit line, or the data information can be written into the storage element.

[0003] In the process of forming semiconductor structures such as DRAM, transistors are often used as switching elements. After forming an active array composed of multiple active pillars, it is necessary to form an isolation structure between adjacent active pillars. However, due to the high aspect ratio of the active pillars, the aspect ratio of the spacing grooves between adjacent active pillars is also high. In the process of filling the isolation material in the spacing groove with a high aspect ratio to form an isolation structure, gaps are easily generated. The conductive material deposited subsequently may enter the gap, which may easily cause leakage problems between adjacent storage cells, resulting in a reduction in the performance of the semiconductor structure.

[0004] Therefore, how to reduce the leakage problem between adjacent memory cells and reduce the mutual influence between adjacent memory cells, thereby improving the performance of the semiconductor structure, is a technical problem that needs to be solved urgently. Summary of the invention

[0005] Some embodiments of the present disclosure provide a semiconductor structure and a method for forming the same, which are used to reduce leakage problems between adjacent memory cells and reduce mutual influence between adjacent memory cells, thereby improving the performance of the semiconductor structure.

[0006] According to some embodiments, the present disclosure provides a method for forming a semiconductor structure, comprising the following steps:

[0007] forming a substrate and a plurality of active pillars on the substrate, wherein adjacent active pillars have isolation trenches between them for exposing the substrate;

[0008] forming an isolation layer that fills the isolation trench, wherein the isolation layer has a solid structure and a top surface of the isolation layer is flat;

[0009] forming a signal line groove exposing a portion of the active pillar;

[0010] A conductive line is formed in the signal line groove.

[0011] In some embodiments, the specific steps of forming a substrate and a plurality of active pillars on the substrate include:

[0012] providing an initial substrate;

[0013] The initial substrate is etched to form the isolation trenches including a plurality of first trenches and a plurality of second trenches, wherein the first trenches and the second trenches are alternately arranged, the width of the first trenches is greater than the width of the second trenches, and the plurality of first trenches and the plurality of second trenches separate the initial substrate into a plurality of active pillars arranged at intervals, and the remaining initial substrate below the active pillars serves as the substrate.

[0014] In some embodiments, the aspect ratio of the first trench is less than 15:1.

[0015] In some embodiments, the aspect ratio of the first trench is (10-11):1.

[0016] In some embodiments, the specific steps of forming the isolation layer that fills the isolation trench include:

[0017] forming a first isolation layer covering the inner wall of the first trench and filling the second trench;

[0018] A second isolation layer is formed to fill the remaining first trench, wherein the second isolation layer has a solid structure and a top surface of the second isolation layer is flat, and the first isolation layer and the second isolation layer together serve as the isolation layer.

[0019] In some embodiments, before forming a signal line trench of the active pillar in the isolation layer to expose a portion thereof, the method further includes the following steps:

[0020] Etching back a portion of the isolation layer to form a third trench exposing a portion of the active pillar;

[0021] At least increasing the width of the exposed active pillar;

[0022] A filling layer is formed to completely fill the third trench.

[0023] In some embodiments, the specific steps of forming the third trench of the exposed portion of the active pillar include:

[0024] Part of the first isolation layer is etched back to form a third trench exposing a portion of the active pillar.

[0025] In some embodiments, the specific steps of at least increasing the width of the exposed active pillars include:

[0026] The exposed active pillars are processed by an epitaxial process to form epitaxial layers covering surfaces of the exposed active pillars.

[0027] In some embodiments, the first trench and the second trench are arranged at intervals along a first direction, and a width of the epitaxial layer at least along the first direction is smaller than a width of the third trench along the first direction.

[0028] In some embodiments, the projection of the active pillar on the top surface of the substrate extends along the second direction, and the active pillar includes a channel region and a source / drain region distributed outside the channel region along the second direction; the specific steps of forming a signal line trench exposing a portion of the active pillar include:

[0029] The isolation layer and the channel region in the active pillar are etched to reduce the height of the channel region in the active pillar and form the signal line trench that at least exposes the remaining channel region in the active pillar.

[0030] In some embodiments, the specific steps of forming a conductive line in the signal line trench include:

[0031] forming a gate dielectric layer covering the remaining channel region in the signal line trench;

[0032] forming a conductive material layer covering the gate dielectric layer;

[0033] A signal line cover layer is formed to cover the conductive material layer, and the conductive material layer and the signal line cover layer together constitute the conductive line.

[0034] According to some other embodiments, the present disclosure further provides a semiconductor structure, including:

[0035] substrate;

[0036] A plurality of active structures are located on the substrate, and the plurality of active structures are arranged at intervals, and the plurality of active structures are arranged at intervals at least along a first direction, and the active structure comprises a first portion and a second portion located above the first portion, and the width of the second portion at least along the first direction is greater than the width of the second portion along the first direction;

[0037] An isolation structure, located on the substrate and distributed between adjacent active structures, wherein the isolation structure is a solid structure and a top surface of the isolation structure is flat;

[0038] The conductive line is located on the substrate and covers the active structure.

[0039] In some embodiments, the active structure comprises:

[0040] an active pillar, located on the substrate and extending in a direction perpendicular to a top surface of the substrate;

[0041] An epitaxial layer covers an upper portion of the active pillar, the epitaxial layer and the active pillar covered by the epitaxial layer serve as the second portion, and the active pillar located below the second portion serves as the first portion.

[0042] In some embodiments, the isolation structure comprises:

[0043] an isolation layer, located at least between the first parts of two active structures adjacent to each other along the first direction, the isolation layer being a solid structure;

[0044] A filling layer covers the second portion of the active structure and covers a surface of the isolation layer.

[0045] In some embodiments, the isolation layer comprises:

[0046] a first isolation layer, covering the first portion of the active structure;

[0047] The second isolation layer, the first isolation layer is distributed around the periphery of the second isolation layer, and the second isolation layer protrudes from the first isolation layer in a direction perpendicular to the top surface of the substrate, and the filling layer covers the first isolation layer and covers the part of the second isolation layer protruding from the first isolation layer.

[0048] Some embodiments of the present disclosure provide a semiconductor structure and a method for forming the same. By forming an isolation layer with a solid structure and a flat top surface, there are no gaps in the isolation layer, which not only enhances the electrical isolation effect between adjacent active pillars (or active structures), but also prevents subsequently deposited conductive materials (such as conductive materials used to form conductive lines) from entering the interior of the isolation layer, thereby reducing leakage problems between adjacent storage cells, reducing mutual influence between adjacent storage cells, and achieving improvement in the electrical performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Attached Figure 1 is a flow chart of a method for forming a semiconductor structure in a specific embodiment of the present disclosure;

[0050] Attached Figure 2 -Attached Figure 8 It is a schematic diagram of the main process structure in the process of forming a semiconductor structure according to a specific embodiment of the present disclosure. DETAILED DESCRIPTION

[0051] The specific implementation of the semiconductor structure and the method for forming the same provided by the present disclosure will be described in detail below with reference to the accompanying drawings.

[0052] This specific embodiment provides a method for forming a semiconductor structure. Figure 1 is a flow chart of a method for forming a semiconductor structure in a specific embodiment of the present disclosure, Figure 2 -Attached Figure 8 Schematic diagram of the main process structure in the process of forming a semiconductor structure in the specific embodiment of the present disclosure. Figure 1-Figure 8 As shown, the method for forming the semiconductor structure comprises the following steps:

[0053] Step S11, forming a substrate 20 and a plurality of active pillars 21 on the substrate 20, with isolation trenches 22 exposing the substrate 20 between adjacent active pillars 21;

[0054] Step S12, forming an isolation layer 30 that fills the isolation trench 22, wherein the isolation layer 30 has a solid structure and a top surface of the isolation layer 30 is flat;

[0055] Step S13, forming a signal line groove 80 exposing a portion of the active pillar 21;

[0056] Step S14, forming a conductive line 73 in the signal line trench.

[0057] In some embodiments, the specific steps of forming the substrate 20 and the plurality of active pillars 21 on the substrate 20 include:

[0058] providing an initial substrate;

[0059] The initial substrate is etched to form the isolation trenches 22 including a plurality of first trenches 221 and a plurality of second trenches 222, wherein the first trenches 221 and the second trenches 222 are alternately arranged, the width of the first trenches 221 is greater than the width of the second trenches 222, and the plurality of first trenches 221 and the plurality of second trenches 222 separate the initial substrate into a plurality of active pillars 21 arranged at intervals, and the remaining initial substrate below the active pillars 21 serves as the substrate 20, such as Figure 2 As shown. Among them, Figure 2 (a) is a schematic top view after forming a plurality of active pillars 21. Figure 2 (b) in the Figure 2 (a) is a schematic cross-sectional view at position AA.

[0060] The semiconductor structure may be, but is not limited to, a DRAM. This specific embodiment takes the semiconductor structure as an example for explanation. The initial substrate may be, but is not limited to, a silicon substrate. This specific embodiment takes the initial substrate as an example for explanation. In other embodiments, the initial substrate may also be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide or SOI. The initial substrate may be etched by a dry etching process to form a plurality of first grooves 221 and a plurality of second grooves 222, and the first grooves 221 and the second grooves 222 do not penetrate the initial substrate, and the first grooves 221 and the second grooves 222 do not penetrate the initial substrate along the fifth direction D5. The remaining unetched initial substrate below the first grooves 221 and the second grooves 222 is used as the substrate 20. The fifth direction D5 is perpendicular to the top surface of the substrate 20. The top surface of the substrate 20 refers to the surface of the substrate 20 facing the active pillar 21.

[0061] The first grooves 221 and the second grooves 222 are arranged alternately at least along the first direction D1, the first grooves 221 extend along the third direction D3, and the second grooves 222 extend along the second direction D2. The plurality of the first grooves 221 and the plurality of the second grooves 222 separate the initial substrate into a plurality of the active pillars 21. The active pillars 21 extend along the second direction D2, and the plurality of the active pillars 21 are arranged in an array along the second direction D2 and the third direction D3. The first direction D1, the second direction D2 and the third direction D3 are all parallel to the top surface of the substrate, and any two directions of the first direction D1, the second direction D2 and the third direction D3 intersect. The projection of each active pillar 21 on the top surface of the substrate 20 extends along the second direction D2. Two adjacent active pillars 21 along the third direction D3 are at least partially staggered to increase the arrangement density of the active pillars 21 while reducing the coupling effect between adjacent active pillars 21.

[0062] In some embodiments, the aspect ratio of the first trench 221 is less than 15:1.

[0063] In some embodiments, the aspect ratio of the first trench 221 is (10-11):1.

[0064] In one example, the aspect ratio of the first trench 221 refers to the ratio between the depth of the first trench 221 along the fifth direction D5 and the width CD2 along the third direction D3. In one example, the width CD2 of the first trench 221 along the third direction D3 can be increased by reducing the width CD1 of the active pillar 21 along the third direction D3, thereby reducing the aspect ratio of the first trench 221. In this specific embodiment, the aspect ratio of the first trench 221 is set to be less than 15:1, for example, the aspect ratio of the first trench 221 is (10-11):1, so that in the subsequent process of filling the isolation layer 30 in the first trench 221, the problem of gaps in the isolation layer 30 due to the excessive aspect ratio of the first trench 221 is avoided, so that the isolation layer 30 subsequently formed in the first trench 221 is a solid structure, and the top surface of the isolation layer 30 is flat and has no gaps. In addition, by increasing the width CD2 of the first trench 221 along the third direction D3, the interval width between adjacent active pillars 21 can be increased, thereby reducing the mutual influence between adjacent active pillars 21, thereby further improving the performance of the semiconductor structure.

[0065] In some embodiments, the specific steps of forming the isolation layer 30 that fills the isolation trench 22 include:

[0066] forming a first isolation layer 31 covering the inner wall of the first trench 221 and filling the second trench 222;

[0067] A second isolation layer 32 is formed to fill the remaining first groove 221, the second isolation layer 32 has a solid structure and the top surface of the second isolation layer 32 is flat, and the first isolation layer 31 and the second isolation layer 32 together serve as the isolation layer 30. Figure 3 As shown. Among them, Figure 3 (a) is a schematic top view after forming a plurality of the first isolation layers 31 and the second isolation layers 32. Figure 3 (b) in the Figure 3 (a) is a schematic cross-sectional view at position AA.

[0068] For example, after forming the first trench 221 and the second trench 222, the active pillar 21 may be treated by an in-situ water gas generation (ISSG) process to form a first oxide layer covering the inner wall of the first trench 221 and the inner wall of the second trench 222. Afterwards, an oxide material (e.g., silicon dioxide) may be deposited in the first trench 221 and the second trench 222 by an atomic layer deposition process to form a second oxide layer covering the first oxide layer. The first oxide layer and the second oxide layer together constitute the first isolation layer 31. The first isolation layer 31 fills the second trench 222. Since the width of the first trench 221 is greater than the width of the second trench 222, the first isolation layer 31 does not fill the first trench 221. Next, a nitride material (e.g., silicon nitride) may be deposited in the first trench 221 by an atomic layer deposition process to form the second isolation layer 32 covering the surface of the first isolation layer 31 and filling the remaining first trench 221. The material of the first isolation layer 31 and the material of the second isolation layer 32 should have a high etching selectivity ratio (for example, an etching selectivity ratio greater than 3) to facilitate subsequent selective etching of the first isolation layer 31 .

[0069] Since the aspect ratio of the first trench 221 is set to be less than 15:1 in this specific embodiment, when the second isolation layer 32 is deposited in the first trench 221, a seam can be avoided in the second isolation layer 32, so that the second isolation layer 32 and the isolation layer 30 formed are solid structures as a whole, and the top surfaces of the second isolation layer 32 and the isolation layer 30 as a whole are flat, which can not only improve the structural stability of the isolation layer 30 as a whole, but also prevent the subsequent deposited conductive material from entering the interior of the isolation layer 30, thereby reducing the influence between adjacent storage cells and avoiding the contact area between the conductive material and the substrate 20, thereby further improving the performance of the semiconductor structure. In this specific embodiment, the isolation layer 30 has a solid structure, which means that there are no air gaps and seams in the isolation layer 30. The top surface of the isolation layer 30 is flat, which means that there is no seam extending from the top surface of the isolation layer 30 to the inside of the isolation layer 30 in the top surface of the isolation layer 30 (that is, the surface of the isolation layer 30 away from the substrate 20).

[0070] In some embodiments, before forming the signal line trench 80 exposing a portion of the active pillar 21 in the isolation layer 30, the following steps are also included:

[0071] The isolation layer 30 is partially etched back to form a third trench 40 exposing a portion of the active pillar 21. Figure 4 As shown, Figure 4(a) is a schematic top view after the third groove 40 is formed. Figure 4 (b) in the Figure 4 (a) is a schematic cross-sectional view at position AA;

[0072] At least increasing the width of the exposed active pillar 21;

[0073] A filling layer 60 is formed to fill the third trench 40. Figure 6 As shown, Figure 6 (a) is a schematic top view after the filling layer 60 is formed. Figure 6 (b) in the Figure 6 (a) is a schematic cross-sectional view at position AA.

[0074] The following description is made by taking the case where the material of the first isolation layer 31 is silicon dioxide and the material of the second isolation layer 32 is silicon nitride as an example. After forming the isolation layer 30, a wet etching process can be used to selectively etch back a portion of the first isolation layer 31 to reduce the height of the first isolation layer 31, thereby forming the third trench 40 located between the active pillar 21 and the second isolation layer 32 and between portions of the adjacent active pillars 21. Figure 4 As shown. In the wet etching process, in order to further avoid damage to the second isolation layer 32 and the active pillar 21, DHF (Dilute HydroFluoric acid) can be used as an etchant. By etching away part of the first isolation layer 31, the upper part of the active pillar 21 is exposed, providing space for subsequently increasing the width of the active pillar 21. In this specific embodiment, the first isolation layer 31 and the second isolation layer 32 with different etching rates are used to jointly constitute the isolation layer 30, and the upper part of the active pillar 21 is exposed by etching back part of the first isolation layer 31. The remaining second isolation layer 32 protrudes from the remaining first isolation layer 31 along the fifth direction D5. The remaining second isolation layer 32 can isolate the adjacent active pillars 21 on the one hand, and on the other hand, it can also limit the width of the epitaxial layer 50 formed subsequently to avoid the size of the storage unit being too large. After forming the third trench 40, the width of the active pillar 21 exposed by the third trench 40 (for example, the width of the active pillar 21 along the first direction D1) can be increased, thereby increasing the contact area between the active pillar 21 and the charge storage structure in the future to reduce the contact resistance. After increasing the width of the exposed active pillar 21, the third trench 40 can be filled by depositing the filling layer 60 to prevent the active pillar 21 with the increased width from being affected by the external environment.

[0075] In some embodiments, the specific steps of forming the third trench 40 of the exposed portion of the active pillar 21 include:

[0076] Part of the first isolation layer 31 is etched back to form a third trench 40 exposing a portion of the active pillar 21 .

[0077] In some embodiments, the specific steps of at least increasing the width of the exposed active pillar 21 include:

[0078] The exposed active pillar 21 is processed by an epitaxial process to form an epitaxial layer 50 covering the surface of the exposed active pillar 21. Figure 5 As shown. Among them, Figure 5 (a) is a schematic top view after the epitaxial layer 50 is formed. Figure 5 (b) in the Figure 5 (a) is a schematic cross-sectional view at position AA.

[0079] For example, after forming the third trench 40, the epitaxial layer 50 may be formed on the exposed surface of the active pillar 21 by an epitaxial growth process to form an active structure 76 including the active pillar 21 and the epitaxial layer 50. Along the fifth direction D5, the active structure 76 includes a first portion 74 and a second portion 75 located above the first portion 74, wherein the width of the first portion 74 at least along the first direction D1 is smaller than the width of the second portion 75 along the first direction D1. The first portion 74 includes only a portion of the active pillar 21, and the second portion 75 includes a portion of the active pillar 21 located above the first portion 74 and the epitaxial layer 50. By forming the epitaxial layer 50 covering the active pillar 21 on the upper part of the active pillar 21, the width of the top of the active structure 76 can be increased (for example, the width of the top of the active structure 76 along the first direction D1 is increased) to increase the contact area between the bit line structure and / or charge storage structure subsequently formed above the active structure 76 and the active structure 76 to reduce the contact resistance. Wherein, the charge storage structure can be but is not limited to a capacitor. The storage unit includes the active structure 76, and the charge storage structure located above the active structure 76 and electrically connected to the active structure 76. In one example, the epitaxial layer 50 covers the entire surface of the exposed active pillar 21. After forming the epitaxial layer 50, any one of an in-situ water vapor generation process and an atomic layer deposition process or a combination of the two can be used to form the filling layer 60 that fills the third trench 40 and covers the active structure 76 and the remaining isolation layer 30, such as Figure 6In one example, the material of the filling layer 60 may be an oxide material, such as silicon dioxide. In one example, the top surface of the filling layer 60 is flat, and the filling layer 60 is a solid structure.

[0080] This specific embodiment is described by taking the example of using an epitaxial process to process the exposed active pillar 21 to form an epitaxial layer 50 covering the surface of the exposed active pillar 21 to increase the width of the top of the active pillar 21 along the first direction D1. In other specific embodiments, those skilled in the art may also use other methods such as a deposition process to increase the width of the top of the active pillar 21 along the first direction D1.

[0081] In some embodiments, the first trenches 221 and the second trenches 222 are arranged at intervals along the first direction D1, and the width of the epitaxial layer 50 along at least the first direction D1 is smaller than the width of the third trench 40 along the first direction D1. With this structure, on the one hand, the size of the active structure 76 can be prevented from being too large; on the other hand, the two adjacent active structures 76 can be fully isolated, further reducing the mutual influence between the adjacent active structures 76. In one example, the width of the epitaxial layer 50 along the first direction D1 is smaller than 1 / 2 of the width of the third trench 40 along the first direction D1.

[0082] In some embodiments, the projection of the active pillar 21 on the top surface of the substrate 20 extends along the second direction D2, and the active pillar 21 includes a channel region and a source / drain region distributed outside the channel region along the second direction D2; the specific steps of forming a signal line trench exposing a portion of the active pillar 21 include:

[0083] The isolation layer 30 and the channel region in the active pillar 21 are etched to reduce the height of the channel region in the active pillar 21 , thereby forming the signal line trench 80 that at least exposes the remaining channel region in the active pillar 21 .

[0084] For example, the active structure 76 includes a channel region, and a first source-drain region and a second source-drain region distributed outside the channel region along the second direction D2, and the first source-drain region and the second source-drain region together constitute the source-drain region. The first source-drain region is used to be electrically connected to a bit line structure, and the second source-drain region is used to be electrically connected to a charge storage structure (e.g., a capacitor). After forming the filling layer 60, part of the filling layer 60, part of the second isolation layer 32, and part of the active structure 76 are etched back to reduce the height of the channel region in the active structure 76, so as to form the signal line groove 80 located at least between the first source-drain region and the second source-drain region and exposing the channel region in the active structure 76, as shown in FIG. Figure 7As shown. Among them, Figure 7 is a schematic top view after forming the signal line groove 80. After forming the signal line groove 80, the height of the source and drain regions (including the first source and drain regions and the second source and drain regions) in the active structure is greater than the height of the channel region, that is, along the fifth direction D5, the top surface of the source and drain regions is located above the top surface of the channel region.

[0085] In some embodiments, the specific steps of forming the conductive line 73 in the signal line trench 80 include:

[0086] forming a gate dielectric layer covering the remaining channel region in the signal line trench 80;

[0087] forming a conductive material layer covering the gate dielectric layer;

[0088] A signal line cover layer 72 is formed to cover the conductive material layer. The conductive material layer and the signal line cover layer 72 together constitute the conductive line 73 .

[0089] In some embodiments, the conductive material layer includes a first conductive material layer 70 and a second conductive material layer 71 covering the first conductive material layer 70 .

[0090] For example, after forming the signal line trench 80, a gate dielectric layer is formed above the exposed channel region along the signal line trench 80. Next, a first conductive material layer 70 covering the gate dielectric layer, a second conductive material layer 71 covering the first conductive material layer 70, and a signal line capping layer 72 covering the second conductive material layer 71 are formed in the signal line trench. Figure 8 As shown. The first conductive material layer 70, the second conductive material layer 71 and the signal line cover layer 72 together constitute the conductive line 73. The conductive line 73 extends along the first direction D1, and a plurality of the conductive lines 73 are arranged at intervals along the fourth direction D4. The fourth direction D4 is parallel to the top surface of the substrate 20, and any two of the first direction D1, the second direction D2, the third direction D3 and the fourth direction D4 intersect. In one example, the material of the first conductive material layer 70 is a metal material such as tungsten, and the material of the second conductive material layer 71 is polysilicon. In one example, the conductive line 73 is a word line. Among them, Figure 8 (a) is a schematic top view after the conductive line 73 is formed. Figure 8 (b) in the Figure 8 (a) is a schematic cross-sectional view at the AA position. Figure 8 (c) in Figure 8 (a) is a schematic cross-sectional view at the BB position. Figure 8(d) in is Figure 8 (a) Schematic diagram of the cross section at the CC position.

[0091] This specific embodiment also provides a semiconductor structure. The semiconductor structure in this specific embodiment can be used as follows Figure 1-Figure 8 The semiconductor structure is formed by the method of forming the semiconductor structure shown in FIG. Figure 2-Figure 8 .like Figure 2-Figure 8 As shown, the semiconductor structure comprises:

[0092] Substrate 20;

[0093] A plurality of active structures 76 are disposed on the substrate 20 and arranged at intervals. The plurality of active structures 76 are arranged at intervals at least along a first direction D1. The active structure 76 includes a first portion 74 and a second portion 75 disposed above the first portion 74. The width of the second portion 75 at least along the first direction D1 is greater than the width of the second portion 75 along the first direction D1.

[0094] An isolation structure, located on the substrate 20 and distributed between adjacent active structures 76, wherein the isolation structure is a solid structure, and a top surface of the isolation structure is flat;

[0095] The conductive line 73 is located on the substrate 20 and covers the active structure 76 .

[0096] The semiconductor structure may be, but is not limited to, a DRAM. This specific embodiment is described by taking the semiconductor structure being a DRAM as an example. The substrate 20 may be, but is not limited to, a silicon substrate. This specific embodiment is described by taking the substrate 20 being a silicon substrate as an example. In other embodiments, the substrate 20 may also be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide or SOI. The substrate 20 has an active array, and the active array includes a plurality of active structures 76 arranged in an array along the second direction D2 and the third direction D3. The isolation structure is located between two adjacent active structures 76 and is used to isolate adjacent active structures 76. The isolation structure is a solid structure, that is, there is no air gap in the isolation structure, and there is no conductive material for forming the conductive wire 73 in the isolation structure, thereby avoiding mutual influence between adjacent active structures 76, and also avoiding electrical connection between the conductive wire 73 and the substrate 20, and can also enhance the overall stability of the semiconductor structure. A plurality of the conductive lines 73 are located on the substrate 20, each of the conductive lines 73 extends along the first direction D1, and the plurality of conductive lines 73 are arranged at intervals along a fourth direction D4. The fourth direction D4 is parallel to the top surface of the substrate 20, and any two of the first direction D1, the second direction D2, the third direction D3 and the fourth direction D4 intersect. In one example, the conductive line 76 is a word line. By setting the width of the second portion 75 in the active structure 76 at least along the first direction D1 to be greater than the width of the second portion 75 along the first direction D1, the subsequent contact area between the active pillar 21 and the charge storage structure is increased to reduce the contact resistance, so as to further improve the electrical performance of the semiconductor structure.

[0097] In some embodiments, the active structure comprises:

[0098] An active pillar 21, located on the substrate 20 and extending in a direction perpendicular to the top surface of the substrate 20;

[0099] The epitaxial layer 50 covers the upper portion of the active pillar 21 . The epitaxial layer 50 and the active pillar 21 covered by the epitaxial layer 50 serve as the second portion 75 . The active pillar 21 located below the second portion 75 serves as the first portion 74 .

[0100] Specifically, if Figure 8As shown, the active structure 76 includes the active pillar 21 extending along the fifth direction D5, and the epitaxial layer 50 distributed around the periphery of the active pillar 21. The fifth direction D5 is perpendicular to the top surface of the substrate 20. Along the fifth direction D5, the active structure 76 includes a first portion 74 and a second portion 75 located above the first portion 74, wherein the width of the first portion 74 at least along the first direction D1 is smaller than the width of the second portion 75 along the first direction D1. The first portion 74 includes only part of the active pillar 21, and the second portion 75 includes part of the active pillar 21 located above the first portion 74, and the epitaxial layer 50. By forming the epitaxial layer 50 covering the active pillar 21 on the upper part of the active pillar 21, the width of the top of the active structure 76 can be increased (for example, the width of the top of the active structure 76 along the first direction D1 is increased), so as to increase the contact area between the bit line structure and / or charge storage structure subsequently formed above the active structure 76 and the active structure 76, so as to reduce the contact resistance. The charge storage structure can be, but is not limited to, a capacitor.

[0101] In one example, the projection of the active structure 76 on the top surface of the substrate 20 extends along the second direction D2, and the active structure 76 includes a channel region, and a first source and drain region and a second source and drain region distributed outside the channel region along the second direction D2, and the first source and drain region and the second source and drain region together constitute the source and drain region. The first source and drain region is used to be electrically connected to the bit line structure, and the second source and drain region is used to be electrically connected to the charge storage structure (such as a capacitor). The height of the source and drain region (including the first source and drain region and the second source and drain region) in the active structure is greater than the height of the channel region, that is, along the fifth direction D5, the top surface of the source and drain region is located above the top surface of the channel region. The semiconductor structure also includes a gate dielectric layer covering the channel region. The conductive line 73 includes a first conductive material layer 70 located on the gate dielectric layer, a second conductive material layer 71 located on the first conductive material layer 70, and a signal line cap layer 72 covering the second conductive material layer 71. In one example, the material of the first conductive material layer 70 is a metal material such as tungsten, and the material of the second conductive material layer 71 is polysilicon. In one example, the material of the signal line cap layer 73 can be a nitride material, such as silicon nitride.

[0102] In some embodiments, the isolation structure comprises:

[0103] The isolation layer 30 is at least located between the first portions 74 of two adjacent active structures 76 along the first direction D1, and the isolation layer 30 is a solid structure;

[0104] The filling layer 60 covers the second portion 75 in the active structure 76 and covers the surface of the isolation layer 30 .

[0105] In some embodiments, the isolation layer 30 includes:

[0106] A first isolation layer 31, covering the first portion 74 of the active structure 76;

[0107] The second isolation layer 32, the first isolation layer 31 is distributed around the periphery of the second isolation layer 32, and the second isolation layer 32 protrudes from the first isolation layer 31 in a direction perpendicular to the top surface of the substrate 20, and the filling layer 60 covers the first isolation layer 31 and covers the portion of the second isolation layer 32 protruding from the first isolation layer 31. In one example, the material of the first isolation layer 31 is an oxide material, such as silicon dioxide. The material of the second isolation layer 32 is a nitride material, such as silicon nitride.

[0108] The semiconductor structure and the method for forming the same provided in some embodiments of the present specific implementation manner form an isolation layer having a solid structure and a flat top surface so that there are no gaps in the isolation layer, thereby not only enhancing the electrical isolation effect between adjacent active pillars (or active structures), but also preventing subsequently deposited conductive materials (such as conductive materials used to form conductive lines) from entering the interior of the isolation layer, thereby reducing leakage problems between adjacent storage cells, reducing mutual influence between adjacent storage cells, and achieving improvement in the electrical performance of the semiconductor structure.

[0109] The above is only a preferred embodiment of the present disclosure. It should be pointed out that a person skilled in the art can make several improvements and modifications without departing from the principle of the present disclosure. These improvements and modifications should also be regarded as within the scope of protection of the present disclosure.

Claims

1. A method for forming a semiconductor structure, characterized in that: The steps include: forming a substrate and a plurality of active pillars on the substrate, wherein adjacent active pillars have isolation trenches between them for exposing the substrate; forming an isolation layer that fills the isolation trench, wherein the isolation layer has a solid structure and a top surface of the isolation layer is flat; forming a signal line groove exposing a portion of the active pillar; A conductive line is formed in the signal line groove.

2. The method for forming a semiconductor structure according to claim 1, wherein: The specific steps of forming a substrate and a plurality of active pillars on the substrate include: providing an initial substrate; The initial substrate is etched to form the isolation trenches including a plurality of first trenches and a plurality of second trenches, wherein the first trenches and the second trenches are alternately arranged, the width of the first trenches is greater than the width of the second trenches, and the plurality of first trenches and the plurality of second trenches separate the initial substrate into a plurality of active pillars arranged at intervals, and the remaining initial substrate below the active pillars serves as the substrate.

3. The method for forming a semiconductor structure according to claim 2, wherein: The aspect ratio of the first trench is less than 15:

1.

4. The method for forming a semiconductor structure according to claim 3, characterized in that: The aspect ratio of the first groove is (10-11):

1.

5. The method for forming a semiconductor structure according to claim 2, wherein: The specific steps of forming the isolation layer that fills the isolation trench include: forming a first isolation layer covering the inner wall of the first trench and filling the second trench; A second isolation layer is formed to fill the remaining first trench, wherein the second isolation layer has a solid structure and a top surface of the second isolation layer is flat, and the first isolation layer and the second isolation layer together serve as the isolation layer.

6. The method for forming a semiconductor structure according to claim 5, characterized in that: Before forming a signal line trench of the active pillar that exposes a portion of the signal line trench in the isolation layer, the method further includes the following steps: Etching back a portion of the isolation layer to form a third trench exposing a portion of the active pillar; At least increasing the width of the exposed active pillar; A filling layer is formed to completely fill the third trench.

7. The method for forming a semiconductor structure according to claim 6, wherein: The specific steps of forming the third trench of the active pillar of the exposed portion include: Part of the first isolation layer is etched back to form a third trench exposing a portion of the active pillar.

8. The method for forming a semiconductor structure according to claim 6, wherein: The specific steps of at least increasing the width of the exposed active pillars include: The exposed active pillars are processed by an epitaxial process to form epitaxial layers covering surfaces of the exposed active pillars.

9. The method for forming a semiconductor structure according to claim 6, wherein: The first trenches and the second trenches are arranged at intervals along a first direction, and a width of the epitaxial layer at least along the first direction is smaller than a width of the third trench along the first direction.

10. The method for forming a semiconductor structure according to claim 1, wherein: The projection of the active pillar on the top surface of the substrate extends along a second direction, and the active pillar includes a channel region and a source and drain region distributed outside the channel region along the second direction; The specific steps of forming a signal line groove exposing a portion of the active pillar include: The isolation layer and the channel region in the active pillar are etched to reduce the height of the channel region in the active pillar and form the signal line trench that at least exposes the remaining channel region in the active pillar.

11. The method for forming a semiconductor structure according to claim 1, wherein: The specific steps of forming a conductive line in the signal line groove include: forming a gate dielectric layer covering the remaining channel region in the signal line trench; forming a conductive material layer covering the gate dielectric layer; A signal line cover layer is formed to cover the conductive material layer, and the conductive material layer and the signal line cover layer together constitute the conductive line.

12. A semiconductor structure, characterized in that: include: substrate; A plurality of active structures are located on the substrate, and the plurality of active structures are arranged at intervals, and the plurality of active structures are arranged at intervals at least along a first direction, and the active structure comprises a first portion and a second portion located above the first portion, and the width of the second portion at least along the first direction is greater than the width of the second portion along the first direction; An isolation structure, located on the substrate and distributed between adjacent active structures, wherein the isolation structure is a solid structure and a top surface of the isolation structure is flat; The conductive line is located on the substrate and covers the active structure.

13. The semiconductor structure according to claim 12, characterized in that: The active structure comprises: an active pillar, located on the substrate and extending in a direction perpendicular to a top surface of the substrate; An epitaxial layer covers an upper portion of the active pillar, the epitaxial layer and the active pillar covered by the epitaxial layer serve as the second portion, and the active pillar located below the second portion serves as the first portion.

14. The semiconductor structure according to claim 13, characterized in that: The isolation structure comprises: an isolation layer, located at least between the first parts of two active structures adjacent to each other along the first direction, the isolation layer being a solid structure; A filling layer covers the second portion of the active structure and covers a surface of the isolation layer.

15. The semiconductor structure according to claim 14, characterized in that: The isolation layer comprises: a first isolation layer, covering the first portion of the active structure; The second isolation layer, the first isolation layer is distributed around the periphery of the second isolation layer, and the second isolation layer protrudes from the first isolation layer in a direction perpendicular to the top surface of the substrate, and the filling layer covers the first isolation layer and covers the part of the second isolation layer protruding from the first isolation layer.

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